.. | .. |
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1 | 1 | // SPDX-License-Identifier: GPL-2.0 |
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2 | 2 | /* |
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3 | | - * SAMSUNG EXYNOS5260 SoC device tree source |
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| 3 | + * Samsung Exynos5260 SoC device tree source |
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4 | 4 | * |
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5 | 5 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. |
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6 | 6 | * http://www.samsung.com |
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.. | .. |
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17 | 17 | #size-cells = <1>; |
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18 | 18 | |
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19 | 19 | aliases { |
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| 20 | + i2c0 = &hsi2c_0; |
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| 21 | + i2c1 = &hsi2c_1; |
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| 22 | + i2c2 = &hsi2c_2; |
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| 23 | + i2c3 = &hsi2c_3; |
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20 | 24 | pinctrl0 = &pinctrl_0; |
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21 | 25 | pinctrl1 = &pinctrl_1; |
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22 | 26 | pinctrl2 = &pinctrl_2; |
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.. | .. |
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158 | 162 | }; |
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159 | 163 | |
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160 | 164 | gic: interrupt-controller@10481000 { |
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161 | | - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; |
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| 165 | + compatible = "arm,gic-400", "arm,cortex-a15-gic"; |
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162 | 166 | #interrupt-cells = <3>; |
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163 | | - #address-cells = <0>; |
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164 | | - #size-cells = <0>; |
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165 | 167 | interrupt-controller; |
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166 | 168 | reg = <0x10481000 0x1000>, |
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167 | 169 | <0x10482000 0x2000>, |
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.. | .. |
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176 | 178 | reg = <0x10000000 0x100>; |
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177 | 179 | }; |
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178 | 180 | |
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179 | | - mct: mct@100b0000 { |
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| 181 | + mct: timer@100b0000 { |
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180 | 182 | compatible = "samsung,exynos4210-mct"; |
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181 | 183 | reg = <0x100B0000 0x1000>; |
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182 | 184 | clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; |
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.. | .. |
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288 | 290 | #size-cells = <0>; |
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289 | 291 | clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; |
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290 | 292 | clock-names = "biu", "ciu"; |
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| 293 | + assigned-clocks = |
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| 294 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>, |
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| 295 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>, |
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| 296 | + <&clock_top TOP_SCLK_MMC0>; |
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| 297 | + assigned-clock-parents = |
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| 298 | + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, |
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| 299 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>; |
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| 300 | + assigned-clock-rates = <0>, <0>, <800000000>; |
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291 | 301 | fifo-depth = <64>; |
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292 | 302 | status = "disabled"; |
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293 | 303 | }; |
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.. | .. |
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300 | 310 | #size-cells = <0>; |
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301 | 311 | clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; |
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302 | 312 | clock-names = "biu", "ciu"; |
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| 313 | + assigned-clocks = |
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| 314 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>, |
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| 315 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>, |
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| 316 | + <&clock_top TOP_SCLK_MMC1>; |
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| 317 | + assigned-clock-parents = |
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| 318 | + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, |
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| 319 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>; |
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| 320 | + assigned-clock-rates = <0>, <0>, <800000000>; |
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303 | 321 | fifo-depth = <64>; |
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304 | 322 | status = "disabled"; |
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305 | 323 | }; |
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.. | .. |
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312 | 330 | #size-cells = <0>; |
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313 | 331 | clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; |
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314 | 332 | clock-names = "biu", "ciu"; |
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| 333 | + assigned-clocks = |
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| 334 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>, |
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| 335 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>, |
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| 336 | + <&clock_top TOP_SCLK_MMC2>; |
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| 337 | + assigned-clock-parents = |
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| 338 | + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, |
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| 339 | + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>; |
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| 340 | + assigned-clock-rates = <0>, <0>, <800000000>; |
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315 | 341 | fifo-depth = <64>; |
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316 | 342 | status = "disabled"; |
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317 | 343 | }; |
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| 344 | + |
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| 345 | + hsi2c_0: hsi2c@12da0000 { |
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| 346 | + compatible = "samsung,exynos5260-hsi2c"; |
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| 347 | + reg = <0x12DA0000 0x1000>; |
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| 348 | + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
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| 349 | + #address-cells = <1>; |
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| 350 | + #size-cells = <0>; |
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| 351 | + pinctrl-names = "default"; |
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| 352 | + pinctrl-0 = <&i2c0_hs_bus>; |
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| 353 | + clocks = <&clock_peri PERI_CLK_HSIC0>; |
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| 354 | + clock-names = "hsi2c"; |
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| 355 | + status = "disabled"; |
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| 356 | + }; |
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| 357 | + |
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| 358 | + hsi2c_1: hsi2c@12db0000 { |
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| 359 | + compatible = "samsung,exynos5260-hsi2c"; |
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| 360 | + reg = <0x12DB0000 0x1000>; |
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| 361 | + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
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| 362 | + #address-cells = <1>; |
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| 363 | + #size-cells = <0>; |
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| 364 | + pinctrl-names = "default"; |
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| 365 | + pinctrl-0 = <&i2c1_hs_bus>; |
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| 366 | + clocks = <&clock_peri PERI_CLK_HSIC1>; |
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| 367 | + clock-names = "hsi2c"; |
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| 368 | + status = "disabled"; |
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| 369 | + }; |
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| 370 | + |
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| 371 | + hsi2c_2: hsi2c@12dc0000 { |
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| 372 | + compatible = "samsung,exynos5260-hsi2c"; |
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| 373 | + reg = <0x12DC0000 0x1000>; |
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| 374 | + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
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| 375 | + #address-cells = <1>; |
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| 376 | + #size-cells = <0>; |
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| 377 | + pinctrl-names = "default"; |
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| 378 | + pinctrl-0 = <&i2c2_hs_bus>; |
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| 379 | + clocks = <&clock_peri PERI_CLK_HSIC2>; |
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| 380 | + clock-names = "hsi2c"; |
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| 381 | + status = "disabled"; |
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| 382 | + }; |
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| 383 | + |
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| 384 | + hsi2c_3: hsi2c@12dd0000 { |
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| 385 | + compatible = "samsung,exynos5260-hsi2c"; |
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| 386 | + reg = <0x12DD0000 0x1000>; |
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| 387 | + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
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| 388 | + #address-cells = <1>; |
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| 389 | + #size-cells = <0>; |
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| 390 | + pinctrl-names = "default"; |
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| 391 | + pinctrl-0 = <&i2c3_hs_bus>; |
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| 392 | + clocks = <&clock_peri PERI_CLK_HSIC3>; |
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| 393 | + clock-names = "hsi2c"; |
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| 394 | + status = "disabled"; |
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| 395 | + }; |
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318 | 396 | }; |
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319 | 397 | }; |
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320 | 398 | |
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