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2023-12-09 958e46acc8e900e8569dd467c1af9b8d2d019394 
 kernel/include/linux/rtsx_pci.h
....@@ -1,19 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /* Driver for Realtek PCI-Express card reader
23  *
34  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License as published by the
7
- * Free Software Foundation; either version 2, or (at your option) any
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- * later version.
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- *
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- * This program is distributed in the hope that it will be useful, but
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- * WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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- * General Public License for more details.
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- *
15
- * You should have received a copy of the GNU General Public License along
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- * with this program; if not, see <http://www.gnu.org/licenses/>.
175  *
186  * Author:
197  *   Wei WANG <wei_wang@realsil.com.cn>
....@@ -110,18 +98,6 @@
11098 	iowrite8(value, (pcr)->remap_addr + reg)
11199 #define rtsx_pci_readb(pcr, reg) \
112100 	ioread8((pcr)->remap_addr + reg)
113
-
114
-#define rtsx_pci_read_config_byte(pcr, where, val) \
115
-	pci_read_config_byte((pcr)->pci, where, val)
116
-
117
-#define rtsx_pci_write_config_byte(pcr, where, val) \
118
-	pci_write_config_byte((pcr)->pci, where, val)
119
-
120
-#define rtsx_pci_read_config_dword(pcr, where, val) \
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-	pci_read_config_dword((pcr)->pci, where, val)
122
-
123
-#define rtsx_pci_write_config_dword(pcr, where, val) \
124
-	pci_write_config_dword((pcr)->pci, where, val)
125101 
126102 #define STATE_TRANS_NONE		0
127103 #define STATE_TRANS_CMD			1
....@@ -317,6 +293,8 @@
317293 #define   SD30_CLK_STOP_CFG0		0x01
318294 #define REG_PRE_RW_MODE			0xFD70
319295 #define EN_INFINITE_MODE		0x01
296
+#define REG_CRC_DUMMY_0		0xFD71
297
+#define CFG_SD_POW_AUTO_PD		(1<<0)
320298 
321299 #define SRCTL				0xFC13
322300 
....@@ -611,6 +589,7 @@
611589 
612590 #define ASPM_FORCE_CTL			0xFE57
613591 #define   FORCE_ASPM_CTL0		0x10
592
+#define   FORCE_ASPM_CTL1		0x20
614593 #define   FORCE_ASPM_VAL_MASK		0x03
615594 #define   FORCE_ASPM_L1_EN		0x02
616595 #define   FORCE_ASPM_L0_EN		0x01
....@@ -678,6 +657,11 @@
678657 #define   RESET_PIN_WAKE		0x02
679658 #define   PM_WAKE_EN			0x01
680659 #define PM_CTRL4			0xFF47
660
+
661
+#define REG_CFG_OOBS_OFF_TIMER 0xFEA6
662
+#define REG_CFG_OOBS_ON_TIMER 0xFEA7
663
+#define REG_CFG_VCM_ON_TIMER 0xFEA8
664
+#define REG_CFG_OOBS_POLLING 0xFEA9
681665 
682666 /* Memory mapping */
683667 #define SRAM_BASE			0xE600
....@@ -1053,10 +1037,6 @@
10531037 #define   PHY_DIG1E_RX_EN_KEEP		0x0001
10541038 #define PHY_DUM_REG			0x1F
10551039 
1056
-#define PCR_ASPM_SETTING_REG1		0x160
1057
-#define PCR_ASPM_SETTING_REG2		0x168
1058
-#define PCR_ASPM_SETTING_5260		0x178
1059
-
10601040 #define PCR_SETTING_REG1		0x724
10611041 #define PCR_SETTING_REG2		0x814
10621042 #define PCR_SETTING_REG3		0x747
....@@ -1092,11 +1072,7 @@
10921072 	void		(*stop_cmd)(struct rtsx_pcr *pcr);
10931073 
10941074 	void (*set_aspm)(struct rtsx_pcr *pcr, bool enable);
1095
-	int (*set_ltr_latency)(struct rtsx_pcr *pcr, u32 latency);
1096
-	int (*set_l1off_sub)(struct rtsx_pcr *pcr, u8 val);
10971075 	void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active);
1098
-	void (*full_on)(struct rtsx_pcr *pcr);
1099
-	void (*power_saving)(struct rtsx_pcr *pcr);
11001076 	void (*enable_ocp)(struct rtsx_pcr *pcr);
11011077 	void (*disable_ocp)(struct rtsx_pcr *pcr);
11021078 	void (*init_ocp)(struct rtsx_pcr *pcr);
....@@ -1107,11 +1083,6 @@
11071083 
11081084 enum PDEV_STAT  {PDEV_STAT_IDLE, PDEV_STAT_RUN};
11091085 
1110
-#define ASPM_L1_1_EN_MASK		BIT(3)
1111
-#define ASPM_L1_2_EN_MASK		BIT(2)
1112
-#define PM_L1_1_EN_MASK		BIT(1)
1113
-#define PM_L1_2_EN_MASK		BIT(0)
1114
-
11151086 #define ASPM_L1_1_EN			BIT(0)
11161087 #define ASPM_L1_2_EN			BIT(1)
11171088 #define PM_L1_1_EN				BIT(2)
....@@ -1119,13 +1090,6 @@
11191090 #define LTR_L1SS_PWR_GATE_EN	BIT(4)
11201091 #define L1_SNOOZE_TEST_EN		BIT(5)
11211092 #define LTR_L1SS_PWR_GATE_CHECK_CARD_EN	BIT(6)
1122
-
1123
-enum dev_aspm_mode {
1124
-	DEV_ASPM_DYNAMIC,
1125
-	DEV_ASPM_BACKDOOR,
1126
-	DEV_ASPM_STATIC,
1127
-	DEV_ASPM_DISABLE,
1128
-};
11291093 
11301094 /*
11311095  * struct rtsx_cr_option  - card reader option
....@@ -1137,7 +1101,6 @@
11371101  * @ltr_active_latency: ltr mode active latency
11381102  * @ltr_idle_latency: ltr mode idle latency
11391103  * @ltr_l1off_latency: ltr mode l1off latency
1140
- * @dev_aspm_mode: device aspm mode
11411104  * @l1_snooze_delay: l1 snooze delay
11421105  * @ltr_l1off_sspwrgate: ltr l1off sspwrgate
11431106  * @ltr_l1off_snooze_sspwrgate: ltr l1off snooze sspwrgate
....@@ -1154,7 +1117,6 @@
11541117 	u32 ltr_active_latency;
11551118 	u32 ltr_idle_latency;
11561119 	u32 ltr_l1off_latency;
1157
-	enum dev_aspm_mode dev_aspm_mode;
11581120 	u32 l1_snooze_delay;
11591121 	u8 ltr_l1off_sspwrgate;
11601122 	u8 ltr_l1off_snooze_sspwrgate;
....@@ -1183,7 +1145,6 @@
11831145 struct rtsx_pcr {
11841146 	struct pci_dev			*pci;
11851147 	unsigned int			id;
1186
-	int				pcie_cap;
11871148 	struct rtsx_cr_option	option;
11881149 	struct rtsx_hw_param hw_param;
11891150 
....@@ -1229,6 +1190,7 @@
12291190 #define EXTRA_CAPS_MMC_HSDDR		(1 << 3)
12301191 #define EXTRA_CAPS_MMC_HS200		(1 << 4)
12311192 #define EXTRA_CAPS_MMC_8BIT		(1 << 5)
1193
+#define EXTRA_CAPS_NO_MMC		(1 << 7)
12321194 	u32				extra_caps;
12331195 
12341196 #define IC_VER_A			0
....@@ -1267,6 +1229,7 @@
12671229 	u8				dma_error_count;
12681230 	u8			ocp_stat;
12691231 	u8			ocp_stat2;
1232
+	u8			rtd3_en;
12701233 };
12711234 
12721235 #define PID_524A	0x524A
....@@ -1274,6 +1237,8 @@
12741237 #define PID_5250	0x5250
12751238 #define PID_525A	0x525A
12761239 #define PID_5260	0x5260
1240
+#define PID_5261	0x5261
1241
+#define PID_5228	0x5228
12771242 
12781243 #define CHK_PCI_PID(pcr, pid)		((pcr)->pci->device == (pid))
12791244 #define PCI_VID(pcr)			((pcr)->pci->vendor)
....@@ -1329,18 +1294,6 @@
13291294 static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
13301295 {
13311296 	return (u8 *)(pcr->host_cmds_ptr);
1332
-}
1333
-
1334
-static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr,
1335
-		u8 mask, u8 append)
1336
-{
1337
-	int err;
1338
-	u8 val;
1339
-
1340
-	err = pci_read_config_byte(pcr->pci, addr, &val);
1341
-	if (err < 0)
1342
-		return err;
1343
-	return pci_write_config_byte(pcr->pci, addr, (val & mask) | append);
13441297 }
13451298 
13461299 static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)