~hc/RK356X_SDK_RELEASE.git

..	..	@@ -5,10 +5,9 @@
5	5	*
6	6	* GPL LICENSE SUMMARY
7	7	*
8		- * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9	8	* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10	9	* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11		- * Copyright(c) 2018 Intel Corporation
	10	+ * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
12	11	*
13	12	* This program is free software; you can redistribute it and/or modify
14	13	* it under the terms of version 2 of the GNU General Public License as
..	..	@@ -19,11 +18,6 @@
19	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	19	* General Public License for more details.
21	20	*
22		- * You should have received a copy of the GNU General Public License
23		- * along with this program; if not, write to the Free Software
24		- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
25		- * USA
26		- *
27	21	* The full GNU General Public License is included in this distribution
28	22	* in the file called COPYING.
29	23	*
..	..	@@ -33,10 +27,9 @@
33	27	*
34	28	* BSD LICENSE
35	29	*
36		- * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
37	30	* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
38	31	* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
39		- * Copyright(c) 2018 Intel Corporation
	32	+ * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
40	33	* All rights reserved.
41	34	*
42	35	* Redistribution and use in source and binary forms, with or without
..	..	@@ -67,15 +60,15 @@
67	60	*
68	61	*****************************************************************************/
69	62	#include <linux/pci.h>
70		-#include <linux/pci-aspm.h>
71	63	#include <linux/interrupt.h>
72	64	#include <linux/debugfs.h>
73	65	#include <linux/sched.h>
74	66	#include <linux/bitops.h>
75	67	#include <linux/gfp.h>
76	68	#include <linux/vmalloc.h>
77		-#include <linux/pm_runtime.h>
78	69	#include <linux/module.h>
	70	+#include <linux/wait.h>
	71	+#include <linux/seq_file.h>
79	72
80	73	#include "iwl-drv.h"
81	74	#include "iwl-trans.h"
..	..	@@ -85,17 +78,21 @@
85	78	#include "iwl-agn-hw.h"
86	79	#include "fw/error-dump.h"
87	80	#include "fw/dbg.h"
	81	+#include "fw/api/tx.h"
88	82	#include "internal.h"
89	83	#include "iwl-fh.h"
	84	+#include "iwl-context-info-gen3.h"
90	85
91	86	/* extended range in FW SRAM */
92	87	#define IWL_FW_MEM_EXTENDED_START 0x40000
93	88	#define IWL_FW_MEM_EXTENDED_END 0x57FFF
94	89
95		-static void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
	90	+void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
96	91	{
97		-#define PCI_DUMP_SIZE 64
98		-#define PREFIX_LEN 32
	92	+#define PCI_DUMP_SIZE 352
	93	+#define PCI_MEM_DUMP_SIZE 64
	94	+#define PCI_PARENT_DUMP_SIZE 524
	95	+#define PREFIX_LEN 32
99	96	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
100	97	struct pci_dev *pdev = trans_pcie->pci_dev;
101	98	u32 i, pos, alloc_size, ptr, buf;
..	..	@@ -106,11 +103,15 @@
106	103
107	104	/* Should be a multiple of 4 */
108	105	BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 \|\| PCI_DUMP_SIZE & 0x3);
	106	+ BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 \|\| PCI_MEM_DUMP_SIZE & 0x3);
	107	+ BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 \|\| PCI_PARENT_DUMP_SIZE & 0x3);
	108	+
109	109	/* Alloc a max size buffer */
110		- if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE)
111		- alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
112		- else
113		- alloc_size = PCI_DUMP_SIZE + PREFIX_LEN;
	110	+ alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
	111	+ alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
	112	+ alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
	113	+ alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
	114	+
114	115	buf = kmalloc(alloc_size, GFP_ATOMIC);
115	116	if (!buf)
116	117	return;
..	..	@@ -127,7 +128,7 @@
127	128	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
128	129
129	130	IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
130		- for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
	131	+ for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
131	132	*ptr = iwl_read32(trans, i);
132	133	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
133	134
..	..	@@ -150,7 +151,7 @@
150	151
151	152	IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
152	153	pci_name(pdev));
153		- for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
	154	+ for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
154	155	if (pci_read_config_dword(pdev, i, ptr))
155	156	goto err_read;
156	157	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
..	..	@@ -183,35 +184,66 @@
183	184	static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
184	185	{
185	186	/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
186		- iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
187		- BIT(trans->cfg->csr->flag_sw_reset));
	187	+ iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
188	188	usleep_range(5000, 6000);
189	189	}
190	190
191	191	static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
192	192	{
193		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	193	+ struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
194	194
195		- if (!trans_pcie->fw_mon_page)
	195	+ if (!fw_mon->size)
196	196	return;
197	197
198		- dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
199		- trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
200		- __free_pages(trans_pcie->fw_mon_page,
201		- get_order(trans_pcie->fw_mon_size));
202		- trans_pcie->fw_mon_page = NULL;
203		- trans_pcie->fw_mon_phys = 0;
204		- trans_pcie->fw_mon_size = 0;
	198	+ dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
	199	+ fw_mon->physical);
	200	+
	201	+ fw_mon->block = NULL;
	202	+ fw_mon->physical = 0;
	203	+ fw_mon->size = 0;
	204	+}
	205	+
	206	+static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
	207	+ u8 max_power, u8 min_power)
	208	+{
	209	+ struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
	210	+ void *block = NULL;
	211	+ dma_addr_t physical = 0;
	212	+ u32 size = 0;
	213	+ u8 power;
	214	+
	215	+ if (fw_mon->size)
	216	+ return;
	217	+
	218	+ for (power = max_power; power >= min_power; power--) {
	219	+ size = BIT(power);
	220	+ block = dma_alloc_coherent(trans->dev, size, &physical,
	221	+ GFP_KERNEL \| __GFP_NOWARN);
	222	+ if (!block)
	223	+ continue;
	224	+
	225	+ IWL_INFO(trans,
	226	+ "Allocated 0x%08x bytes for firmware monitor.\n",
	227	+ size);
	228	+ break;
	229	+ }
	230	+
	231	+ if (WARN_ON_ONCE(!block))
	232	+ return;
	233	+
	234	+ if (power != max_power)
	235	+ IWL_ERR(trans,
	236	+ "Sorry - debug buffer is only %luK while you requested %luK\n",
	237	+ (unsigned long)BIT(power - 10),
	238	+ (unsigned long)BIT(max_power - 10));
	239	+
	240	+ fw_mon->block = block;
	241	+ fw_mon->physical = physical;
	242	+ fw_mon->size = size;
205	243	}
206	244
207	245	void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
208	246	{
209		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
210		- struct page *page = NULL;
211		- dma_addr_t phys;
212		- u32 size = 0;
213		- u8 power;
214		-
215	247	if (!max_power) {
216	248	/* default max_power is maximum */
217	249	max_power = 26;
..	..	@@ -224,49 +256,10 @@
224	256	max_power))
225	257	return;
226	258
227		- if (trans_pcie->fw_mon_page) {
228		- dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
229		- trans_pcie->fw_mon_size,
230		- DMA_FROM_DEVICE);
231		- return;
232		- }
233		-
234		- phys = 0;
235		- for (power = max_power; power >= 11; power--) {
236		- int order;
237		-
238		- size = BIT(power);
239		- order = get_order(size);
240		- page = alloc_pages(__GFP_COMP \| __GFP_NOWARN \| __GFP_ZERO,
241		- order);
242		- if (!page)
243		- continue;
244		-
245		- phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
246		- DMA_FROM_DEVICE);
247		- if (dma_mapping_error(trans->dev, phys)) {
248		- __free_pages(page, order);
249		- page = NULL;
250		- continue;
251		- }
252		- IWL_INFO(trans,
253		- "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
254		- size, order);
255		- break;
256		- }
257		-
258		- if (WARN_ON_ONCE(!page))
	259	+ if (trans->dbg.fw_mon.size)
259	260	return;
260	261
261		- if (power != max_power)
262		- IWL_ERR(trans,
263		- "Sorry - debug buffer is only %luK while you requested %luK\n",
264		- (unsigned long)BIT(power - 10),
265		- (unsigned long)BIT(max_power - 10));
266		-
267		- trans_pcie->fw_mon_page = page;
268		- trans_pcie->fw_mon_phys = phys;
269		- trans_pcie->fw_mon_size = size;
	262	+ iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
270	263	}
271	264
272	265	static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
..	..	@@ -308,18 +301,13 @@
308	301	u16 cap;
309	302
310	303	/*
311		- * HW bug W/A for instability in PCIe bus L0S->L1 transition.
312		- * Check if BIOS (or OS) enabled L1-ASPM on this device.
313		- * If so (likely), disable L0S, so device moves directly L0->L1;
314		- * costs negligible amount of power savings.
315		- * If not (unlikely), enable L0S, so there is at least some
316		- * power savings, even without L1.
	304	+ * L0S states have been found to be unstable with our devices
	305	+ * and in newer hardware they are not officially supported at
	306	+ * all, so we must always set the L0S_DISABLED bit.
317	307	*/
	308	+ iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
	309	+
318	310	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
319		- if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
320		- iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
321		- else
322		- iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
323	311	trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
324	312
325	313	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
..	..	@@ -346,7 +334,7 @@
346	334	*/
347	335
348	336	/* Disable L0S exit timer (platform NMI Work/Around) */
349		- if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
	337	+ if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
350	338	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
351	339	CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
352	340
..	..	@@ -370,29 +358,12 @@
370	358	iwl_pcie_apm_config(trans);
371	359
372	360	/* Configure analog phase-lock-loop before activating to D0A */
373		- if (trans->cfg->base_params->pll_cfg)
	361	+ if (trans->trans_cfg->base_params->pll_cfg)
374	362	iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
375	363
376		- /*
377		- * Set "initialization complete" bit to move adapter from
378		- * D0U* --> D0A* (powered-up active) state.
379		- */
380		- iwl_set_bit(trans, CSR_GP_CNTRL,
381		- BIT(trans->cfg->csr->flag_init_done));
382		-
383		- /*
384		- * Wait for clock stabilization; once stabilized, access to
385		- * device-internal resources is supported, e.g. iwl_write_prph()
386		- * and accesses to uCode SRAM.
387		- */
388		- ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
389		- BIT(trans->cfg->csr->flag_mac_clock_ready),
390		- BIT(trans->cfg->csr->flag_mac_clock_ready),
391		- 25000);
392		- if (ret < 0) {
393		- IWL_ERR(trans, "Failed to init the card\n");
	364	+ ret = iwl_finish_nic_init(trans, trans->trans_cfg);
	365	+ if (ret)
394	366	return ret;
395		- }
396	367
397	368	if (trans->cfg->host_interrupt_operation_mode) {
398	369	/*
..	..	@@ -462,23 +433,8 @@
462	433
463	434	iwl_trans_pcie_sw_reset(trans);
464	435
465		- /*
466		- * Set "initialization complete" bit to move adapter from
467		- * D0U* --> D0A* (powered-up active) state.
468		- */
469		- iwl_set_bit(trans, CSR_GP_CNTRL,
470		- BIT(trans->cfg->csr->flag_init_done));
471		-
472		- /*
473		- * Wait for clock stabilization; once stabilized, access to
474		- * device-internal resources is possible.
475		- */
476		- ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
477		- BIT(trans->cfg->csr->flag_mac_clock_ready),
478		- BIT(trans->cfg->csr->flag_mac_clock_ready),
479		- 25000);
480		- if (WARN_ON(ret < 0)) {
481		- IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
	436	+ ret = iwl_finish_nic_init(trans, trans->trans_cfg);
	437	+ if (WARN_ON(ret)) {
482	438	/* Release XTAL ON request */
483	439	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
484	440	CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
..	..	@@ -526,8 +482,7 @@
526	482	* Clear "initialization complete" bit to move adapter from
527	483	* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
528	484	*/
529		- iwl_clear_bit(trans, CSR_GP_CNTRL,
530		- BIT(trans->cfg->csr->flag_init_done));
	485	+ iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
531	486
532	487	/* Activates XTAL resources monitor */
533	488	__iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
..	..	@@ -549,12 +504,11 @@
549	504	int ret;
550	505
551	506	/* stop device's busmaster DMA activity */
552		- iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
553		- BIT(trans->cfg->csr->flag_stop_master));
	507	+ iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
554	508
555		- ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset,
556		- BIT(trans->cfg->csr->flag_master_dis),
557		- BIT(trans->cfg->csr->flag_master_dis), 100);
	509	+ ret = iwl_poll_bit(trans, CSR_RESET,
	510	+ CSR_RESET_REG_FLAG_MASTER_DISABLED,
	511	+ CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
558	512	if (ret < 0)
559	513	IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
560	514
..	..	@@ -570,10 +524,11 @@
570	524	iwl_pcie_apm_init(trans);
571	525
572	526	/* inform ME that we are leaving */
573		- if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
	527	+ if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
574	528	iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
575	529	APMG_PCIDEV_STT_VAL_WAKE_ME);
576		- else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
	530	+ else if (trans->trans_cfg->device_family >=
	531	+ IWL_DEVICE_FAMILY_8000) {
577	532	iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
578	533	CSR_RESET_LINK_PWR_MGMT_DISABLED);
579	534	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
..	..	@@ -602,8 +557,7 @@
602	557	* Clear "initialization complete" bit to move adapter from
603	558	* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
604	559	*/
605		- iwl_clear_bit(trans, CSR_GP_CNTRL,
606		- BIT(trans->cfg->csr->flag_init_done));
	560	+ iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
607	561	}
608	562
609	563	static int iwl_pcie_nic_init(struct iwl_trans *trans)
..	..	@@ -630,7 +584,7 @@
630	584	if (iwl_pcie_tx_init(trans))
631	585	return -ENOMEM;
632	586
633		- if (trans->cfg->base_params->shadow_reg_enable) {
	587	+ if (trans->trans_cfg->base_params->shadow_reg_enable) {
634	588	/* enable shadow regs in HW */
635	589	iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
636	590	IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
..	..	@@ -868,7 +822,7 @@
868	822
869	823	iwl_enable_interrupts(trans);
870	824
871		- if (trans->cfg->use_tfh) {
	825	+ if (trans->trans_cfg->use_tfh) {
872	826	if (cpu == 1)
873	827	iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
874	828	0xFFFF);
..	..	@@ -928,11 +882,53 @@
928	882	return 0;
929	883	}
930	884
	885	+static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
	886	+{
	887	+ enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
	888	+ struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
	889	+ &trans->dbg.fw_mon_cfg[alloc_id];
	890	+ struct iwl_dram_data *frag;
	891	+
	892	+ if (!iwl_trans_dbg_ini_valid(trans))
	893	+ return;
	894	+
	895	+ if (le32_to_cpu(fw_mon_cfg->buf_location) ==
	896	+ IWL_FW_INI_LOCATION_SRAM_PATH) {
	897	+ IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
	898	+ /* set sram monitor by enabling bit 7 */
	899	+ iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
	900	+ CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
	901	+
	902	+ return;
	903	+ }
	904	+
	905	+ if (le32_to_cpu(fw_mon_cfg->buf_location) !=
	906	+ IWL_FW_INI_LOCATION_DRAM_PATH \|\|
	907	+ !trans->dbg.fw_mon_ini[alloc_id].num_frags)
	908	+ return;
	909	+
	910	+ frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
	911	+
	912	+ IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
	913	+ alloc_id);
	914	+
	915	+ iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
	916	+ frag->physical >> MON_BUFF_SHIFT_VER2);
	917	+ iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
	918	+ (frag->physical + frag->size - 256) >>
	919	+ MON_BUFF_SHIFT_VER2);
	920	+}
	921	+
931	922	void iwl_pcie_apply_destination(struct iwl_trans *trans)
932	923	{
933		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
934		- const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv;
	924	+ const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
	925	+ const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
935	926	int i;
	927	+
	928	+ if (iwl_trans_dbg_ini_valid(trans)) {
	929	+ iwl_pcie_apply_destination_ini(trans);
	930	+ return;
	931	+ }
936	932
937	933	IWL_INFO(trans, "Applying debug destination %s\n",
938	934	get_fw_dbg_mode_string(dest->monitor_mode));
..	..	@@ -942,7 +938,7 @@
942	938	else
943	939	IWL_WARN(trans, "PCI should have external buffer debug\n");
944	940
945		- for (i = 0; i < trans->dbg_dest_reg_num; i++) {
	941	+ for (i = 0; i < trans->dbg.n_dest_reg; i++) {
946	942	u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
947	943	u32 val = le32_to_cpu(dest->reg_ops[i].val);
948	944
..	..	@@ -981,26 +977,23 @@
981	977	}
982	978
983	979	monitor:
984		- if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
	980	+ if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
985	981	iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
986		- trans_pcie->fw_mon_phys >> dest->base_shift);
987		- if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
	982	+ fw_mon->physical >> dest->base_shift);
	983	+ if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
988	984	iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
989		- (trans_pcie->fw_mon_phys +
990		- trans_pcie->fw_mon_size - 256) >>
991		- dest->end_shift);
	985	+ (fw_mon->physical + fw_mon->size -
	986	+ 256) >> dest->end_shift);
992	987	else
993	988	iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
994		- (trans_pcie->fw_mon_phys +
995		- trans_pcie->fw_mon_size) >>
996		- dest->end_shift);
	989	+ (fw_mon->physical + fw_mon->size) >>
	990	+ dest->end_shift);
997	991	}
998	992	}
999	993
1000	994	static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
1001	995	const struct fw_img *image)
1002	996	{
1003		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1004	997	int ret = 0;
1005	998	int first_ucode_section;
1006	999
..	..	@@ -1025,21 +1018,8 @@
1025	1018	return ret;
1026	1019	}
1027	1020
1028		- /* supported for 7000 only for the moment */
1029		- if (iwlwifi_mod_params.fw_monitor &&
1030		- trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1031		- iwl_pcie_alloc_fw_monitor(trans, 0);
1032		-
1033		- if (trans_pcie->fw_mon_size) {
1034		- iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1035		- trans_pcie->fw_mon_phys >> 4);
1036		- iwl_write_prph(trans, MON_BUFF_END_ADDR,
1037		- (trans_pcie->fw_mon_phys +
1038		- trans_pcie->fw_mon_size) >> 4);
1039		- }
1040		- } else if (trans->dbg_dest_tlv) {
	1021	+ if (iwl_pcie_dbg_on(trans))
1041	1022	iwl_pcie_apply_destination(trans);
1042		- }
1043	1023
1044	1024	iwl_enable_interrupts(trans);
1045	1025
..	..	@@ -1058,7 +1038,7 @@
1058	1038	IWL_DEBUG_FW(trans, "working with %s CPU\n",
1059	1039	image->is_dual_cpus ? "Dual" : "Single");
1060	1040
1061		- if (trans->dbg_dest_tlv)
	1041	+ if (iwl_pcie_dbg_on(trans))
1062	1042	iwl_pcie_apply_destination(trans);
1063	1043
1064	1044	IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
..	..	@@ -1123,6 +1103,7 @@
1123	1103	{MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1124	1104	{MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1125	1105	{MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
	1106	+ {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12},
1126	1107	{MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1127	1108	{MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1128	1109	{MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
..	..	@@ -1133,30 +1114,12 @@
1133	1114	{MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1134	1115	};
1135	1116
1136		-static struct iwl_causes_list causes_list_v2[] = {
1137		- {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1138		- {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1139		- {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1140		- {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1141		- {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1142		- {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1143		- {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15},
1144		- {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1145		- {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1146		- {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1147		- {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1148		- {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1149		- {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1150		- {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1151		-};
1152		-
1153	1117	static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1154	1118	{
1155	1119	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1156	1120	int val = trans_pcie->def_irq \| MSIX_NON_AUTO_CLEAR_CAUSE;
1157		- int i, arr_size =
1158		- (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ?
1159		- ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2);
	1121	+ int i, arr_size = ARRAY_SIZE(causes_list);
	1122	+ struct iwl_causes_list *causes = causes_list;
1160	1123
1161	1124	/*
1162	1125	* Access all non RX causes and map them to the default irq.
..	..	@@ -1164,10 +1127,6 @@
1164	1127	* the first interrupt vector will serve non-RX and FBQ causes.
1165	1128	*/
1166	1129	for (i = 0; i < arr_size; i++) {
1167		- struct iwl_causes_list *causes =
1168		- (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ?
1169		- causes_list : causes_list_v2;
1170		-
1171	1130	iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1172	1131	iwl_clear_bit(trans, causes[i].mask_reg,
1173	1132	causes[i].cause_num);
..	..	@@ -1209,10 +1168,10 @@
1209	1168	struct iwl_trans *trans = trans_pcie->trans;
1210	1169
1211	1170	if (!trans_pcie->msix_enabled) {
1212		- if (trans->cfg->mq_rx_supported &&
	1171	+ if (trans->trans_cfg->mq_rx_supported &&
1213	1172	test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1214		- iwl_write_prph(trans, UREG_CHICK,
1215		- UREG_CHICK_MSI_ENABLE);
	1173	+ iwl_write_umac_prph(trans, UREG_CHICK,
	1174	+ UREG_CHICK_MSI_ENABLE);
1216	1175	return;
1217	1176	}
1218	1177	/*
..	..	@@ -1221,7 +1180,7 @@
1221	1180	* prph.
1222	1181	*/
1223	1182	if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1224		- iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
	1183	+ iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1225	1184
1226	1185	/*
1227	1186	* Each cause from the causes list above and the RX causes is
..	..	@@ -1250,7 +1209,7 @@
1250	1209	trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1251	1210	}
1252	1211
1253		-static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
	1212	+static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1254	1213	{
1255	1214	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1256	1215
..	..	@@ -1260,15 +1219,6 @@
1260	1219	return;
1261	1220
1262	1221	trans_pcie->is_down = true;
1263		-
1264		- /* Stop dbgc before stopping device */
1265		- if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1266		- iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
1267		- } else {
1268		- iwl_write_prph(trans, DBGC_IN_SAMPLE, 0);
1269		- udelay(100);
1270		- iwl_write_prph(trans, DBGC_OUT_CTRL, 0);
1271		- }
1272	1222
1273	1223	/* tell the device to stop sending interrupts */
1274	1224	iwl_disable_interrupts(trans);
..	..	@@ -1299,7 +1249,7 @@
1299	1249
1300	1250	/* Make sure (redundant) we've released our request to stay awake */
1301	1251	iwl_clear_bit(trans, CSR_GP_CNTRL,
1302		- BIT(trans->cfg->csr->flag_mac_access_req));
	1252	+ CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1303	1253
1304	1254	/* Stop the device, and put it in low power state */
1305	1255	iwl_pcie_apm_stop(trans, false);
..	..	@@ -1425,7 +1375,7 @@
1425	1375	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1426	1376
1427	1377	/* Load the given image to the HW */
1428		- if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
	1378	+ if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1429	1379	ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1430	1380	else
1431	1381	ret = iwl_pcie_load_given_ucode(trans, fw);
..	..	@@ -1475,7 +1425,7 @@
1475	1425	iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1476	1426	}
1477	1427
1478		-static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
	1428	+static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1479	1429	{
1480	1430	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1481	1431	bool was_in_rfkill;
..	..	@@ -1483,7 +1433,7 @@
1483	1433	mutex_lock(&trans_pcie->mutex);
1484	1434	trans_pcie->opmode_down = true;
1485	1435	was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1486		- _iwl_trans_pcie_stop_device(trans, low_power);
	1436	+ _iwl_trans_pcie_stop_device(trans);
1487	1437	iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1488	1438	mutex_unlock(&trans_pcie->mutex);
1489	1439	}
..	..	@@ -1498,22 +1448,16 @@
1498	1448	IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1499	1449	state ? "disabled" : "enabled");
1500	1450	if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1501		- if (trans->cfg->gen2)
1502		- _iwl_trans_pcie_gen2_stop_device(trans, true);
	1451	+ if (trans->trans_cfg->gen2)
	1452	+ _iwl_trans_pcie_gen2_stop_device(trans);
1503	1453	else
1504		- _iwl_trans_pcie_stop_device(trans, true);
	1454	+ _iwl_trans_pcie_stop_device(trans);
1505	1455	}
1506	1456	}
1507	1457
1508		-static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1509		- bool reset)
	1458	+void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
	1459	+ bool test, bool reset)
1510	1460	{
1511		- if (!reset) {
1512		- /* Enable persistence mode to avoid reset */
1513		- iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1514		- CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1515		- }
1516		-
1517	1461	iwl_disable_interrupts(trans);
1518	1462
1519	1463	/*
..	..	@@ -1528,11 +1472,8 @@
1528	1472	iwl_pcie_synchronize_irqs(trans);
1529	1473
1530	1474	iwl_clear_bit(trans, CSR_GP_CNTRL,
1531		- BIT(trans->cfg->csr->flag_mac_access_req));
1532		- iwl_clear_bit(trans, CSR_GP_CNTRL,
1533		- BIT(trans->cfg->csr->flag_init_done));
1534		-
1535		- iwl_pcie_enable_rx_wake(trans, false);
	1475	+ CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
	1476	+ iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1536	1477
1537	1478	if (reset) {
1538	1479	/*
..	..	@@ -1546,6 +1487,38 @@
1546	1487	iwl_pcie_set_pwr(trans, true);
1547	1488	}
1548	1489
	1490	+static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
	1491	+ bool reset)
	1492	+{
	1493	+ int ret;
	1494	+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	1495	+
	1496	+ if (!reset)
	1497	+ /* Enable persistence mode to avoid reset */
	1498	+ iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
	1499	+ CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
	1500	+
	1501	+ if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
	1502	+ iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
	1503	+ UREG_DOORBELL_TO_ISR6_SUSPEND);
	1504	+
	1505	+ ret = wait_event_timeout(trans_pcie->sx_waitq,
	1506	+ trans_pcie->sx_complete, 2 * HZ);
	1507	+ /*
	1508	+ * Invalidate it toward resume.
	1509	+ */
	1510	+ trans_pcie->sx_complete = false;
	1511	+
	1512	+ if (!ret) {
	1513	+ IWL_ERR(trans, "Timeout entering D3\n");
	1514	+ return -ETIMEDOUT;
	1515	+ }
	1516	+ }
	1517	+ iwl_pcie_d3_complete_suspend(trans, test, reset);
	1518	+
	1519	+ return 0;
	1520	+}
	1521	+
1549	1522	static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1550	1523	enum iwl_d3_status *status,
1551	1524	bool test, bool reset)
..	..	@@ -1557,27 +1530,15 @@
1557	1530	if (test) {
1558	1531	iwl_enable_interrupts(trans);
1559	1532	*status = IWL_D3_STATUS_ALIVE;
1560		- return 0;
	1533	+ goto out;
1561	1534	}
1562	1535
1563		- iwl_pcie_enable_rx_wake(trans, true);
1564		-
1565	1536	iwl_set_bit(trans, CSR_GP_CNTRL,
1566		- BIT(trans->cfg->csr->flag_mac_access_req));
1567		- iwl_set_bit(trans, CSR_GP_CNTRL,
1568		- BIT(trans->cfg->csr->flag_init_done));
	1537	+ CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1569	1538
1570		- if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1571		- udelay(2);
1572		-
1573		- ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1574		- BIT(trans->cfg->csr->flag_mac_clock_ready),
1575		- BIT(trans->cfg->csr->flag_mac_clock_ready),
1576		- 25000);
1577		- if (ret < 0) {
1578		- IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
	1539	+ ret = iwl_finish_nic_init(trans, trans->trans_cfg);
	1540	+ if (ret)
1579	1541	return ret;
1580		- }
1581	1542
1582	1543	/*
1583	1544	* Reconfigure IVAR table in case of MSIX or reset ict table in
..	..	@@ -1595,7 +1556,7 @@
1595	1556
1596	1557	if (!reset) {
1597	1558	iwl_clear_bit(trans, CSR_GP_CNTRL,
1598		- BIT(trans->cfg->csr->flag_mac_access_req));
	1559	+ CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1599	1560	} else {
1600	1561	iwl_trans_pcie_tx_reset(trans);
1601	1562
..	..	@@ -1608,7 +1569,7 @@
1608	1569	}
1609	1570
1610	1571	IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1611		- iwl_read_prph(trans, WFPM_GP2));
	1572	+ iwl_read_umac_prph(trans, WFPM_GP2));
1612	1573
1613	1574	val = iwl_read32(trans, CSR_RESET);
1614	1575	if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
..	..	@@ -1616,20 +1577,45 @@
1616	1577	else
1617	1578	*status = IWL_D3_STATUS_ALIVE;
1618	1579
	1580	+out:
	1581	+ if (*status == IWL_D3_STATUS_ALIVE &&
	1582	+ trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
	1583	+ trans_pcie->sx_complete = false;
	1584	+ iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
	1585	+ UREG_DOORBELL_TO_ISR6_RESUME);
	1586	+
	1587	+ ret = wait_event_timeout(trans_pcie->sx_waitq,
	1588	+ trans_pcie->sx_complete, 2 * HZ);
	1589	+ /*
	1590	+ * Invalidate it toward next suspend.
	1591	+ */
	1592	+ trans_pcie->sx_complete = false;
	1593	+
	1594	+ if (!ret) {
	1595	+ IWL_ERR(trans, "Timeout exiting D3\n");
	1596	+ return -ETIMEDOUT;
	1597	+ }
	1598	+ }
1619	1599	return 0;
1620	1600	}
1621	1601
1622		-static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1623		- struct iwl_trans *trans)
	1602	+static void
	1603	+iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
	1604	+ struct iwl_trans *trans,
	1605	+ const struct iwl_cfg_trans_params *cfg_trans)
1624	1606	{
1625	1607	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1626	1608	int max_irqs, num_irqs, i, ret;
1627	1609	u16 pci_cmd;
	1610	+ u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES;
1628	1611
1629		- if (!trans->cfg->mq_rx_supported)
	1612	+ if (!cfg_trans->mq_rx_supported)
1630	1613	goto enable_msi;
1631	1614
1632		- max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
	1615	+ if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000)
	1616	+ max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES;
	1617	+
	1618	+ max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues);
1633	1619	for (i = 0; i < max_irqs; i++)
1634	1620	trans_pcie->msix_entries[i].entry = i;
1635	1621
..	..	@@ -1743,10 +1729,63 @@
1743	1729	return 0;
1744	1730	}
1745	1731
1746		-static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
	1732	+static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
	1733	+{
	1734	+ u32 hpm, wprot;
	1735	+
	1736	+ switch (trans->trans_cfg->device_family) {
	1737	+ case IWL_DEVICE_FAMILY_9000:
	1738	+ wprot = PREG_PRPH_WPROT_9000;
	1739	+ break;
	1740	+ case IWL_DEVICE_FAMILY_22000:
	1741	+ wprot = PREG_PRPH_WPROT_22000;
	1742	+ break;
	1743	+ default:
	1744	+ return 0;
	1745	+ }
	1746	+
	1747	+ hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
	1748	+ if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
	1749	+ u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
	1750	+
	1751	+ if (wprot_val & PREG_WFPM_ACCESS) {
	1752	+ IWL_ERR(trans,
	1753	+ "Error, can not clear persistence bit\n");
	1754	+ return -EPERM;
	1755	+ }
	1756	+ iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
	1757	+ hpm & ~PERSISTENCE_BIT);
	1758	+ }
	1759	+
	1760	+ return 0;
	1761	+}
	1762	+
	1763	+static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
	1764	+{
	1765	+ int ret;
	1766	+
	1767	+ ret = iwl_finish_nic_init(trans, trans->trans_cfg);
	1768	+ if (ret < 0)
	1769	+ return ret;
	1770	+
	1771	+ iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
	1772	+ HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
	1773	+ udelay(20);
	1774	+ iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
	1775	+ HPM_HIPM_GEN_CFG_CR_PG_EN \|
	1776	+ HPM_HIPM_GEN_CFG_CR_SLP_EN);
	1777	+ udelay(20);
	1778	+ iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
	1779	+ HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
	1780	+
	1781	+ iwl_trans_pcie_sw_reset(trans);
	1782	+
	1783	+ return 0;
	1784	+}
	1785	+
	1786	+static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1747	1787	{
1748	1788	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1749		- u32 hpm;
1750	1789	int err;
1751	1790
1752	1791	lockdep_assert_held(&trans_pcie->mutex);
..	..	@@ -1757,18 +1796,18 @@
1757	1796	return err;
1758	1797	}
1759	1798
1760		- hpm = iwl_trans_read_prph(trans, HPM_DEBUG);
1761		- if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
1762		- if (iwl_trans_read_prph(trans, PREG_PRPH_WPROT_0) &
1763		- PREG_WFPM_ACCESS) {
1764		- IWL_ERR(trans,
1765		- "Error, can not clear persistence bit\n");
1766		- return -EPERM;
1767		- }
1768		- iwl_trans_write_prph(trans, HPM_DEBUG, hpm & ~PERSISTENCE_BIT);
1769		- }
	1799	+ err = iwl_trans_pcie_clear_persistence_bit(trans);
	1800	+ if (err)
	1801	+ return err;
1770	1802
1771	1803	iwl_trans_pcie_sw_reset(trans);
	1804	+
	1805	+ if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
	1806	+ trans->trans_cfg->integrated) {
	1807	+ err = iwl_pcie_gen2_force_power_gating(trans);
	1808	+ if (err)
	1809	+ return err;
	1810	+ }
1772	1811
1773	1812	err = iwl_pcie_apm_init(trans);
1774	1813	if (err)
..	..	@@ -1787,20 +1826,16 @@
1787	1826	/* ...rfkill can call stop_device and set it false if needed */
1788	1827	iwl_pcie_check_hw_rf_kill(trans);
1789	1828
1790		- /* Make sure we sync here, because we'll need full access later */
1791		- if (low_power)
1792		- pm_runtime_resume(trans->dev);
1793		-
1794	1829	return 0;
1795	1830	}
1796	1831
1797		-static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
	1832	+static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1798	1833	{
1799	1834	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1800	1835	int ret;
1801	1836
1802	1837	mutex_lock(&trans_pcie->mutex);
1803		- ret = _iwl_trans_pcie_start_hw(trans, low_power);
	1838	+ ret = _iwl_trans_pcie_start_hw(trans);
1804	1839	mutex_unlock(&trans_pcie->mutex);
1805	1840
1806	1841	return ret;
..	..	@@ -1843,7 +1878,7 @@
1843	1878
1844	1879	static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1845	1880	{
1846		- if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
	1881	+ if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1847	1882	return 0x00FFFFFF;
1848	1883	else
1849	1884	return 0x000FFFFF;
..	..	@@ -1873,9 +1908,15 @@
1873	1908	{
1874	1909	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1875	1910
1876		- trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1877		- trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1878		- trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
	1911	+ /* free all first - we might be reconfigured for a different size */
	1912	+ iwl_pcie_free_rbs_pool(trans);
	1913	+
	1914	+ trans->txqs.cmd.q_id = trans_cfg->cmd_queue;
	1915	+ trans->txqs.cmd.fifo = trans_cfg->cmd_fifo;
	1916	+ trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
	1917	+ trans->txqs.page_offs = trans_cfg->cb_data_offs;
	1918	+ trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
	1919	+
1879	1920	if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1880	1921	trans_pcie->n_no_reclaim_cmds = 0;
1881	1922	else
..	..	@@ -1887,13 +1928,15 @@
1887	1928	trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1888	1929	trans_pcie->rx_page_order =
1889	1930	iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
	1931	+ trans_pcie->rx_buf_bytes =
	1932	+ iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
	1933	+ trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);
	1934	+ if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
	1935	+ trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);
1890	1936
1891		- trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
	1937	+ trans->txqs.bc_table_dword = trans_cfg->bc_table_dword;
1892	1938	trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1893	1939	trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1894		-
1895		- trans_pcie->page_offs = trans_cfg->cb_data_offs;
1896		- trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1897	1940
1898	1941	trans->command_groups = trans_cfg->command_groups;
1899	1942	trans->command_groups_size = trans_cfg->command_groups_size;
..	..	@@ -1914,8 +1957,8 @@
1914	1957
1915	1958	iwl_pcie_synchronize_irqs(trans);
1916	1959
1917		- if (trans->cfg->gen2)
1918		- iwl_pcie_gen2_tx_free(trans);
	1960	+ if (trans->trans_cfg->gen2)
	1961	+ iwl_txq_gen2_tx_free(trans);
1919	1962	else
1920	1963	iwl_pcie_tx_free(trans);
1921	1964	iwl_pcie_rx_free(trans);
..	..	@@ -1939,15 +1982,11 @@
1939	1982
1940	1983	iwl_pcie_free_fw_monitor(trans);
1941	1984
1942		- for_each_possible_cpu(i) {
1943		- struct iwl_tso_hdr_page *p =
1944		- per_cpu_ptr(trans_pcie->tso_hdr_page, i);
	1985	+ if (trans_pcie->pnvm_dram.size)
	1986	+ dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size,
	1987	+ trans_pcie->pnvm_dram.block,
	1988	+ trans_pcie->pnvm_dram.physical);
1945	1989
1946		- if (p->page)
1947		- __free_page(p->page);
1948		- }
1949		-
1950		- free_percpu(trans_pcie->tso_hdr_page);
1951	1990	mutex_destroy(&trans_pcie->mutex);
1952	1991	iwl_trans_free(trans);
1953	1992	}
..	..	@@ -1970,7 +2009,7 @@
1970	2009	struct iwl_trans_pcie_removal *removal =
1971	2010	container_of(wk, struct iwl_trans_pcie_removal, work);
1972	2011	struct pci_dev *pdev = removal->pdev;
1973		- char *prop[] = {"EVENT=INACCESSIBLE", NULL};
	2012	+ static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
1974	2013
1975	2014	dev_err(&pdev->dev, "Device gone - attempting removal\n");
1976	2015	kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
..	..	@@ -1989,15 +2028,15 @@
1989	2028	int ret;
1990	2029	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1991	2030
1992		- spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
	2031	+ spin_lock_bh(&trans_pcie->reg_lock);
1993	2032
1994	2033	if (trans_pcie->cmd_hold_nic_awake)
1995	2034	goto out;
1996	2035
1997	2036	/* this bit wakes up the NIC */
1998	2037	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1999		- BIT(trans->cfg->csr->flag_mac_access_req));
2000		- if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
	2038	+ CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
	2039	+ if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
2001	2040	udelay(2);
2002	2041
2003	2042	/*
..	..	@@ -2021,8 +2060,8 @@
2021	2060	* and do not save/restore SRAM when power cycling.
2022	2061	*/
2023	2062	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2024		- BIT(trans->cfg->csr->flag_val_mac_access_en),
2025		- (BIT(trans->cfg->csr->flag_mac_clock_ready) \|
	2063	+ CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
	2064	+ (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY \|
2026	2065	CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2027	2066	if (unlikely(ret < 0)) {
2028	2067	u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
..	..	@@ -2036,7 +2075,7 @@
2036	2075	if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2037	2076	struct iwl_trans_pcie_removal *removal;
2038	2077
2039		- if (trans_pcie->scheduled_for_removal)
	2078	+ if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2040	2079	goto err;
2041	2080
2042	2081	IWL_ERR(trans, "Device gone - scheduling removal!\n");
..	..	@@ -2062,7 +2101,7 @@
2062	2101	* we don't need to clear this flag, because
2063	2102	* the trans will be freed and reallocated.
2064	2103	*/
2065		- trans_pcie->scheduled_for_removal = true;
	2104	+ set_bit(STATUS_TRANS_DEAD, &trans->status);
2066	2105
2067	2106	removal->pdev = to_pci_dev(trans->dev);
2068	2107	INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
..	..	@@ -2074,7 +2113,7 @@
2074	2113	}
2075	2114
2076	2115	err:
2077		- spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
	2116	+ spin_unlock_bh(&trans_pcie->reg_lock);
2078	2117	return false;
2079	2118	}
2080	2119
..	..	@@ -2104,16 +2143,15 @@
2104	2143	goto out;
2105	2144
2106	2145	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2107		- BIT(trans->cfg->csr->flag_mac_access_req));
	2146	+ CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2108	2147	/*
2109	2148	* Above we read the CSR_GP_CNTRL register, which will flush
2110	2149	* any previous writes, but we need the write that clears the
2111	2150	* MAC_ACCESS_REQ bit to be performed before any other writes
2112	2151	* scheduled on different CPUs (after we drop reg_lock).
2113	2152	*/
2114		- mmiowb();
2115	2153	out:
2116		- spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
	2154	+ spin_unlock_bh(&trans_pcie->reg_lock);
2117	2155	}
2118	2156
2119	2157	static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
..	..	@@ -2173,15 +2211,21 @@
2173	2211	return ret;
2174	2212	}
2175	2213
	2214	+static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
	2215	+ u32 *val)
	2216	+{
	2217	+ return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
	2218	+ ofs, val);
	2219	+}
	2220	+
2176	2221	static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2177	2222	unsigned long txqs,
2178	2223	bool freeze)
2179	2224	{
2180		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2181	2225	int queue;
2182	2226
2183	2227	for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
2184		- struct iwl_txq *txq = trans_pcie->txq[queue];
	2228	+ struct iwl_txq *txq = trans->txqs.txq[queue];
2185	2229	unsigned long now;
2186	2230
2187	2231	spin_lock_bh(&txq->lock);
..	..	@@ -2229,13 +2273,12 @@
2229	2273
2230	2274	static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2231	2275	{
2232		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2233	2276	int i;
2234	2277
2235		- for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2236		- struct iwl_txq *txq = trans_pcie->txq[i];
	2278	+ for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
	2279	+ struct iwl_txq *txq = trans->txqs.txq[i];
2237	2280
2238		- if (i == trans_pcie->cmd_queue)
	2281	+ if (i == trans->txqs.cmd.q_id)
2239	2282	continue;
2240	2283
2241	2284	spin_lock_bh(&txq->lock);
..	..	@@ -2256,36 +2299,6 @@
2256	2299
2257	2300	#define IWL_FLUSH_WAIT_MS 2000
2258	2301
2259		-void iwl_trans_pcie_log_scd_error(struct iwl_trans trans, struct iwl_txq txq)
2260		-{
2261		- u32 txq_id = txq->id;
2262		- u32 status;
2263		- bool active;
2264		- u8 fifo;
2265		-
2266		- if (trans->cfg->use_tfh) {
2267		- IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2268		- txq->read_ptr, txq->write_ptr);
2269		- /* TODO: access new SCD registers and dump them */
2270		- return;
2271		- }
2272		-
2273		- status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2274		- fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2275		- active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2276		-
2277		- IWL_ERR(trans,
2278		- "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2279		- txq_id, active ? "" : "in", fifo,
2280		- jiffies_to_msecs(txq->wd_timeout),
2281		- txq->read_ptr, txq->write_ptr,
2282		- iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2283		- (trans->cfg->base_params->max_tfd_queue_size - 1),
2284		- iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2285		- (trans->cfg->base_params->max_tfd_queue_size - 1),
2286		- iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
2287		-}
2288		-
2289	2302	static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2290	2303	struct iwl_trans_rxq_dma_data *data)
2291	2304	{
..	..	@@ -2304,34 +2317,57 @@
2304	2317
2305	2318	static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2306	2319	{
2307		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2308	2320	struct iwl_txq *txq;
2309	2321	unsigned long now = jiffies;
	2322	+ bool overflow_tx;
2310	2323	u8 wr_ptr;
2311	2324
2312		- if (!test_bit(txq_idx, trans_pcie->queue_used))
	2325	+ /* Make sure the NIC is still alive in the bus */
	2326	+ if (test_bit(STATUS_TRANS_DEAD, &trans->status))
	2327	+ return -ENODEV;
	2328	+
	2329	+ if (!test_bit(txq_idx, trans->txqs.queue_used))
2313	2330	return -EINVAL;
2314	2331
2315	2332	IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2316		- txq = trans_pcie->txq[txq_idx];
	2333	+ txq = trans->txqs.txq[txq_idx];
	2334	+
	2335	+ spin_lock_bh(&txq->lock);
	2336	+ overflow_tx = txq->overflow_tx \|\|
	2337	+ !skb_queue_empty(&txq->overflow_q);
	2338	+ spin_unlock_bh(&txq->lock);
	2339	+
2317	2340	wr_ptr = READ_ONCE(txq->write_ptr);
2318	2341
2319		- while (txq->read_ptr != READ_ONCE(txq->write_ptr) &&
	2342	+ while ((txq->read_ptr != READ_ONCE(txq->write_ptr) \|\|
	2343	+ overflow_tx) &&
2320	2344	!time_after(jiffies,
2321	2345	now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2322	2346	u8 write_ptr = READ_ONCE(txq->write_ptr);
2323	2347
2324		- if (WARN_ONCE(wr_ptr != write_ptr,
	2348	+ /*
	2349	+ * If write pointer moved during the wait, warn only
	2350	+ * if the TX came from op mode. In case TX came from
	2351	+ * trans layer (overflow TX) don't warn.
	2352	+ */
	2353	+ if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
2325	2354	"WR pointer moved while flushing %d -> %d\n",
2326	2355	wr_ptr, write_ptr))
2327	2356	return -ETIMEDOUT;
	2357	+ wr_ptr = write_ptr;
	2358	+
2328	2359	usleep_range(1000, 2000);
	2360	+
	2361	+ spin_lock_bh(&txq->lock);
	2362	+ overflow_tx = txq->overflow_tx \|\|
	2363	+ !skb_queue_empty(&txq->overflow_q);
	2364	+ spin_unlock_bh(&txq->lock);
2329	2365	}
2330	2366
2331	2367	if (txq->read_ptr != txq->write_ptr) {
2332	2368	IWL_ERR(trans,
2333	2369	"fail to flush all tx fifo queues Q %d\n", txq_idx);
2334		- iwl_trans_pcie_log_scd_error(trans, txq);
	2370	+ iwl_txq_log_scd_error(trans, txq);
2335	2371	return -ETIMEDOUT;
2336	2372	}
2337	2373
..	..	@@ -2342,16 +2378,17 @@
2342	2378
2343	2379	static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2344	2380	{
2345		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2346	2381	int cnt;
2347	2382	int ret = 0;
2348	2383
2349	2384	/* waiting for all the tx frames complete might take a while */
2350		- for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
	2385	+ for (cnt = 0;
	2386	+ cnt < trans->trans_cfg->base_params->num_of_queues;
	2387	+ cnt++) {
2351	2388
2352		- if (cnt == trans_pcie->cmd_queue)
	2389	+ if (cnt == trans->txqs.cmd.q_id)
2353	2390	continue;
2354		- if (!test_bit(cnt, trans_pcie->queue_used))
	2391	+ if (!test_bit(cnt, trans->txqs.queue_used))
2355	2392	continue;
2356	2393	if (!(BIT(cnt) & txq_bm))
2357	2394	continue;
..	..	@@ -2368,42 +2405,10 @@
2368	2405	u32 mask, u32 value)
2369	2406	{
2370	2407	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2371		- unsigned long flags;
2372	2408
2373		- spin_lock_irqsave(&trans_pcie->reg_lock, flags);
	2409	+ spin_lock_bh(&trans_pcie->reg_lock);
2374	2410	__iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2375		- spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2376		-}
2377		-
2378		-static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2379		-{
2380		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2381		-
2382		- if (iwlwifi_mod_params.d0i3_disable)
2383		- return;
2384		-
2385		- pm_runtime_get(&trans_pcie->pci_dev->dev);
2386		-
2387		-#ifdef CONFIG_PM
2388		- IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2389		- atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2390		-#endif /* CONFIG_PM */
2391		-}
2392		-
2393		-static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2394		-{
2395		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2396		-
2397		- if (iwlwifi_mod_params.d0i3_disable)
2398		- return;
2399		-
2400		- pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2401		- pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2402		-
2403		-#ifdef CONFIG_PM
2404		- IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2405		- atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2406		-#endif /* CONFIG_PM */
	2411	+ spin_unlock_bh(&trans_pcie->reg_lock);
2407	2412	}
2408	2413
2409	2414	static const char *get_csr_string(int cmd)
..	..	@@ -2482,9 +2487,8 @@
2482	2487	#ifdef CONFIG_IWLWIFI_DEBUGFS
2483	2488	/* create and remove of files */
2484	2489	#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
2485		- if (!debugfs_create_file(#name, mode, parent, trans, \
2486		- &iwl_dbgfs_##name##_ops)) \
2487		- goto err; \
	2490	+ debugfs_create_file(#name, mode, parent, trans, \
	2491	+ &iwl_dbgfs_##name##_ops); \
2488	2492	} while (0)
2489	2493
2490	2494	/* file operation */
..	..	@@ -2510,41 +2514,94 @@
2510	2514	.llseek = generic_file_llseek, \
2511	2515	};
2512	2516
2513		-static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2514		- char __user *user_buf,
2515		- size_t count, loff_t *ppos)
	2517	+struct iwl_dbgfs_tx_queue_priv {
	2518	+ struct iwl_trans *trans;
	2519	+};
	2520	+
	2521	+struct iwl_dbgfs_tx_queue_state {
	2522	+ loff_t pos;
	2523	+};
	2524	+
	2525	+static void iwl_dbgfs_tx_queue_seq_start(struct seq_file seq, loff_t *pos)
2516	2526	{
2517		- struct iwl_trans *trans = file->private_data;
2518		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2519		- struct iwl_txq *txq;
2520		- char *buf;
2521		- int pos = 0;
2522		- int cnt;
2523		- int ret;
2524		- size_t bufsz;
	2527	+ struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
	2528	+ struct iwl_dbgfs_tx_queue_state *state;
2525	2529
2526		- bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
	2530	+ if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
	2531	+ return NULL;
2527	2532
2528		- if (!trans_pcie->txq_memory)
2529		- return -EAGAIN;
	2533	+ state = kmalloc(sizeof(*state), GFP_KERNEL);
	2534	+ if (!state)
	2535	+ return NULL;
	2536	+ state->pos = *pos;
	2537	+ return state;
	2538	+}
2530	2539
2531		- buf = kzalloc(bufsz, GFP_KERNEL);
2532		- if (!buf)
	2540	+static void iwl_dbgfs_tx_queue_seq_next(struct seq_file seq,
	2541	+ void v, loff_t pos)
	2542	+{
	2543	+ struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
	2544	+ struct iwl_dbgfs_tx_queue_state *state = v;
	2545	+
	2546	+ *pos = ++state->pos;
	2547	+
	2548	+ if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
	2549	+ return NULL;
	2550	+
	2551	+ return state;
	2552	+}
	2553	+
	2554	+static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file seq, void v)
	2555	+{
	2556	+ kfree(v);
	2557	+}
	2558	+
	2559	+static int iwl_dbgfs_tx_queue_seq_show(struct seq_file seq, void v)
	2560	+{
	2561	+ struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
	2562	+ struct iwl_dbgfs_tx_queue_state *state = v;
	2563	+ struct iwl_trans *trans = priv->trans;
	2564	+ struct iwl_txq *txq = trans->txqs.txq[state->pos];
	2565	+
	2566	+ seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
	2567	+ (unsigned int)state->pos,
	2568	+ !!test_bit(state->pos, trans->txqs.queue_used),
	2569	+ !!test_bit(state->pos, trans->txqs.queue_stopped));
	2570	+ if (txq)
	2571	+ seq_printf(seq,
	2572	+ "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
	2573	+ txq->read_ptr, txq->write_ptr,
	2574	+ txq->need_update, txq->frozen,
	2575	+ txq->n_window, txq->ampdu);
	2576	+ else
	2577	+ seq_puts(seq, "(unallocated)");
	2578	+
	2579	+ if (state->pos == trans->txqs.cmd.q_id)
	2580	+ seq_puts(seq, " (HCMD)");
	2581	+ seq_puts(seq, "\n");
	2582	+
	2583	+ return 0;
	2584	+}
	2585	+
	2586	+static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {
	2587	+ .start = iwl_dbgfs_tx_queue_seq_start,
	2588	+ .next = iwl_dbgfs_tx_queue_seq_next,
	2589	+ .stop = iwl_dbgfs_tx_queue_seq_stop,
	2590	+ .show = iwl_dbgfs_tx_queue_seq_show,
	2591	+};
	2592	+
	2593	+static int iwl_dbgfs_tx_queue_open(struct inode inode, struct file filp)
	2594	+{
	2595	+ struct iwl_dbgfs_tx_queue_priv *priv;
	2596	+
	2597	+ priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,
	2598	+ sizeof(*priv));
	2599	+
	2600	+ if (!priv)
2533	2601	return -ENOMEM;
2534	2602
2535		- for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2536		- txq = trans_pcie->txq[cnt];
2537		- pos += scnprintf(buf + pos, bufsz - pos,
2538		- "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2539		- cnt, txq->read_ptr, txq->write_ptr,
2540		- !!test_bit(cnt, trans_pcie->queue_used),
2541		- !!test_bit(cnt, trans_pcie->queue_stopped),
2542		- txq->need_update, txq->frozen,
2543		- (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2544		- }
2545		- ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2546		- kfree(buf);
2547		- return ret;
	2603	+ priv->trans = inode->i_private;
	2604	+ return 0;
2548	2605	}
2549	2606
2550	2607	static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
..	..	@@ -2555,7 +2612,7 @@
2555	2612	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2556	2613	char *buf;
2557	2614	int pos = 0, i, ret;
2558		- size_t bufsz = sizeof(buf);
	2615	+ size_t bufsz;
2559	2616
2560	2617	bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2561	2618
..	..	@@ -2727,30 +2784,174 @@
2727	2784	{
2728	2785	struct iwl_trans *trans = file->private_data;
2729	2786	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2730		- bool old = trans_pcie->debug_rfkill;
	2787	+ bool new_value;
2731	2788	int ret;
2732	2789
2733		- ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
	2790	+ ret = kstrtobool_from_user(user_buf, count, &new_value);
2734	2791	if (ret)
2735	2792	return ret;
2736		- if (old == trans_pcie->debug_rfkill)
	2793	+ if (new_value == trans_pcie->debug_rfkill)
2737	2794	return count;
2738	2795	IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2739		- old, trans_pcie->debug_rfkill);
	2796	+ trans_pcie->debug_rfkill, new_value);
	2797	+ trans_pcie->debug_rfkill = new_value;
2740	2798	iwl_pcie_handle_rfkill_irq(trans);
2741	2799
2742	2800	return count;
2743	2801	}
2744	2802
	2803	+static int iwl_dbgfs_monitor_data_open(struct inode *inode,
	2804	+ struct file *file)
	2805	+{
	2806	+ struct iwl_trans *trans = inode->i_private;
	2807	+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	2808	+
	2809	+ if (!trans->dbg.dest_tlv \|\|
	2810	+ trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
	2811	+ IWL_ERR(trans, "Debug destination is not set to DRAM\n");
	2812	+ return -ENOENT;
	2813	+ }
	2814	+
	2815	+ if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
	2816	+ return -EBUSY;
	2817	+
	2818	+ trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
	2819	+ return simple_open(inode, file);
	2820	+}
	2821	+
	2822	+static int iwl_dbgfs_monitor_data_release(struct inode *inode,
	2823	+ struct file *file)
	2824	+{
	2825	+ struct iwl_trans_pcie *trans_pcie =
	2826	+ IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
	2827	+
	2828	+ if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
	2829	+ trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
	2830	+ return 0;
	2831	+}
	2832	+
	2833	+static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
	2834	+ void buf, ssize_t size,
	2835	+ ssize_t *bytes_copied)
	2836	+{
	2837	+ int buf_size_left = count - *bytes_copied;
	2838	+
	2839	+ buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
	2840	+ if (*size > buf_size_left)
	2841	+ *size = buf_size_left;
	2842	+
	2843	+ size -= copy_to_user(user_buf, buf, size);
	2844	+ bytes_copied += size;
	2845	+
	2846	+ if (buf_size_left == *size)
	2847	+ return true;
	2848	+ return false;
	2849	+}
	2850	+
	2851	+static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
	2852	+ char __user *user_buf,
	2853	+ size_t count, loff_t *ppos)
	2854	+{
	2855	+ struct iwl_trans *trans = file->private_data;
	2856	+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	2857	+ void cpu_addr = (void )trans->dbg.fw_mon.block, *curr_buf;
	2858	+ struct cont_rec *data = &trans_pcie->fw_mon_data;
	2859	+ u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
	2860	+ ssize_t size, bytes_copied = 0;
	2861	+ bool b_full;
	2862	+
	2863	+ if (trans->dbg.dest_tlv) {
	2864	+ write_ptr_addr =
	2865	+ le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
	2866	+ wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
	2867	+ } else {
	2868	+ write_ptr_addr = MON_BUFF_WRPTR;
	2869	+ wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
	2870	+ }
	2871	+
	2872	+ if (unlikely(!trans->dbg.rec_on))
	2873	+ return 0;
	2874	+
	2875	+ mutex_lock(&data->mutex);
	2876	+ if (data->state ==
	2877	+ IWL_FW_MON_DBGFS_STATE_DISABLED) {
	2878	+ mutex_unlock(&data->mutex);
	2879	+ return 0;
	2880	+ }
	2881	+
	2882	+ /* write_ptr position in bytes rather then DW */
	2883	+ write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
	2884	+ wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
	2885	+
	2886	+ if (data->prev_wrap_cnt == wrap_cnt) {
	2887	+ size = write_ptr - data->prev_wr_ptr;
	2888	+ curr_buf = cpu_addr + data->prev_wr_ptr;
	2889	+ b_full = iwl_write_to_user_buf(user_buf, count,
	2890	+ curr_buf, &size,
	2891	+ &bytes_copied);
	2892	+ data->prev_wr_ptr += size;
	2893	+
	2894	+ } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
	2895	+ write_ptr < data->prev_wr_ptr) {
	2896	+ size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
	2897	+ curr_buf = cpu_addr + data->prev_wr_ptr;
	2898	+ b_full = iwl_write_to_user_buf(user_buf, count,
	2899	+ curr_buf, &size,
	2900	+ &bytes_copied);
	2901	+ data->prev_wr_ptr += size;
	2902	+
	2903	+ if (!b_full) {
	2904	+ size = write_ptr;
	2905	+ b_full = iwl_write_to_user_buf(user_buf, count,
	2906	+ cpu_addr, &size,
	2907	+ &bytes_copied);
	2908	+ data->prev_wr_ptr = size;
	2909	+ data->prev_wrap_cnt++;
	2910	+ }
	2911	+ } else {
	2912	+ if (data->prev_wrap_cnt == wrap_cnt - 1 &&
	2913	+ write_ptr > data->prev_wr_ptr)
	2914	+ IWL_WARN(trans,
	2915	+ "write pointer passed previous write pointer, start copying from the beginning\n");
	2916	+ else if (!unlikely(data->prev_wrap_cnt == 0 &&
	2917	+ data->prev_wr_ptr == 0))
	2918	+ IWL_WARN(trans,
	2919	+ "monitor data is out of sync, start copying from the beginning\n");
	2920	+
	2921	+ size = write_ptr;
	2922	+ b_full = iwl_write_to_user_buf(user_buf, count,
	2923	+ cpu_addr, &size,
	2924	+ &bytes_copied);
	2925	+ data->prev_wr_ptr = size;
	2926	+ data->prev_wrap_cnt = wrap_cnt;
	2927	+ }
	2928	+
	2929	+ mutex_unlock(&data->mutex);
	2930	+
	2931	+ return bytes_copied;
	2932	+}
	2933	+
2745	2934	DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2746	2935	DEBUGFS_READ_FILE_OPS(fh_reg);
2747	2936	DEBUGFS_READ_FILE_OPS(rx_queue);
2748		-DEBUGFS_READ_FILE_OPS(tx_queue);
2749	2937	DEBUGFS_WRITE_FILE_OPS(csr);
2750	2938	DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
	2939	+static const struct file_operations iwl_dbgfs_tx_queue_ops = {
	2940	+ .owner = THIS_MODULE,
	2941	+ .open = iwl_dbgfs_tx_queue_open,
	2942	+ .read = seq_read,
	2943	+ .llseek = seq_lseek,
	2944	+ .release = seq_release_private,
	2945	+};
	2946	+
	2947	+static const struct file_operations iwl_dbgfs_monitor_data_ops = {
	2948	+ .read = iwl_dbgfs_monitor_data_read,
	2949	+ .open = iwl_dbgfs_monitor_data_open,
	2950	+ .release = iwl_dbgfs_monitor_data_release,
	2951	+};
2751	2952
2752	2953	/* Create the debugfs files and directories */
2753		-int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
	2954	+void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2754	2955	{
2755	2956	struct dentry *dir = trans->dbgfs_dir;
2756	2957
..	..	@@ -2760,22 +2961,27 @@
2760	2961	DEBUGFS_ADD_FILE(csr, dir, 0200);
2761	2962	DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2762	2963	DEBUGFS_ADD_FILE(rfkill, dir, 0600);
2763		- return 0;
	2964	+ DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
	2965	+}
2764	2966
2765		-err:
2766		- IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2767		- return -ENOMEM;
	2967	+static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
	2968	+{
	2969	+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	2970	+ struct cont_rec *data = &trans_pcie->fw_mon_data;
	2971	+
	2972	+ mutex_lock(&data->mutex);
	2973	+ data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
	2974	+ mutex_unlock(&data->mutex);
2768	2975	}
2769	2976	#endif /CONFIG_IWLWIFI_DEBUGFS /
2770	2977
2771	2978	static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans trans, void tfd)
2772	2979	{
2773		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2774	2980	u32 cmdlen = 0;
2775	2981	int i;
2776	2982
2777		- for (i = 0; i < trans_pcie->max_tbs; i++)
2778		- cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
	2983	+ for (i = 0; i < trans->txqs.tfd.max_tbs; i++)
	2984	+ cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);
2779	2985
2780	2986	return cmdlen;
2781	2987	}
..	..	@@ -2785,7 +2991,7 @@
2785	2991	int allocated_rb_nums)
2786	2992	{
2787	2993	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2788		- int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
	2994	+ int max_len = trans_pcie->rx_buf_bytes;
2789	2995	/* Dump RBs is supported only for pre-9000 devices (1 queue) */
2790	2996	struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2791	2997	u32 i, r, j, rb_len = 0;
..	..	@@ -2811,9 +3017,9 @@
2811	3017	rb->index = cpu_to_le32(i);
2812	3018	memcpy(rb->data, page_address(rxb->page), max_len);
2813	3019	/* remap the page for the free benefit */
2814		- rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2815		- max_len,
2816		- DMA_FROM_DEVICE);
	3020	+ rxb->page_dma = dma_map_page(trans->dev, rxb->page,
	3021	+ rxb->offset, max_len,
	3022	+ DMA_FROM_DEVICE);
2817	3023
2818	3024	data = iwl_fw_error_next_data(data);
2819	3025	}
..	..	@@ -2858,12 +3064,13 @@
2858	3064	(*data)->len = cpu_to_le32(fh_regs_len);
2859	3065	val = (void )(data)->data;
2860	3066
2861		- if (!trans->cfg->gen2)
	3067	+ if (!trans->trans_cfg->gen2)
2862	3068	for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2863	3069	i += sizeof(u32))
2864	3070	*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2865	3071	else
2866		- for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2;
	3072	+ for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
	3073	+ i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
2867	3074	i += sizeof(u32))
2868	3075	*val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2869	3076	i));
..	..	@@ -2888,15 +3095,49 @@
2888	3095	if (!iwl_trans_grab_nic_access(trans, &flags))
2889	3096	return 0;
2890	3097
2891		- iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
	3098	+ iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2892	3099	for (i = 0; i < buf_size_in_dwords; i++)
2893		- buffer[i] = iwl_read_prph_no_grab(trans,
2894		- MON_DMARB_RD_DATA_ADDR);
2895		- iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
	3100	+ buffer[i] = iwl_read_umac_prph_no_grab(trans,
	3101	+ MON_DMARB_RD_DATA_ADDR);
	3102	+ iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2896	3103
2897	3104	iwl_trans_release_nic_access(trans, &flags);
2898	3105
2899	3106	return monitor_len;
	3107	+}
	3108	+
	3109	+static void
	3110	+iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
	3111	+ struct iwl_fw_error_dump_fw_mon *fw_mon_data)
	3112	+{
	3113	+ u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
	3114	+
	3115	+ if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
	3116	+ base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
	3117	+ base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
	3118	+ write_ptr = DBGC_CUR_DBGBUF_STATUS;
	3119	+ wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
	3120	+ } else if (trans->dbg.dest_tlv) {
	3121	+ write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
	3122	+ wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
	3123	+ base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
	3124	+ } else {
	3125	+ base = MON_BUFF_BASE_ADDR;
	3126	+ write_ptr = MON_BUFF_WRPTR;
	3127	+ wrap_cnt = MON_BUFF_CYCLE_CNT;
	3128	+ }
	3129	+
	3130	+ write_ptr_val = iwl_read_prph(trans, write_ptr);
	3131	+ fw_mon_data->fw_mon_cycle_cnt =
	3132	+ cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
	3133	+ fw_mon_data->fw_mon_base_ptr =
	3134	+ cpu_to_le32(iwl_read_prph(trans, base));
	3135	+ if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
	3136	+ fw_mon_data->fw_mon_base_high_ptr =
	3137	+ cpu_to_le32(iwl_read_prph(trans, base_high));
	3138	+ write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
	3139	+ }
	3140	+ fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
2900	3141	}
2901	3142
2902	3143	static u32
..	..	@@ -2904,72 +3145,44 @@
2904	3145	struct iwl_fw_error_dump_data **data,
2905	3146	u32 monitor_len)
2906	3147	{
2907		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	3148	+ struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
2908	3149	u32 len = 0;
2909	3150
2910		- if ((trans_pcie->fw_mon_page &&
2911		- trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) \|\|
2912		- trans->dbg_dest_tlv) {
	3151	+ if (trans->dbg.dest_tlv \|\|
	3152	+ (fw_mon->size &&
	3153	+ (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 \|\|
	3154	+ trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
2913	3155	struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2914		- u32 base, write_ptr, wrap_cnt;
2915		-
2916		- /* If there was a dest TLV - use the values from there */
2917		- if (trans->dbg_dest_tlv) {
2918		- write_ptr =
2919		- le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2920		- wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2921		- base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2922		- } else {
2923		- base = MON_BUFF_BASE_ADDR;
2924		- write_ptr = MON_BUFF_WRPTR;
2925		- wrap_cnt = MON_BUFF_CYCLE_CNT;
2926		- }
2927	3156
2928	3157	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2929	3158	fw_mon_data = (void )(data)->data;
2930		- fw_mon_data->fw_mon_wr_ptr =
2931		- cpu_to_le32(iwl_read_prph(trans, write_ptr));
2932		- fw_mon_data->fw_mon_cycle_cnt =
2933		- cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2934		- fw_mon_data->fw_mon_base_ptr =
2935		- cpu_to_le32(iwl_read_prph(trans, base));
	3159	+
	3160	+ iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
2936	3161
2937	3162	len += sizeof(*data) + sizeof(fw_mon_data);
2938		- if (trans_pcie->fw_mon_page) {
2939		- /*
2940		- * The firmware is now asserted, it won't write anything
2941		- * to the buffer. CPU can take ownership to fetch the
2942		- * data. The buffer will be handed back to the device
2943		- * before the firmware will be restarted.
2944		- */
2945		- dma_sync_single_for_cpu(trans->dev,
2946		- trans_pcie->fw_mon_phys,
2947		- trans_pcie->fw_mon_size,
2948		- DMA_FROM_DEVICE);
2949		- memcpy(fw_mon_data->data,
2950		- page_address(trans_pcie->fw_mon_page),
2951		- trans_pcie->fw_mon_size);
2952		-
2953		- monitor_len = trans_pcie->fw_mon_size;
2954		- } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
	3163	+ if (fw_mon->size) {
	3164	+ memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
	3165	+ monitor_len = fw_mon->size;
	3166	+ } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
	3167	+ u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
2955	3168	/*
2956	3169	* Update pointers to reflect actual values after
2957	3170	* shifting
2958	3171	*/
2959		- if (trans->dbg_dest_tlv->version) {
	3172	+ if (trans->dbg.dest_tlv->version) {
2960	3173	base = (iwl_read_prph(trans, base) &
2961	3174	IWL_LDBG_M2S_BUF_BA_MSK) <<
2962		- trans->dbg_dest_tlv->base_shift;
	3175	+ trans->dbg.dest_tlv->base_shift;
2963	3176	base *= IWL_M2S_UNIT_SIZE;
2964	3177	base += trans->cfg->smem_offset;
2965	3178	} else {
2966	3179	base = iwl_read_prph(trans, base) <<
2967		- trans->dbg_dest_tlv->base_shift;
	3180	+ trans->dbg.dest_tlv->base_shift;
2968	3181	}
2969	3182
2970	3183	iwl_trans_read_mem(trans, base, fw_mon_data->data,
2971	3184	monitor_len / sizeof(u32));
2972		- } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
	3185	+ } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
2973	3186	monitor_len =
2974	3187	iwl_trans_pci_dump_marbh_monitor(trans,
2975	3188	fw_mon_data,
..	..	@@ -2986,97 +3199,93 @@
2986	3199	return len;
2987	3200	}
2988	3201
2989		-static struct iwl_trans_dump_data
2990		-iwl_trans_pcie_dump_data(struct iwl_trans trans,
2991		- const struct iwl_fw_dbg_trigger_tlv *trigger)
	3202	+static int iwl_trans_get_fw_monitor_len(struct iwl_trans trans, u32 len)
2992	3203	{
2993		- struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2994		- struct iwl_fw_error_dump_data *data;
2995		- struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
2996		- struct iwl_fw_error_dump_txcmd *txcmd;
2997		- struct iwl_trans_dump_data *dump_data;
2998		- u32 len, num_rbs = 0;
2999		- u32 monitor_len;
3000		- int i, ptr;
3001		- bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3002		- !trans->cfg->mq_rx_supported &&
3003		- trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
	3204	+ if (trans->dbg.fw_mon.size) {
	3205	+ *len += sizeof(struct iwl_fw_error_dump_data) +
	3206	+ sizeof(struct iwl_fw_error_dump_fw_mon) +
	3207	+ trans->dbg.fw_mon.size;
	3208	+ return trans->dbg.fw_mon.size;
	3209	+ } else if (trans->dbg.dest_tlv) {
	3210	+ u32 base, end, cfg_reg, monitor_len;
3004	3211
3005		- /* transport dump header */
3006		- len = sizeof(*dump_data);
3007		-
3008		- /* host commands */
3009		- len += sizeof(*data) +
3010		- cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
3011		-
3012		- /* FW monitor */
3013		- if (trans_pcie->fw_mon_page) {
3014		- len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
3015		- trans_pcie->fw_mon_size;
3016		- monitor_len = trans_pcie->fw_mon_size;
3017		- } else if (trans->dbg_dest_tlv) {
3018		- u32 base, end, cfg_reg;
3019		-
3020		- if (trans->dbg_dest_tlv->version == 1) {
3021		- cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
	3212	+ if (trans->dbg.dest_tlv->version == 1) {
	3213	+ cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3022	3214	cfg_reg = iwl_read_prph(trans, cfg_reg);
3023	3215	base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3024		- trans->dbg_dest_tlv->base_shift;
	3216	+ trans->dbg.dest_tlv->base_shift;
3025	3217	base *= IWL_M2S_UNIT_SIZE;
3026	3218	base += trans->cfg->smem_offset;
3027	3219
3028	3220	monitor_len =
3029	3221	(cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3030		- trans->dbg_dest_tlv->end_shift;
	3222	+ trans->dbg.dest_tlv->end_shift;
3031	3223	monitor_len *= IWL_M2S_UNIT_SIZE;
3032	3224	} else {
3033		- base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
3034		- end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
	3225	+ base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
	3226	+ end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
3035	3227
3036	3228	base = iwl_read_prph(trans, base) <<
3037		- trans->dbg_dest_tlv->base_shift;
	3229	+ trans->dbg.dest_tlv->base_shift;
3038	3230	end = iwl_read_prph(trans, end) <<
3039		- trans->dbg_dest_tlv->end_shift;
	3231	+ trans->dbg.dest_tlv->end_shift;
3040	3232
3041	3233	/* Make "end" point to the actual end */
3042		- if (trans->cfg->device_family >=
	3234	+ if (trans->trans_cfg->device_family >=
3043	3235	IWL_DEVICE_FAMILY_8000 \|\|
3044		- trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
3045		- end += (1 << trans->dbg_dest_tlv->end_shift);
	3236	+ trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
	3237	+ end += (1 << trans->dbg.dest_tlv->end_shift);
3046	3238	monitor_len = end - base;
3047	3239	}
3048		- len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
3049		- monitor_len;
3050		- } else {
3051		- monitor_len = 0;
	3240	+ *len += sizeof(struct iwl_fw_error_dump_data) +
	3241	+ sizeof(struct iwl_fw_error_dump_fw_mon) +
	3242	+ monitor_len;
	3243	+ return monitor_len;
3052	3244	}
	3245	+ return 0;
	3246	+}
3053	3247
3054		- if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
3055		- if (!(trans->dbg_dump_mask &
3056		- BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)))
3057		- return NULL;
	3248	+static struct iwl_trans_dump_data
	3249	+iwl_trans_pcie_dump_data(struct iwl_trans trans,
	3250	+ u32 dump_mask)
	3251	+{
	3252	+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	3253	+ struct iwl_fw_error_dump_data *data;
	3254	+ struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id];
	3255	+ struct iwl_fw_error_dump_txcmd *txcmd;
	3256	+ struct iwl_trans_dump_data *dump_data;
	3257	+ u32 len, num_rbs = 0, monitor_len = 0;
	3258	+ int i, ptr;
	3259	+ bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
	3260	+ !trans->trans_cfg->mq_rx_supported &&
	3261	+ dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3058	3262
3059		- dump_data = vzalloc(len);
3060		- if (!dump_data)
3061		- return NULL;
	3263	+ if (!dump_mask)
	3264	+ return NULL;
3062	3265
3063		- data = (void *)dump_data->data;
3064		- len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3065		- dump_data->len = len;
	3266	+ /* transport dump header */
	3267	+ len = sizeof(*dump_data);
3066	3268
3067		- return dump_data;
3068		- }
	3269	+ /* host commands */
	3270	+ if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
	3271	+ len += sizeof(*data) +
	3272	+ cmdq->n_window * (sizeof(*txcmd) +
	3273	+ TFD_MAX_PAYLOAD_SIZE);
	3274	+
	3275	+ /* FW monitor */
	3276	+ if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
	3277	+ monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
3069	3278
3070	3279	/* CSR registers */
3071		- if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
	3280	+ if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3072	3281	len += sizeof(*data) + IWL_CSR_TO_DUMP;
3073	3282
3074	3283	/* FH registers */
3075		- if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3076		- if (trans->cfg->gen2)
	3284	+ if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
	3285	+ if (trans->trans_cfg->gen2)
3077	3286	len += sizeof(*data) +
3078		- (FH_MEM_UPPER_BOUND_GEN2 -
3079		- FH_MEM_LOWER_BOUND_GEN2);
	3287	+ (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
	3288	+ iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
3080	3289	else
3081	3290	len += sizeof(*data) +
3082	3291	(FH_MEM_UPPER_BOUND -
..	..	@@ -3097,12 +3306,11 @@
3097	3306	}
3098	3307
3099	3308	/* Paged memory for gen2 HW */
3100		- if (trans->cfg->gen2 &&
3101		- trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3102		- for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
	3309	+ if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
	3310	+ for (i = 0; i < trans->init_dram.paging_cnt; i++)
3103	3311	len += sizeof(*data) +
3104	3312	sizeof(struct iwl_fw_error_dump_paging) +
3105		- trans_pcie->init_dram.paging[i].size;
	3313	+ trans->init_dram.paging[i].size;
3106	3314
3107	3315	dump_data = vzalloc(len);
3108	3316	if (!dump_data)
..	..	@@ -3111,20 +3319,26 @@
3111	3319	len = 0;
3112	3320	data = (void *)dump_data->data;
3113	3321
3114		- if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD)) {
3115		- u16 tfd_size = trans_pcie->tfd_size;
	3322	+ if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
	3323	+ u16 tfd_size = trans->txqs.tfd.size;
3116	3324
3117	3325	data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3118	3326	txcmd = (void *)data->data;
3119	3327	spin_lock_bh(&cmdq->lock);
3120	3328	ptr = cmdq->write_ptr;
3121	3329	for (i = 0; i < cmdq->n_window; i++) {
3122		- u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
	3330	+ u8 idx = iwl_txq_get_cmd_index(cmdq, ptr);
	3331	+ u8 tfdidx;
3123	3332	u32 caplen, cmdlen;
3124	3333
	3334	+ if (trans->trans_cfg->use_tfh)
	3335	+ tfdidx = idx;
	3336	+ else
	3337	+ tfdidx = ptr;
	3338	+
3125	3339	cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3126		- cmdq->tfds +
3127		- tfd_size * ptr);
	3340	+ (u8 *)cmdq->tfds +
	3341	+ tfd_size * tfdidx);
3128	3342	caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3129	3343
3130	3344	if (cmdlen) {
..	..	@@ -3136,7 +3350,7 @@
3136	3350	txcmd = (void )((u8 )txcmd->data + caplen);
3137	3351	}
3138	3352
3139		- ptr = iwl_queue_dec_wrap(trans, ptr);
	3353	+ ptr = iwl_txq_dec_wrap(trans, ptr);
3140	3354	}
3141	3355	spin_unlock_bh(&cmdq->lock);
3142	3356
..	..	@@ -3145,36 +3359,32 @@
3145	3359	data = iwl_fw_error_next_data(data);
3146	3360	}
3147	3361
3148		- if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
	3362	+ if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3149	3363	len += iwl_trans_pcie_dump_csr(trans, &data);
3150		- if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
	3364	+ if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3151	3365	len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3152	3366	if (dump_rbs)
3153	3367	len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3154	3368
3155	3369	/* Paged memory for gen2 HW */
3156		- if (trans->cfg->gen2 &&
3157		- trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
3158		- for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
	3370	+ if (trans->trans_cfg->gen2 &&
	3371	+ dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
	3372	+ for (i = 0; i < trans->init_dram.paging_cnt; i++) {
3159	3373	struct iwl_fw_error_dump_paging *paging;
3160		- dma_addr_t addr =
3161		- trans_pcie->init_dram.paging[i].physical;
3162		- u32 page_len = trans_pcie->init_dram.paging[i].size;
	3374	+ u32 page_len = trans->init_dram.paging[i].size;
3163	3375
3164	3376	data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3165	3377	data->len = cpu_to_le32(sizeof(*paging) + page_len);
3166	3378	paging = (void *)data->data;
3167	3379	paging->index = cpu_to_le32(i);
3168		- dma_sync_single_for_cpu(trans->dev, addr, page_len,
3169		- DMA_BIDIRECTIONAL);
3170	3380	memcpy(paging->data,
3171		- trans_pcie->init_dram.paging[i].block, page_len);
	3381	+ trans->init_dram.paging[i].block, page_len);
3172	3382	data = iwl_fw_error_next_data(data);
3173	3383
3174	3384	len += sizeof(data) + sizeof(paging) + page_len;
3175	3385	}
3176	3386	}
3177		- if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
	3387	+ if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3178	3388	len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3179	3389
3180	3390	dump_data->len = len;
..	..	@@ -3185,18 +3395,11 @@
3185	3395	#ifdef CONFIG_PM_SLEEP
3186	3396	static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3187	3397	{
3188		- if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3189		- (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
3190		- return iwl_pci_fw_enter_d0i3(trans);
3191		-
3192	3398	return 0;
3193	3399	}
3194	3400
3195	3401	static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3196	3402	{
3197		- if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3198		- (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
3199		- iwl_pci_fw_exit_d0i3(trans);
3200	3403	}
3201	3404	#endif /* CONFIG_PM_SLEEP */
3202	3405
..	..	@@ -3209,18 +3412,17 @@
3209	3412	.write_prph = iwl_trans_pcie_write_prph, \
3210	3413	.read_mem = iwl_trans_pcie_read_mem, \
3211	3414	.write_mem = iwl_trans_pcie_write_mem, \
	3415	+ .read_config32 = iwl_trans_pcie_read_config32, \
3212	3416	.configure = iwl_trans_pcie_configure, \
3213	3417	.set_pmi = iwl_trans_pcie_set_pmi, \
3214	3418	.sw_reset = iwl_trans_pcie_sw_reset, \
3215	3419	.grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3216	3420	.release_nic_access = iwl_trans_pcie_release_nic_access, \
3217	3421	.set_bits_mask = iwl_trans_pcie_set_bits_mask, \
3218		- .ref = iwl_trans_pcie_ref, \
3219		- .unref = iwl_trans_pcie_unref, \
3220	3422	.dump_data = iwl_trans_pcie_dump_data, \
3221		- .dump_regs = iwl_trans_pcie_dump_regs, \
3222	3423	.d3_suspend = iwl_trans_pcie_d3_suspend, \
3223		- .d3_resume = iwl_trans_pcie_d3_resume
	3424	+ .d3_resume = iwl_trans_pcie_d3_resume, \
	3425	+ .sync_nmi = iwl_trans_pcie_sync_nmi
3224	3426
3225	3427	#ifdef CONFIG_PM_SLEEP
3226	3428	#define IWL_TRANS_PM_OPS \
..	..	@@ -3252,6 +3454,9 @@
3252	3454
3253	3455	.freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3254	3456	.block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
	3457	+#ifdef CONFIG_IWLWIFI_DEBUGFS
	3458	+ .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
	3459	+#endif
3255	3460	};
3256	3461
3257	3462	static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
..	..	@@ -3264,33 +3469,39 @@
3264	3469
3265	3470	.send_cmd = iwl_trans_pcie_gen2_send_hcmd,
3266	3471
3267		- .tx = iwl_trans_pcie_gen2_tx,
	3472	+ .tx = iwl_txq_gen2_tx,
3268	3473	.reclaim = iwl_trans_pcie_reclaim,
3269	3474
3270		- .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3271		- .txq_free = iwl_trans_pcie_dyn_txq_free,
	3475	+ .set_q_ptrs = iwl_trans_pcie_set_q_ptrs,
	3476	+
	3477	+ .txq_alloc = iwl_txq_dyn_alloc,
	3478	+ .txq_free = iwl_txq_dyn_free,
3272	3479	.wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3273	3480	.rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
	3481	+ .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
	3482	+#ifdef CONFIG_IWLWIFI_DEBUGFS
	3483	+ .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
	3484	+#endif
3274	3485	};
3275	3486
3276	3487	struct iwl_trans iwl_trans_pcie_alloc(struct pci_dev pdev,
3277		- const struct pci_device_id *ent,
3278		- const struct iwl_cfg *cfg)
	3488	+ const struct pci_device_id *ent,
	3489	+ const struct iwl_cfg_trans_params *cfg_trans)
3279	3490	{
3280	3491	struct iwl_trans_pcie *trans_pcie;
3281	3492	struct iwl_trans *trans;
3282	3493	int ret, addr_size;
	3494	+ const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
	3495	+
	3496	+ if (!cfg_trans->gen2)
	3497	+ ops = &trans_ops_pcie;
3283	3498
3284	3499	ret = pcim_enable_device(pdev);
3285	3500	if (ret)
3286	3501	return ERR_PTR(ret);
3287	3502
3288		- if (cfg->gen2)
3289		- trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3290		- &pdev->dev, cfg, &trans_ops_pcie_gen2);
3291		- else
3292		- trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3293		- &pdev->dev, cfg, &trans_ops_pcie);
	3503	+ trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
	3504	+ cfg_trans);
3294	3505	if (!trans)
3295	3506	return ERR_PTR(-ENOMEM);
3296	3507
..	..	@@ -3300,6 +3511,7 @@
3300	3511	trans_pcie->opmode_down = true;
3301	3512	spin_lock_init(&trans_pcie->irq_lock);
3302	3513	spin_lock_init(&trans_pcie->reg_lock);
	3514	+ spin_lock_init(&trans_pcie->alloc_page_lock);
3303	3515	mutex_init(&trans_pcie->mutex);
3304	3516	init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3305	3517
..	..	@@ -3311,14 +3523,9 @@
3311	3523	}
3312	3524	INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3313	3525
3314		- trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3315		- if (!trans_pcie->tso_hdr_page) {
3316		- ret = -ENOMEM;
3317		- goto out_no_pci;
3318		- }
	3526	+ trans_pcie->debug_rfkill = -1;
3319	3527
3320		-
3321		- if (!cfg->base_params->pcie_l1_allowed) {
	3528	+ if (!cfg_trans->base_params->pcie_l1_allowed) {
3322	3529	/*
3323	3530	* W/A - seems to solve weird behavior. We need to remove this
3324	3531	* if we don't want to stay in L1 all the time. This wastes a
..	..	@@ -3329,19 +3536,11 @@
3329	3536	PCIE_LINK_STATE_CLKPM);
3330	3537	}
3331	3538
3332		- if (cfg->use_tfh) {
3333		- addr_size = 64;
3334		- trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
3335		- trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
3336		- } else {
3337		- addr_size = 36;
3338		- trans_pcie->max_tbs = IWL_NUM_OF_TBS;
3339		- trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3340		- }
3341		- trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
	3539	+ trans_pcie->def_rx_queue = 0;
3342	3540
3343	3541	pci_set_master(pdev);
3344	3542
	3543	+ addr_size = trans->txqs.tfd.addr_size;
3345	3544	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
3346	3545	if (!ret)
3347	3546	ret = pci_set_consistent_dma_mask(pdev,
..	..	@@ -3379,15 +3578,19 @@
3379	3578	iwl_disable_interrupts(trans);
3380	3579
3381	3580	trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
	3581	+ if (trans->hw_rev == 0xffffffff) {
	3582	+ dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
	3583	+ ret = -EIO;
	3584	+ goto out_no_pci;
	3585	+ }
	3586	+
3382	3587	/*
3383	3588	* In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3384	3589	* changed, and now the revision step also includes bit 0-1 (no more
3385	3590	* "dash" value). To keep hw_rev backwards compatible - we'll store it
3386	3591	* in the old format.
3387	3592	*/
3388		- if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
3389		- unsigned long flags;
3390		-
	3593	+ if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) {
3391	3594	trans->hw_rev = (trans->hw_rev & 0xfff0) \|
3392	3595	(CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3393	3596
..	..	@@ -3401,89 +3604,15 @@
3401	3604	* in-order to recognize C step driver should read chip version
3402	3605	* id located at the AUX bus MISC address space.
3403	3606	*/
3404		- iwl_set_bit(trans, CSR_GP_CNTRL,
3405		- BIT(trans->cfg->csr->flag_init_done));
3406		- udelay(2);
3407		-
3408		- ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3409		- BIT(trans->cfg->csr->flag_mac_clock_ready),
3410		- BIT(trans->cfg->csr->flag_mac_clock_ready),
3411		- 25000);
3412		- if (ret < 0) {
3413		- IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
	3607	+ ret = iwl_finish_nic_init(trans, cfg_trans);
	3608	+ if (ret)
3414	3609	goto out_no_pci;
3415		- }
3416	3610
3417		- if (iwl_trans_grab_nic_access(trans, &flags)) {
3418		- u32 hw_step;
3419		-
3420		- hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
3421		- hw_step \|= ENABLE_WFPM;
3422		- iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3423		- hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
3424		- hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3425		- if (hw_step == 0x3)
3426		- trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) \|
3427		- (SILICON_C_STEP << 2);
3428		- iwl_trans_release_nic_access(trans, &flags);
3429		- }
3430	3611	}
3431	3612
3432		- /*
3433		- * 9000-series integrated A-step has a problem with suspend/resume
3434		- * and sometimes even causes the whole platform to get stuck. This
3435		- * workaround makes the hardware not go into the problematic state.
3436		- */
3437		- if (trans->cfg->integrated &&
3438		- trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
3439		- CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP)
3440		- iwl_set_bit(trans, CSR_HOST_CHICKEN,
3441		- CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
	3613	+ IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3442	3614
3443		-#if IS_ENABLED(CONFIG_IWLMVM)
3444		- trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3445		-
3446		- if (cfg == &iwl22000_2ax_cfg_hr) {
3447		- if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3448		- CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) {
3449		- trans->cfg = &iwl22000_2ax_cfg_hr;
3450		- } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3451		- CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) {
3452		- trans->cfg = &iwl22000_2ax_cfg_jf;
3453		- } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3454		- CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HRCDB)) {
3455		- IWL_ERR(trans, "RF ID HRCDB is not supported\n");
3456		- ret = -EINVAL;
3457		- goto out_no_pci;
3458		- } else {
3459		- IWL_ERR(trans, "Unrecognized RF ID 0x%08x\n",
3460		- CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id));
3461		- ret = -EINVAL;
3462		- goto out_no_pci;
3463		- }
3464		- } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3465		- CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) {
3466		- u32 hw_status;
3467		-
3468		- hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
3469		- if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP)
3470		- /*
3471		- * b step fw is the same for physical card and fpga
3472		- */
3473		- trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0;
3474		- else if ((hw_status & UMAG_GEN_HW_IS_FPGA) &&
3475		- CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) {
3476		- trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0;
3477		- } else {
3478		- /*
3479		- * a step no FPGA
3480		- */
3481		- trans->cfg = &iwl22000_2ac_cfg_hr;
3482		- }
3483		- }
3484		-#endif
3485		-
3486		- iwl_pcie_set_interrupt_capa(pdev, trans);
	3615	+ iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
3487	3616	trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3488	3617	snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3489	3618	"PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
..	..	@@ -3491,7 +3620,8 @@
3491	3620	/* Initialize the wait queue for commands */
3492	3621	init_waitqueue_head(&trans_pcie->wait_command_queue);
3493	3622
3494		- init_waitqueue_head(&trans_pcie->d0i3_waitq);
	3623	+ init_waitqueue_head(&trans_pcie->sx_waitq);
	3624	+
3495	3625
3496	3626	if (trans_pcie->msix_enabled) {
3497	3627	ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
..	..	@@ -3513,20 +3643,65 @@
3513	3643	trans_pcie->inta_mask = CSR_INI_SET_MASK;
3514	3644	}
3515	3645
3516		-#ifdef CONFIG_IWLWIFI_PCIE_RTPM
3517		- trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3518		-#else
3519		- trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3520		-#endif /* CONFIG_IWLWIFI_PCIE_RTPM */
	3646	+#ifdef CONFIG_IWLWIFI_DEBUGFS
	3647	+ trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
	3648	+ mutex_init(&trans_pcie->fw_mon_data.mutex);
	3649	+#endif
	3650	+
	3651	+ iwl_dbg_tlv_init(trans);
3521	3652
3522	3653	return trans;
3523	3654
3524	3655	out_free_ict:
3525	3656	iwl_pcie_free_ict(trans);
3526	3657	out_no_pci:
3527		- free_percpu(trans_pcie->tso_hdr_page);
3528	3658	destroy_workqueue(trans_pcie->rba.alloc_wq);
3529	3659	out_free_trans:
3530	3660	iwl_trans_free(trans);
3531	3661	return ERR_PTR(ret);
3532	3662	}
	3663	+
	3664	+void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
	3665	+{
	3666	+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	3667	+ unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
	3668	+ bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status);
	3669	+ u32 inta_addr, sw_err_bit;
	3670	+
	3671	+ if (trans_pcie->msix_enabled) {
	3672	+ inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
	3673	+ sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
	3674	+ } else {
	3675	+ inta_addr = CSR_INT;
	3676	+ sw_err_bit = CSR_INT_BIT_SW_ERR;
	3677	+ }
	3678	+
	3679	+ /* if the interrupts were already disabled, there is no point in
	3680	+ * calling iwl_disable_interrupts
	3681	+ */
	3682	+ if (interrupts_enabled)
	3683	+ iwl_disable_interrupts(trans);
	3684	+
	3685	+ iwl_force_nmi(trans);
	3686	+ while (time_after(timeout, jiffies)) {
	3687	+ u32 inta_hw = iwl_read32(trans, inta_addr);
	3688	+
	3689	+ /* Error detected by uCode */
	3690	+ if (inta_hw & sw_err_bit) {
	3691	+ /* Clear causes register */
	3692	+ iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
	3693	+ break;
	3694	+ }
	3695	+
	3696	+ mdelay(1);
	3697	+ }
	3698	+
	3699	+ /* enable interrupts only if there were already enabled before this
	3700	+ * function to avoid a case were the driver enable interrupts before
	3701	+ * proper configurations were made
	3702	+ */
	3703	+ if (interrupts_enabled)
	3704	+ iwl_enable_interrupts(trans);
	3705	+
	3706	+ iwl_trans_fw_error(trans);
	3707	+}