~hc/RK356X_SDK_RELEASE.git

..	..	@@ -23,14 +23,11 @@
23	23	#define HCLGE_SHAPER_BS_U_DEF 5
24	24	#define HCLGE_SHAPER_BS_S_DEF 20
25	25
26		-#define HCLGE_ETHER_MAX_RATE 100000
27		-
28	26	/* hclge_shaper_para_calc: calculate ir parameter for the shaper
29	27	* @ir: Rate to be config, its unit is Mbps
30	28	* @shaper_level: the shaper level. eg: port, pg, priority, queueset
31		- * @ir_b: IR_B parameter of IR shaper
32		- * @ir_u: IR_U parameter of IR shaper
33		- * @ir_s: IR_S parameter of IR shaper
	29	+ * @ir_para: parameters of IR shaper
	30	+ * @max_tm_rate: max tm rate is available to config
34	31	*
35	32	* the formula:
36	33	*
..	..	@@ -41,21 +38,26 @@
41	38	* @return: 0: calculate sucessful, negative: fail
42	39	*/
43	40	static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
44		- u8 ir_b, u8 ir_u, u8 *ir_s)
	41	+ struct hclge_shaper_ir_para *ir_para,
	42	+ u32 max_tm_rate)
45	43	{
46		- const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = {
	44	+#define DIVISOR_CLK (1000 * 8)
	45	+#define DIVISOR_IR_B_126 (126 * DIVISOR_CLK)
	46	+
	47	+ static const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = {
47	48	6 * 256, /* Prioriy level */
48	49	6 * 32, /* Prioriy group level */
49	50	6 * 8, /* Port level */
50	51	6 * 256 /* Qset level */
51	52	};
52		- u8 ir_u_calc = 0, ir_s_calc = 0;
	53	+ u8 ir_u_calc = 0;
	54	+ u8 ir_s_calc = 0;
53	55	u32 ir_calc;
54	56	u32 tick;
55	57
56	58	/* Calc tick */
57	59	if (shaper_level >= HCLGE_SHAPER_LVL_CNT \|\|
58		- ir > HCLGE_ETHER_MAX_RATE)
	60	+ ir > max_tm_rate)
59	61	return -EINVAL;
60	62
61	63	tick = tick_array[shaper_level];
..	..	@@ -67,45 +69,44 @@
67	69	* ir_calc = ---------------- * 1000
68	70	* tick * 1
69	71	*/
70		- ir_calc = (1008000 + (tick >> 1) - 1) / tick;
	72	+ ir_calc = (DIVISOR_IR_B_126 + (tick >> 1) - 1) / tick;
71	73
72	74	if (ir_calc == ir) {
73		- *ir_b = 126;
74		- *ir_u = 0;
75		- *ir_s = 0;
	75	+ ir_para->ir_b = 126;
	76	+ ir_para->ir_u = 0;
	77	+ ir_para->ir_s = 0;
76	78
77	79	return 0;
78	80	} else if (ir_calc > ir) {
79	81	/* Increasing the denominator to select ir_s value */
80		- while (ir_calc > ir) {
	82	+ while (ir_calc >= ir && ir) {
81	83	ir_s_calc++;
82		- ir_calc = 1008000 / (tick * (1 << ir_s_calc));
	84	+ ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc));
83	85	}
84	86
85		- if (ir_calc == ir)
86		- *ir_b = 126;
87		- else
88		- ir_b = (ir tick * (1 << ir_s_calc) + 4000) / 8000;
	87	+ ir_para->ir_b = (ir * tick * (1 << ir_s_calc) +
	88	+ (DIVISOR_CLK >> 1)) / DIVISOR_CLK;
89	89	} else {
90	90	/* Increasing the numerator to select ir_u value */
91	91	u32 numerator;
92	92
93	93	while (ir_calc < ir) {
94	94	ir_u_calc++;
95		- numerator = 1008000 * (1 << ir_u_calc);
	95	+ numerator = DIVISOR_IR_B_126 * (1 << ir_u_calc);
96	96	ir_calc = (numerator + (tick >> 1)) / tick;
97	97	}
98	98
99	99	if (ir_calc == ir) {
100		- *ir_b = 126;
	100	+ ir_para->ir_b = 126;
101	101	} else {
102		- u32 denominator = (8000 * (1 << --ir_u_calc));
103		- ir_b = (ir tick + (denominator >> 1)) / denominator;
	102	+ u32 denominator = DIVISOR_CLK * (1 << --ir_u_calc);
	103	+ ir_para->ir_b = (ir * tick + (denominator >> 1)) /
	104	+ denominator;
104	105	}
105	106	}
106	107
107		- *ir_u = ir_u_calc;
108		- *ir_s = ir_s_calc;
	108	+ ir_para->ir_u = ir_u_calc;
	109	+ ir_para->ir_s = ir_s_calc;
109	110
110	111	return 0;
111	112	}
..	..	@@ -120,13 +121,12 @@
120	121	opcode == HCLGE_OPC_QUERY_PFC_TX_PKT_CNT))
121	122	return -EINVAL;
122	123
123		- for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) {
	124	+ for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1; i++) {
124	125	hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
125		- if (i != (HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1))
126		- desc[i].flag \|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
127		- else
128		- desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
	126	+ desc[i].flag \|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
129	127	}
	128	+
	129	+ hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
130	130
131	131	ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_TM_PFC_PKT_GET_CMD_NUM);
132	132	if (ret)
..	..	@@ -173,7 +173,7 @@
173	173	u8 pfc_bitmap)
174	174	{
175	175	struct hclge_desc desc;
176		- struct hclge_pfc_en_cmd pfc = (struct hclge_pfc_en_cmd )&desc.data;
	176	+ struct hclge_pfc_en_cmd pfc = (struct hclge_pfc_en_cmd )desc.data;
177	177
178	178	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PFC_PAUSE_EN, false);
179	179
..	..	@@ -189,11 +189,12 @@
189	189	struct hclge_cfg_pause_param_cmd *pause_param;
190	190	struct hclge_desc desc;
191	191
192		- pause_param = (struct hclge_cfg_pause_param_cmd *)&desc.data;
	192	+ pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
193	193
194	194	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, false);
195	195
196	196	ether_addr_copy(pause_param->mac_addr, addr);
	197	+ ether_addr_copy(pause_param->mac_addr_extra, addr);
197	198	pause_param->pause_trans_gap = pause_trans_gap;
198	199	pause_param->pause_trans_time = cpu_to_le16(pause_trans_time);
199	200
..	..	@@ -208,7 +209,7 @@
208	209	u8 trans_gap;
209	210	int ret;
210	211
211		- pause_param = (struct hclge_cfg_pause_param_cmd *)&desc.data;
	212	+ pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
212	213
213	214	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true);
214	215
..	..	@@ -219,8 +220,7 @@
219	220	trans_gap = pause_param->pause_trans_gap;
220	221	trans_time = le16_to_cpu(pause_param->pause_trans_time);
221	222
222		- return hclge_pause_param_cfg(hdev, mac_addr, trans_gap,
223		- trans_time);
	223	+ return hclge_pause_param_cfg(hdev, mac_addr, trans_gap, trans_time);
224	224	}
225	225
226	226	static int hclge_fill_pri_array(struct hclge_dev hdev, u8 pri, u8 pri_id)
..	..	@@ -361,28 +361,35 @@
361	361	return hclge_cmd_send(&hdev->hw, &desc, 1);
362	362	}
363	363
364		-static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev,
365		- enum hclge_shap_bucket bucket, u8 pg_id,
366		- u8 ir_b, u8 ir_u, u8 ir_s, u8 bs_b, u8 bs_s)
	364	+static u32 hclge_tm_get_shapping_para(u8 ir_b, u8 ir_u, u8 ir_s,
	365	+ u8 bs_b, u8 bs_s)
367	366	{
368		- struct hclge_pg_shapping_cmd *shap_cfg_cmd;
369		- enum hclge_opcode_type opcode;
370		- struct hclge_desc desc;
371	367	u32 shapping_para = 0;
372		-
373		- opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING :
374		- HCLGE_OPC_TM_PG_C_SHAPPING;
375		- hclge_cmd_setup_basic_desc(&desc, opcode, false);
376		-
377		- shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
378		-
379		- shap_cfg_cmd->pg_id = pg_id;
380	368
381	369	hclge_tm_set_field(shapping_para, IR_B, ir_b);
382	370	hclge_tm_set_field(shapping_para, IR_U, ir_u);
383	371	hclge_tm_set_field(shapping_para, IR_S, ir_s);
384	372	hclge_tm_set_field(shapping_para, BS_B, bs_b);
385	373	hclge_tm_set_field(shapping_para, BS_S, bs_s);
	374	+
	375	+ return shapping_para;
	376	+}
	377	+
	378	+static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev,
	379	+ enum hclge_shap_bucket bucket, u8 pg_id,
	380	+ u32 shapping_para)
	381	+{
	382	+ struct hclge_pg_shapping_cmd *shap_cfg_cmd;
	383	+ enum hclge_opcode_type opcode;
	384	+ struct hclge_desc desc;
	385	+
	386	+ opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING :
	387	+ HCLGE_OPC_TM_PG_C_SHAPPING;
	388	+ hclge_cmd_setup_basic_desc(&desc, opcode, false);
	389	+
	390	+ shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
	391	+
	392	+ shap_cfg_cmd->pg_id = pg_id;
386	393
387	394	shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para);
388	395
..	..	@@ -392,25 +399,24 @@
392	399	static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev)
393	400	{
394	401	struct hclge_port_shapping_cmd *shap_cfg_cmd;
	402	+ struct hclge_shaper_ir_para ir_para;
395	403	struct hclge_desc desc;
396		- u32 shapping_para = 0;
397		- u8 ir_u, ir_b, ir_s;
	404	+ u32 shapping_para;
398	405	int ret;
399	406
400		- ret = hclge_shaper_para_calc(HCLGE_ETHER_MAX_RATE,
401		- HCLGE_SHAPER_LVL_PORT,
402		- &ir_b, &ir_u, &ir_s);
	407	+ ret = hclge_shaper_para_calc(hdev->hw.mac.speed, HCLGE_SHAPER_LVL_PORT,
	408	+ &ir_para,
	409	+ hdev->ae_dev->dev_specs.max_tm_rate);
403	410	if (ret)
404	411	return ret;
405	412
406	413	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, false);
407	414	shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data;
408	415
409		- hclge_tm_set_field(shapping_para, IR_B, ir_b);
410		- hclge_tm_set_field(shapping_para, IR_U, ir_u);
411		- hclge_tm_set_field(shapping_para, IR_S, ir_s);
412		- hclge_tm_set_field(shapping_para, BS_B, HCLGE_SHAPER_BS_U_DEF);
413		- hclge_tm_set_field(shapping_para, BS_S, HCLGE_SHAPER_BS_S_DEF);
	416	+ shapping_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
	417	+ ir_para.ir_s,
	418	+ HCLGE_SHAPER_BS_U_DEF,
	419	+ HCLGE_SHAPER_BS_S_DEF);
414	420
415	421	shap_cfg_cmd->port_shapping_para = cpu_to_le32(shapping_para);
416	422
..	..	@@ -419,28 +425,20 @@
419	425
420	426	static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev,
421	427	enum hclge_shap_bucket bucket, u8 pri_id,
422		- u8 ir_b, u8 ir_u, u8 ir_s,
423		- u8 bs_b, u8 bs_s)
	428	+ u32 shapping_para)
424	429	{
425	430	struct hclge_pri_shapping_cmd *shap_cfg_cmd;
426	431	enum hclge_opcode_type opcode;
427	432	struct hclge_desc desc;
428		- u32 shapping_para = 0;
429	433
430	434	opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING :
431		- HCLGE_OPC_TM_PRI_C_SHAPPING;
	435	+ HCLGE_OPC_TM_PRI_C_SHAPPING;
432	436
433	437	hclge_cmd_setup_basic_desc(&desc, opcode, false);
434	438
435	439	shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
436	440
437	441	shap_cfg_cmd->pri_id = pri_id;
438		-
439		- hclge_tm_set_field(shapping_para, IR_B, ir_b);
440		- hclge_tm_set_field(shapping_para, IR_U, ir_u);
441		- hclge_tm_set_field(shapping_para, IR_S, ir_s);
442		- hclge_tm_set_field(shapping_para, BS_B, bs_b);
443		- hclge_tm_set_field(shapping_para, BS_S, bs_s);
444	442
445	443	shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para);
446	444
..	..	@@ -513,24 +511,97 @@
513	511	return hclge_cmd_send(&hdev->hw, &desc, 1);
514	512	}
515	513
	514	+int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate)
	515	+{
	516	+ struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
	517	+ struct hclge_qs_shapping_cmd *shap_cfg_cmd;
	518	+ struct hclge_shaper_ir_para ir_para;
	519	+ struct hclge_dev *hdev = vport->back;
	520	+ struct hclge_desc desc;
	521	+ u32 shaper_para;
	522	+ int ret, i;
	523	+
	524	+ if (!max_tx_rate)
	525	+ max_tx_rate = hdev->ae_dev->dev_specs.max_tm_rate;
	526	+
	527	+ ret = hclge_shaper_para_calc(max_tx_rate, HCLGE_SHAPER_LVL_QSET,
	528	+ &ir_para,
	529	+ hdev->ae_dev->dev_specs.max_tm_rate);
	530	+ if (ret)
	531	+ return ret;
	532	+
	533	+ shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
	534	+ ir_para.ir_s,
	535	+ HCLGE_SHAPER_BS_U_DEF,
	536	+ HCLGE_SHAPER_BS_S_DEF);
	537	+
	538	+ for (i = 0; i < kinfo->num_tc; i++) {
	539	+ hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QCN_SHAPPING_CFG,
	540	+ false);
	541	+
	542	+ shap_cfg_cmd = (struct hclge_qs_shapping_cmd *)desc.data;
	543	+ shap_cfg_cmd->qs_id = cpu_to_le16(vport->qs_offset + i);
	544	+ shap_cfg_cmd->qs_shapping_para = cpu_to_le32(shaper_para);
	545	+
	546	+ ret = hclge_cmd_send(&hdev->hw, &desc, 1);
	547	+ if (ret) {
	548	+ dev_err(&hdev->pdev->dev,
	549	+ "vf%u, qs%u failed to set tx_rate:%d, ret=%d\n",
	550	+ vport->vport_id, shap_cfg_cmd->qs_id,
	551	+ max_tx_rate, ret);
	552	+ return ret;
	553	+ }
	554	+ }
	555	+
	556	+ return 0;
	557	+}
	558	+
516	559	static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
517	560	{
518	561	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
519	562	struct hclge_dev *hdev = vport->back;
	563	+ u16 max_rss_size;
520	564	u8 i;
521	565
522		- vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit;
523		- kinfo->num_tc =
524		- min_t(u16, kinfo->num_tqps, hdev->tm_info.num_tc);
525		- kinfo->rss_size
526		- = min_t(u16, hdev->rss_size_max,
527		- kinfo->num_tqps / kinfo->num_tc);
528		- vport->qs_offset = hdev->tm_info.num_tc * vport->vport_id;
	566	+ /* TC configuration is shared by PF/VF in one port, only allow
	567	+ * one tc for VF for simplicity. VF's vport_id is non zero.
	568	+ */
	569	+ kinfo->num_tc = vport->vport_id ? 1 :
	570	+ min_t(u16, vport->alloc_tqps, hdev->tm_info.num_tc);
	571	+ vport->qs_offset = (vport->vport_id ? HNAE3_MAX_TC : 0) +
	572	+ (vport->vport_id ? (vport->vport_id - 1) : 0);
	573	+
	574	+ max_rss_size = min_t(u16, hdev->rss_size_max,
	575	+ vport->alloc_tqps / kinfo->num_tc);
	576	+
	577	+ /* Set to user value, no larger than max_rss_size. */
	578	+ if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
	579	+ kinfo->req_rss_size <= max_rss_size) {
	580	+ dev_info(&hdev->pdev->dev, "rss changes from %u to %u\n",
	581	+ kinfo->rss_size, kinfo->req_rss_size);
	582	+ kinfo->rss_size = kinfo->req_rss_size;
	583	+ } else if (kinfo->rss_size > max_rss_size \|\|
	584	+ (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) {
	585	+ /* if user not set rss, the rss_size should compare with the
	586	+ * valid msi numbers to ensure one to one map between tqp and
	587	+ * irq as default.
	588	+ */
	589	+ if (!kinfo->req_rss_size)
	590	+ max_rss_size = min_t(u16, max_rss_size,
	591	+ (hdev->num_nic_msi - 1) /
	592	+ kinfo->num_tc);
	593	+
	594	+ /* Set to the maximum specification value (max_rss_size). */
	595	+ kinfo->rss_size = max_rss_size;
	596	+ }
	597	+
	598	+ kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size;
529	599	vport->dwrr = 100; /* 100 percent as init */
530	600	vport->alloc_rss_size = kinfo->rss_size;
	601	+ vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit;
531	602
532		- for (i = 0; i < kinfo->num_tc; i++) {
533		- if (hdev->hw_tc_map & BIT(i)) {
	603	+ for (i = 0; i < HNAE3_MAX_TC; i++) {
	604	+ if (hdev->hw_tc_map & BIT(i) && i < kinfo->num_tc) {
534	605	kinfo->tc_info[i].enable = true;
535	606	kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
536	607	kinfo->tc_info[i].tqp_count = kinfo->rss_size;
..	..	@@ -545,7 +616,7 @@
545	616	}
546	617
547	618	memcpy(kinfo->prio_tc, hdev->tm_info.prio_tc,
548		- FIELD_SIZEOF(struct hnae3_knic_private_info, prio_tc));
	619	+ sizeof_field(struct hnae3_knic_private_info, prio_tc));
549	620	}
550	621
551	622	static void hclge_tm_vport_info_update(struct hclge_dev *hdev)
..	..	@@ -575,43 +646,42 @@
575	646	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
576	647	hdev->tm_info.prio_tc[i] =
577	648	(i >= hdev->tm_info.num_tc) ? 0 : i;
578		-
579		- /* DCB is enabled if we have more than 1 TC */
580		- if (hdev->tm_info.num_tc > 1)
581		- hdev->flag \|= HCLGE_FLAG_DCB_ENABLE;
582		- else
583		- hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
584	649	}
585	650
586	651	static void hclge_tm_pg_info_init(struct hclge_dev *hdev)
587	652	{
	653	+#define BW_PERCENT 100
	654	+
588	655	u8 i;
589	656
590	657	for (i = 0; i < hdev->tm_info.num_pg; i++) {
591	658	int k;
592	659
593		- hdev->tm_info.pg_dwrr[i] = i ? 0 : 100;
	660	+ hdev->tm_info.pg_dwrr[i] = i ? 0 : BW_PERCENT;
594	661
595	662	hdev->tm_info.pg_info[i].pg_id = i;
596	663	hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR;
597	664
598		- hdev->tm_info.pg_info[i].bw_limit = HCLGE_ETHER_MAX_RATE;
	665	+ hdev->tm_info.pg_info[i].bw_limit =
	666	+ hdev->ae_dev->dev_specs.max_tm_rate;
599	667
600	668	if (i != 0)
601	669	continue;
602	670
603	671	hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map;
604	672	for (k = 0; k < hdev->tm_info.num_tc; k++)
605		- hdev->tm_info.pg_info[i].tc_dwrr[k] = 100;
	673	+ hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT;
	674	+ for (; k < HNAE3_MAX_TC; k++)
	675	+ hdev->tm_info.pg_info[i].tc_dwrr[k] = 0;
606	676	}
607	677	}
608	678
609		-static void hclge_pfc_info_init(struct hclge_dev *hdev)
	679	+static void hclge_update_fc_mode_by_dcb_flag(struct hclge_dev *hdev)
610	680	{
611		- if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE)) {
	681	+ if (hdev->tm_info.num_tc == 1 && !hdev->tm_info.pfc_en) {
612	682	if (hdev->fc_mode_last_time == HCLGE_FC_PFC)
613	683	dev_warn(&hdev->pdev->dev,
614		- "DCB is disable, but last mode is FC_PFC\n");
	684	+ "Only 1 tc used, but last mode is FC_PFC\n");
615	685
616	686	hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
617	687	} else if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) {
..	..	@@ -624,21 +694,36 @@
624	694	}
625	695	}
626	696
627		-static int hclge_tm_schd_info_init(struct hclge_dev *hdev)
	697	+static void hclge_update_fc_mode(struct hclge_dev *hdev)
628	698	{
629		- if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) &&
630		- (hdev->tm_info.num_pg != 1))
631		- return -EINVAL;
	699	+ if (!hdev->tm_info.pfc_en) {
	700	+ hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
	701	+ return;
	702	+ }
632	703
	704	+ if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) {
	705	+ hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
	706	+ hdev->tm_info.fc_mode = HCLGE_FC_PFC;
	707	+ }
	708	+}
	709	+
	710	+void hclge_tm_pfc_info_update(struct hclge_dev *hdev)
	711	+{
	712	+ if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
	713	+ hclge_update_fc_mode(hdev);
	714	+ else
	715	+ hclge_update_fc_mode_by_dcb_flag(hdev);
	716	+}
	717	+
	718	+static void hclge_tm_schd_info_init(struct hclge_dev *hdev)
	719	+{
633	720	hclge_tm_pg_info_init(hdev);
634	721
635	722	hclge_tm_tc_info_init(hdev);
636	723
637	724	hclge_tm_vport_info_update(hdev);
638	725
639		- hclge_pfc_info_init(hdev);
640		-
641		- return 0;
	726	+ hclge_tm_pfc_info_update(hdev);
642	727	}
643	728
644	729	static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev)
..	..	@@ -662,7 +747,9 @@
662	747
663	748	static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev)
664	749	{
665		- u8 ir_u, ir_b, ir_s;
	750	+ u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
	751	+ struct hclge_shaper_ir_para ir_para;
	752	+ u32 shaper_para;
666	753	int ret;
667	754	u32 i;
668	755
..	..	@@ -673,25 +760,29 @@
673	760	/* Pg to pri */
674	761	for (i = 0; i < hdev->tm_info.num_pg; i++) {
675	762	/* Calc shaper para */
676		- ret = hclge_shaper_para_calc(
677		- hdev->tm_info.pg_info[i].bw_limit,
678		- HCLGE_SHAPER_LVL_PG,
679		- &ir_b, &ir_u, &ir_s);
	763	+ ret = hclge_shaper_para_calc(hdev->tm_info.pg_info[i].bw_limit,
	764	+ HCLGE_SHAPER_LVL_PG,
	765	+ &ir_para, max_tm_rate);
680	766	if (ret)
681	767	return ret;
682	768
	769	+ shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
	770	+ HCLGE_SHAPER_BS_U_DEF,
	771	+ HCLGE_SHAPER_BS_S_DEF);
683	772	ret = hclge_tm_pg_shapping_cfg(hdev,
684	773	HCLGE_TM_SHAP_C_BUCKET, i,
685		- 0, 0, 0, HCLGE_SHAPER_BS_U_DEF,
686		- HCLGE_SHAPER_BS_S_DEF);
	774	+ shaper_para);
687	775	if (ret)
688	776	return ret;
689	777
	778	+ shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b,
	779	+ ir_para.ir_u,
	780	+ ir_para.ir_s,
	781	+ HCLGE_SHAPER_BS_U_DEF,
	782	+ HCLGE_SHAPER_BS_S_DEF);
690	783	ret = hclge_tm_pg_shapping_cfg(hdev,
691	784	HCLGE_TM_SHAP_P_BUCKET, i,
692		- ir_b, ir_u, ir_s,
693		- HCLGE_SHAPER_BS_U_DEF,
694		- HCLGE_SHAPER_BS_S_DEF);
	785	+ shaper_para);
695	786	if (ret)
696	787	return ret;
697	788	}
..	..	@@ -711,8 +802,7 @@
711	802	/* pg to prio */
712	803	for (i = 0; i < hdev->tm_info.num_pg; i++) {
713	804	/* Cfg dwrr */
714		- ret = hclge_tm_pg_weight_cfg(hdev, i,
715		- hdev->tm_info.pg_dwrr[i]);
	805	+ ret = hclge_tm_pg_weight_cfg(hdev, i, hdev->tm_info.pg_dwrr[i]);
716	806	if (ret)
717	807	return ret;
718	808	}
..	..	@@ -753,13 +843,17 @@
753	843
754	844	if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
755	845	/* Cfg qs -> pri mapping, one by one mapping */
756		- for (k = 0; k < hdev->num_alloc_vport; k++)
757		- for (i = 0; i < hdev->tm_info.num_tc; i++) {
	846	+ for (k = 0; k < hdev->num_alloc_vport; k++) {
	847	+ struct hnae3_knic_private_info *kinfo =
	848	+ &vport[k].nic.kinfo;
	849	+
	850	+ for (i = 0; i < kinfo->num_tc; i++) {
758	851	ret = hclge_tm_qs_to_pri_map_cfg(
759	852	hdev, vport[k].qs_offset + i, i);
760	853	if (ret)
761	854	return ret;
762	855	}
	856	+ }
763	857	} else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) {
764	858	/* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */
765	859	for (k = 0; k < hdev->num_alloc_vport; k++)
..	..	@@ -787,29 +881,34 @@
787	881
788	882	static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
789	883	{
790		- u8 ir_u, ir_b, ir_s;
	884	+ u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
	885	+ struct hclge_shaper_ir_para ir_para;
	886	+ u32 shaper_para;
791	887	int ret;
792	888	u32 i;
793	889
794	890	for (i = 0; i < hdev->tm_info.num_tc; i++) {
795		- ret = hclge_shaper_para_calc(
796		- hdev->tm_info.tc_info[i].bw_limit,
797		- HCLGE_SHAPER_LVL_PRI,
798		- &ir_b, &ir_u, &ir_s);
	891	+ ret = hclge_shaper_para_calc(hdev->tm_info.tc_info[i].bw_limit,
	892	+ HCLGE_SHAPER_LVL_PRI,
	893	+ &ir_para, max_tm_rate);
799	894	if (ret)
800	895	return ret;
801	896
802		- ret = hclge_tm_pri_shapping_cfg(
803		- hdev, HCLGE_TM_SHAP_C_BUCKET, i,
804		- 0, 0, 0, HCLGE_SHAPER_BS_U_DEF,
805		- HCLGE_SHAPER_BS_S_DEF);
	897	+ shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
	898	+ HCLGE_SHAPER_BS_U_DEF,
	899	+ HCLGE_SHAPER_BS_S_DEF);
	900	+ ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, i,
	901	+ shaper_para);
806	902	if (ret)
807	903	return ret;
808	904
809		- ret = hclge_tm_pri_shapping_cfg(
810		- hdev, HCLGE_TM_SHAP_P_BUCKET, i,
811		- ir_b, ir_u, ir_s, HCLGE_SHAPER_BS_U_DEF,
812		- HCLGE_SHAPER_BS_S_DEF);
	905	+ shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b,
	906	+ ir_para.ir_u,
	907	+ ir_para.ir_s,
	908	+ HCLGE_SHAPER_BS_U_DEF,
	909	+ HCLGE_SHAPER_BS_S_DEF);
	910	+ ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, i,
	911	+ shaper_para);
813	912	if (ret)
814	913	return ret;
815	914	}
..	..	@@ -820,26 +919,30 @@
820	919	static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport)
821	920	{
822	921	struct hclge_dev *hdev = vport->back;
823		- u8 ir_u, ir_b, ir_s;
	922	+ struct hclge_shaper_ir_para ir_para;
	923	+ u32 shaper_para;
824	924	int ret;
825	925
826	926	ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF,
827		- &ir_b, &ir_u, &ir_s);
	927	+ &ir_para,
	928	+ hdev->ae_dev->dev_specs.max_tm_rate);
828	929	if (ret)
829	930	return ret;
830	931
	932	+ shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
	933	+ HCLGE_SHAPER_BS_U_DEF,
	934	+ HCLGE_SHAPER_BS_S_DEF);
831	935	ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET,
832		- vport->vport_id,
833		- 0, 0, 0, HCLGE_SHAPER_BS_U_DEF,
834		- HCLGE_SHAPER_BS_S_DEF);
	936	+ vport->vport_id, shaper_para);
835	937	if (ret)
836	938	return ret;
837	939
	940	+ shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
	941	+ ir_para.ir_s,
	942	+ HCLGE_SHAPER_BS_U_DEF,
	943	+ HCLGE_SHAPER_BS_S_DEF);
838	944	ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET,
839		- vport->vport_id,
840		- ir_b, ir_u, ir_s,
841		- HCLGE_SHAPER_BS_U_DEF,
842		- HCLGE_SHAPER_BS_S_DEF);
	945	+ vport->vport_id, shaper_para);
843	946	if (ret)
844	947	return ret;
845	948
..	..	@@ -850,15 +953,15 @@
850	953	{
851	954	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
852	955	struct hclge_dev *hdev = vport->back;
853		- u8 ir_u, ir_b, ir_s;
	956	+ u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
	957	+ struct hclge_shaper_ir_para ir_para;
854	958	u32 i;
855	959	int ret;
856	960
857	961	for (i = 0; i < kinfo->num_tc; i++) {
858		- ret = hclge_shaper_para_calc(
859		- hdev->tm_info.tc_info[i].bw_limit,
860		- HCLGE_SHAPER_LVL_QSET,
861		- &ir_b, &ir_u, &ir_s);
	962	+ ret = hclge_shaper_para_calc(hdev->tm_info.tc_info[i].bw_limit,
	963	+ HCLGE_SHAPER_LVL_QSET,
	964	+ &ir_para, max_tm_rate);
862	965	if (ret)
863	966	return ret;
864	967	}
..	..	@@ -934,6 +1037,29 @@
934	1037	return 0;
935	1038	}
936	1039
	1040	+static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev)
	1041	+{
	1042	+#define DEFAULT_TC_OFFSET 14
	1043	+
	1044	+ struct hclge_ets_tc_weight_cmd *ets_weight;
	1045	+ struct hclge_desc desc;
	1046	+ unsigned int i;
	1047	+
	1048	+ hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, false);
	1049	+ ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data;
	1050	+
	1051	+ for (i = 0; i < HNAE3_MAX_TC; i++) {
	1052	+ struct hclge_pg_info *pg_info;
	1053	+
	1054	+ pg_info = &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
	1055	+ ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
	1056	+ }
	1057	+
	1058	+ ets_weight->weight_offset = DEFAULT_TC_OFFSET;
	1059	+
	1060	+ return hclge_cmd_send(&hdev->hw, &desc, 1);
	1061	+}
	1062	+
937	1063	static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport)
938	1064	{
939	1065	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
..	..	@@ -983,6 +1109,19 @@
983	1109	ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev);
984	1110	if (ret)
985	1111	return ret;
	1112	+
	1113	+ if (!hnae3_dev_dcb_supported(hdev))
	1114	+ return 0;
	1115	+
	1116	+ ret = hclge_tm_ets_tc_dwrr_cfg(hdev);
	1117	+ if (ret == -EOPNOTSUPP) {
	1118	+ dev_warn(&hdev->pdev->dev,
	1119	+ "fw %08x does't support ets tc weight cmd\n",
	1120	+ hdev->fw_version);
	1121	+ ret = 0;
	1122	+ }
	1123	+
	1124	+ return ret;
986	1125	} else {
987	1126	ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev);
988	1127	if (ret)
..	..	@@ -992,7 +1131,7 @@
992	1131	return 0;
993	1132	}
994	1133
995		-int hclge_tm_map_cfg(struct hclge_dev *hdev)
	1134	+static int hclge_tm_map_cfg(struct hclge_dev *hdev)
996	1135	{
997	1136	int ret;
998	1137
..	..	@@ -1110,7 +1249,7 @@
1110	1249	return 0;
1111	1250	}
1112	1251
1113		-int hclge_tm_schd_mode_hw(struct hclge_dev *hdev)
	1252	+static int hclge_tm_schd_mode_hw(struct hclge_dev *hdev)
1114	1253	{
1115	1254	int ret;
1116	1255
..	..	@@ -1121,7 +1260,7 @@
1121	1260	return hclge_tm_lvl34_schd_mode_cfg(hdev);
1122	1261	}
1123	1262
1124		-static int hclge_tm_schd_setup_hw(struct hclge_dev *hdev)
	1263	+int hclge_tm_schd_setup_hw(struct hclge_dev *hdev)
1125	1264	{
1126	1265	int ret;
1127	1266
..	..	@@ -1149,8 +1288,8 @@
1149	1288	struct hclge_mac *mac = &hdev->hw.mac;
1150	1289
1151	1290	return hclge_pause_param_cfg(hdev, mac->mac_addr,
1152		- HCLGE_DEFAULT_PAUSE_TRANS_GAP,
1153		- HCLGE_DEFAULT_PAUSE_TRANS_TIME);
	1291	+ HCLGE_DEFAULT_PAUSE_TRANS_GAP,
	1292	+ HCLGE_DEFAULT_PAUSE_TRANS_TIME);
1154	1293	}
1155	1294
1156	1295	static int hclge_pfc_setup_hw(struct hclge_dev *hdev)
..	..	@@ -1231,10 +1370,23 @@
1231	1370	return hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
1232	1371	}
1233	1372
1234		-int hclge_pause_setup_hw(struct hclge_dev *hdev)
	1373	+static int hclge_tm_bp_setup(struct hclge_dev *hdev)
1235	1374	{
1236	1375	int ret;
1237		- u8 i;
	1376	+ int i;
	1377	+
	1378	+ for (i = 0; i < hdev->tm_info.num_tc; i++) {
	1379	+ ret = hclge_bp_setup_hw(hdev, i);
	1380	+ if (ret)
	1381	+ return ret;
	1382	+ }
	1383	+
	1384	+ return 0;
	1385	+}
	1386	+
	1387	+int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init)
	1388	+{
	1389	+ int ret;
1238	1390
1239	1391	ret = hclge_pause_param_setup_hw(hdev);
1240	1392	if (ret)
..	..	@@ -1248,29 +1400,29 @@
1248	1400	if (!hnae3_dev_dcb_supported(hdev))
1249	1401	return 0;
1250	1402
1251		- /* When MAC is GE Mode, hdev does not support pfc setting */
	1403	+ /* GE MAC does not support PFC, when driver is initializing and MAC
	1404	+ * is in GE Mode, ignore the error here, otherwise initialization
	1405	+ * will fail.
	1406	+ */
1252	1407	ret = hclge_pfc_setup_hw(hdev);
1253		- if (ret)
1254		- dev_warn(&hdev->pdev->dev, "set pfc pause failed:%d\n", ret);
1255		-
1256		- for (i = 0; i < hdev->tm_info.num_tc; i++) {
1257		- ret = hclge_bp_setup_hw(hdev, i);
1258		- if (ret)
1259		- return ret;
	1408	+ if (init && ret == -EOPNOTSUPP)
	1409	+ dev_warn(&hdev->pdev->dev, "GE MAC does not support pfc\n");
	1410	+ else if (ret) {
	1411	+ dev_err(&hdev->pdev->dev, "config pfc failed! ret = %d\n",
	1412	+ ret);
	1413	+ return ret;
1260	1414	}
1261	1415
1262		- return 0;
	1416	+ return hclge_tm_bp_setup(hdev);
1263	1417	}
1264	1418
1265		-int hclge_tm_prio_tc_info_update(struct hclge_dev hdev, u8 prio_tc)
	1419	+void hclge_tm_prio_tc_info_update(struct hclge_dev hdev, u8 prio_tc)
1266	1420	{
1267	1421	struct hclge_vport *vport = hdev->vport;
1268	1422	struct hnae3_knic_private_info *kinfo;
1269	1423	u32 i, k;
1270	1424
1271	1425	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
1272		- if (prio_tc[i] >= hdev->tm_info.num_tc)
1273		- return -EINVAL;
1274	1426	hdev->tm_info.prio_tc[i] = prio_tc[i];
1275	1427
1276	1428	for (k = 0; k < hdev->num_alloc_vport; k++) {
..	..	@@ -1278,12 +1430,12 @@
1278	1430	kinfo->prio_tc[i] = prio_tc[i];
1279	1431	}
1280	1432	}
1281		- return 0;
1282	1433	}
1283	1434
1284	1435	void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc)
1285	1436	{
1286		- u8 i, bit_map = 0;
	1437	+ u8 bit_map = 0;
	1438	+ u8 i;
1287	1439
1288	1440	hdev->tm_info.num_tc = num_tc;
1289	1441
..	..	@@ -1300,7 +1452,7 @@
1300	1452	hclge_tm_schd_info_init(hdev);
1301	1453	}
1302	1454
1303		-int hclge_tm_init_hw(struct hclge_dev *hdev)
	1455	+int hclge_tm_init_hw(struct hclge_dev *hdev, bool init)
1304	1456	{
1305	1457	int ret;
1306	1458
..	..	@@ -1312,7 +1464,7 @@
1312	1464	if (ret)
1313	1465	return ret;
1314	1466
1315		- ret = hclge_pause_setup_hw(hdev);
	1467	+ ret = hclge_pause_setup_hw(hdev, init);
1316	1468	if (ret)
1317	1469	return ret;
1318	1470
..	..	@@ -1321,15 +1473,32 @@
1321	1473
1322	1474	int hclge_tm_schd_init(struct hclge_dev *hdev)
1323	1475	{
1324		- int ret;
1325		-
1326	1476	/* fc_mode is HCLGE_FC_FULL on reset */
1327	1477	hdev->tm_info.fc_mode = HCLGE_FC_FULL;
1328	1478	hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
1329	1479
1330		- ret = hclge_tm_schd_info_init(hdev);
	1480	+ if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE &&
	1481	+ hdev->tm_info.num_pg != 1)
	1482	+ return -EINVAL;
	1483	+
	1484	+ hclge_tm_schd_info_init(hdev);
	1485	+
	1486	+ return hclge_tm_init_hw(hdev, true);
	1487	+}
	1488	+
	1489	+int hclge_tm_vport_map_update(struct hclge_dev *hdev)
	1490	+{
	1491	+ struct hclge_vport *vport = hdev->vport;
	1492	+ int ret;
	1493	+
	1494	+ hclge_tm_vport_tc_info_update(vport);
	1495	+
	1496	+ ret = hclge_vport_q_to_qs_map(hdev, vport);
1331	1497	if (ret)
1332	1498	return ret;
1333	1499
1334		- return hclge_tm_init_hw(hdev);
	1500	+ if (hdev->tm_info.num_tc == 1 && !hdev->tm_info.pfc_en)
	1501	+ return 0;
	1502	+
	1503	+ return hclge_tm_bp_setup(hdev);
1335	1504	}