forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-09 958e46acc8e900e8569dd467c1af9b8d2d019394 
 kernel/drivers/media/platform/rockchip/isp/csi.c
....@@ -12,6 +12,7 @@
1212 #include <media/v4l2-subdev.h>
1313 #include <media/videobuf2-dma-contig.h>
1414 #include "dev.h"
15
+#include "isp_external.h"
1516 #include "regs.h"
1617 
1718 static void get_remote_mipi_sensor(struct rkisp_device *dev,
....@@ -103,14 +104,15 @@
103104 }
104105 
105106 static int rkisp_csi_g_mbus_config(struct v4l2_subdev *sd,
106
-				  struct v4l2_mbus_config *config)
107
+				   unsigned int pad_id,
108
+				   struct v4l2_mbus_config *config)
107109 {
108110 	struct v4l2_subdev *remote_sd;
109111 
110112 	if (!sd)
111113 		return -ENODEV;
112114 	remote_sd = get_remote_subdev(sd);
113
-	return v4l2_subdev_call(remote_sd, video, g_mbus_config, config);
115
+	return v4l2_subdev_call(remote_sd, pad, get_mbus_config, pad_id, config);
114116 }
115117 
116118 static int rkisp_csi_get_set_fmt(struct v4l2_subdev *sd,
....@@ -159,10 +161,10 @@
159161 static const struct v4l2_subdev_pad_ops rkisp_csi_pad_ops = {
160162 	.set_fmt = rkisp_csi_get_set_fmt,
161163 	.get_fmt = rkisp_csi_get_set_fmt,
164
+	.get_mbus_config = rkisp_csi_g_mbus_config,
162165 };
163166 
164167 static const struct v4l2_subdev_video_ops rkisp_csi_video_ops = {
165
-	.g_mbus_config = rkisp_csi_g_mbus_config,
166168 	.s_stream = rkisp_csi_s_stream,
167169 };
168170 
....@@ -279,15 +281,10 @@
279281 
280282 		dev->hdr.op_mode = HDR_NORMAL;
281283 		dev->hdr.esp_mode = HDR_NORMAL_VC;
282
-		if (mipi_sensor) {
283
-			ret = v4l2_subdev_call(mipi_sensor,
284
-					       core, ioctl,
285
-					       RKMODULE_GET_HDR_CFG,
286
-					       &hdr_cfg);
287
-			if (!ret) {
288
-				dev->hdr.op_mode = hdr_cfg.hdr_mode;
289
-				dev->hdr.esp_mode = hdr_cfg.esp.mode;
290
-			}
284
+		memset(&hdr_cfg, 0, sizeof(hdr_cfg));
285
+		if (rkisp_csi_get_hdr_cfg(dev, &hdr_cfg) == 0) {
286
+			dev->hdr.op_mode = hdr_cfg.hdr_mode;
287
+			dev->hdr.esp_mode = hdr_cfg.esp.mode;
291288 		}
292289 
293290 		/* normal read back mode */
....@@ -316,9 +313,13 @@
316313 			rkisp_write(dev, CSI2RX_DATA_IDS_1, val, true);
317314 		} else {
318315 			rkisp_set_bits(dev, CSI2RX_DATA_IDS_1, mask, val, true);
319
-			for (i = 0; i < dev->hw_dev->dev_num; i++)
316
+			for (i = 0; i < dev->hw_dev->dev_num; i++) {
317
+				if (dev->hw_dev->isp[i] &&
318
+				    !dev->hw_dev->isp[i]->is_hw_link)
319
+					continue;
320320 				rkisp_set_bits(dev->hw_dev->isp[i],
321321 					CSI2RX_DATA_IDS_1, mask, val, false);
322
+			}
322323 		}
323324 		val = SW_CSI_ID4(csi->mipi_di[4]);
324325 		rkisp_write(dev, CSI2RX_DATA_IDS_2, val, true);
....@@ -338,9 +339,13 @@
338339 			Y_STAT_AFIFOX3_OVERFLOW;
339340 		rkisp_write(dev, CSI2RX_MASK_OVERFLOW, val, true);
340341 		val = RAW0_WR_FRAME | RAW1_WR_FRAME | RAW2_WR_FRAME |
341
-			MIPI_DROP_FRM | RAW_WR_SIZE_ERR | MIPI_LINECNT |
342
+			RAW_WR_SIZE_ERR | MIPI_LINECNT |
342343 			RAW_RD_SIZE_ERR | RAW0_Y_STATE |
343344 			RAW1_Y_STATE | RAW2_Y_STATE;
345
+		if (dev->isp_ver == ISP_V20)
346
+			val |= MIPI_DROP_FRM;
347
+		else
348
+			val |= ISP21_MIPI_DROP_FRM;
344349 		rkisp_write(dev, CSI2RX_MASK_STAT, val, true);
345350 
346351 		/* hdr merge */
....@@ -423,6 +428,133 @@
423428 	return 0;
424429 }
425430 
431
+int rkisp_expander_config(struct rkisp_device *dev,
432
+			  struct rkmodule_hdr_cfg *cfg, bool on)
433
+{
434
+	struct rkmodule_hdr_cfg hdr_cfg;
435
+	u32 i, val, num, d0, d1, drop_bit = 0;
436
+
437
+	if (dev->isp_ver != ISP_V32)
438
+		return 0;
439
+
440
+	if (!on) {
441
+		rkisp_write(dev, ISP32_EXPD_CTRL, 0, false);
442
+		return 0;
443
+	}
444
+
445
+	if (!cfg) {
446
+		if (rkisp_csi_get_hdr_cfg(dev, &hdr_cfg) != 0)
447
+			goto err;
448
+		cfg = &hdr_cfg;
449
+	}
450
+
451
+	if (cfg->hdr_mode != HDR_COMPR)
452
+		return 0;
453
+
454
+	/* compressed data max 12bit and src data max 20bit */
455
+	if (cfg->compr.bit > 20)
456
+		drop_bit = cfg->compr.bit - 20;
457
+	dev->hdr.compr_bit = cfg->compr.bit - drop_bit;
458
+
459
+	num = cfg->compr.segment;
460
+	for (i = 0; i < num; i++) {
461
+		val = cfg->compr.slope_k[i];
462
+		rkisp_write(dev, ISP32_EXPD_K0 + i * 4, val, false);
463
+	}
464
+
465
+	d0 = 0;
466
+	d1 = cfg->compr.data_compr[0];
467
+	val = ISP32_EXPD_DATA(d0, d1 > 0xfff ? 0xfff : d1);
468
+	rkisp_write(dev, ISP32_EXPD_X00_01, val, false);
469
+
470
+	d1 = cfg->compr.data_src_shitf[0];
471
+	val = ISP32_EXPD_DATA(d0, drop_bit ? d1 >> drop_bit : d1);
472
+	rkisp_write(dev, ISP32_EXPD_Y00_01, val, false);
473
+
474
+	for (i = 1; i < num - 1; i += 2) {
475
+		d0 = cfg->compr.data_compr[i];
476
+		d1 = cfg->compr.data_compr[i + 1];
477
+		val = ISP32_EXPD_DATA(d0 > 0xfff ? 0xfff : d0,
478
+				      d1 > 0xfff ? 0xfff : d1);
479
+		rkisp_write(dev, ISP32_EXPD_X00_01 + (i + 1) * 2, val, false);
480
+
481
+		d0 = cfg->compr.data_src_shitf[i];
482
+		d1 = cfg->compr.data_src_shitf[i + 1];
483
+		if (drop_bit) {
484
+			d0 = d0 >> drop_bit;
485
+			d1 = d1 >> drop_bit;
486
+		}
487
+		val = ISP32_EXPD_DATA(d0, d1);
488
+		rkisp_write(dev, ISP32_EXPD_Y00_01 + (i + 1) * 2, val, false);
489
+	}
490
+
491
+	/* the last valid point */
492
+	val = cfg->compr.data_compr[i];
493
+	val = val > 0xfff ? 0xfff : val;
494
+	d0 = ISP32_EXPD_DATA(val, val);
495
+
496
+	val = cfg->compr.data_src_shitf[i];
497
+	val = drop_bit ? val >> drop_bit : val;
498
+	d1 = ISP32_EXPD_DATA(val, val);
499
+
500
+	num = HDR_COMPR_SEGMENT_16;
501
+	for (; i < num - 1; i += 2) {
502
+		rkisp_write(dev, ISP32_EXPD_X00_01 + (i + 1) * 2, d0, false);
503
+		rkisp_write(dev, ISP32_EXPD_Y00_01 + (i + 1) * 2, d1, false);
504
+	}
505
+	rkisp_write(dev, ISP32_EXPD_Y16, val, false);
506
+
507
+	switch (cfg->compr.segment) {
508
+	case HDR_COMPR_SEGMENT_12:
509
+		num = 1;
510
+		break;
511
+	case HDR_COMPR_SEGMENT_16:
512
+		num = 2;
513
+		break;
514
+	default:
515
+		num = 0;
516
+	}
517
+	val = ISP32_EXPD_EN |
518
+	      ISP32_EXPD_MODE(num) |
519
+	      ISP32_EXPD_K_SHIFT(cfg->compr.k_shift);
520
+	rkisp_write(dev, ISP32_EXPD_CTRL, val, false);
521
+	return 0;
522
+err:
523
+	return -EINVAL;
524
+}
525
+
526
+int rkisp_csi_get_hdr_cfg(struct rkisp_device *dev, void *arg)
527
+{
528
+	struct rkmodule_hdr_cfg *cfg = arg;
529
+	struct v4l2_subdev *sd = NULL;
530
+	u32 type;
531
+
532
+	if (dev->isp_inp & INP_CSI) {
533
+		type = MEDIA_ENT_F_CAM_SENSOR;
534
+	} else if (dev->isp_inp & INP_CIF) {
535
+		type = MEDIA_ENT_F_PROC_VIDEO_COMPOSER;
536
+	} else {
537
+		switch (dev->isp_inp & 0x7) {
538
+		case INP_RAWRD2 | INP_RAWRD0:
539
+			cfg->hdr_mode = HDR_RDBK_FRAME2;
540
+			break;
541
+		case INP_RAWRD2 | INP_RAWRD1 | INP_RAWRD0:
542
+			cfg->hdr_mode = HDR_RDBK_FRAME3;
543
+			break;
544
+		default: //INP_RAWRD2
545
+			cfg->hdr_mode = HDR_RDBK_FRAME1;
546
+		}
547
+		return 0;
548
+	}
549
+	get_remote_mipi_sensor(dev, &sd, type);
550
+	if (!sd) {
551
+		v4l2_err(&dev->v4l2_dev, "%s don't find subdev\n", __func__);
552
+		return -EINVAL;
553
+	}
554
+
555
+	return v4l2_subdev_call(sd, core, ioctl, RKMODULE_GET_HDR_CFG, cfg);
556
+}
557
+
426558 int rkisp_csi_config_patch(struct rkisp_device *dev)
427559 {
428560 	int val = 0, ret = 0;
....@@ -434,63 +566,110 @@
434566 		dev->hw_dev->mipi_dev_id = dev->dev_id;
435567 		ret = csi_config(&dev->csi_dev);
436568 	} else {
569
+		struct rkmodule_hdr_cfg hdr_cfg;
570
+
571
+		memset(&hdr_cfg, 0, sizeof(hdr_cfg));
572
+		ret = rkisp_csi_get_hdr_cfg(dev, &hdr_cfg);
437573 		if (dev->isp_inp & INP_CIF) {
438
-			struct rkmodule_hdr_cfg hdr_cfg;
574
+			struct rkisp_vicap_mode mode;
575
+			int buf_cnt;
576
+
577
+			memset(&mode, 0, sizeof(mode));
578
+			mode.name = dev->name;
439579 
440580 			get_remote_mipi_sensor(dev, &mipi_sensor, MEDIA_ENT_F_PROC_VIDEO_COMPOSER);
581
+			if (!mipi_sensor)
582
+				return -EINVAL;
441583 			dev->hdr.op_mode = HDR_NORMAL;
442584 			dev->hdr.esp_mode = HDR_NORMAL_VC;
443
-			if (mipi_sensor) {
444
-				ret = v4l2_subdev_call(mipi_sensor,
445
-						       core, ioctl,
446
-						       RKMODULE_GET_HDR_CFG,
447
-						       &hdr_cfg);
448
-				if (!ret) {
449
-					dev->hdr.op_mode = hdr_cfg.hdr_mode;
450
-					dev->hdr.esp_mode = hdr_cfg.esp.mode;
451
-				}
585
+			if (!ret) {
586
+				dev->hdr.op_mode = hdr_cfg.hdr_mode;
587
+				dev->hdr.esp_mode = hdr_cfg.esp.mode;
588
+				rkisp_expander_config(dev, &hdr_cfg, true);
452589 			}
453590 
454
-			/* normal read back mode */
455
-			if (dev->hdr.op_mode == HDR_NORMAL)
591
+			/* normal read back mode default */
592
+			if (dev->hdr.op_mode == HDR_NORMAL || dev->hdr.op_mode == HDR_COMPR)
456593 				dev->hdr.op_mode = HDR_RDBK_FRAME1;
457
-		} else {
458
-			switch (dev->isp_inp & 0x7) {
459
-			case INP_RAWRD2 | INP_RAWRD0:
460
-				dev->hdr.op_mode = HDR_RDBK_FRAME2;
461
-				break;
462
-			case INP_RAWRD2 | INP_RAWRD1 | INP_RAWRD0:
463
-				dev->hdr.op_mode = HDR_RDBK_FRAME3;
464
-				break;
465
-			default: //INP_RAWRD2
466
-				dev->hdr.op_mode = HDR_RDBK_FRAME1;
594
+
595
+			if (dev->isp_inp == INP_CIF && dev->isp_ver > ISP_V21)
596
+				mode.rdbk_mode = dev->is_rdbk_auto ? RKISP_VICAP_RDBK_AUTO : RKISP_VICAP_ONLINE;
597
+			else
598
+				mode.rdbk_mode = RKISP_VICAP_RDBK_AIQ;
599
+			v4l2_subdev_call(mipi_sensor, core, ioctl, RKISP_VICAP_CMD_MODE, &mode);
600
+			dev->vicap_in = mode.input;
601
+			/* vicap direct to isp */
602
+			if (dev->isp_ver >= ISP_V30 && !mode.rdbk_mode) {
603
+				switch (dev->hdr.op_mode) {
604
+				case HDR_RDBK_FRAME3:
605
+					dev->hdr.op_mode = HDR_LINEX3_DDR;
606
+					break;
607
+				case HDR_RDBK_FRAME2:
608
+					dev->hdr.op_mode = HDR_LINEX2_DDR;
609
+					break;
610
+				default:
611
+					dev->hdr.op_mode = HDR_NORMAL;
612
+				}
613
+				if (dev->hdr.op_mode != HDR_NORMAL) {
614
+					buf_cnt = 1;
615
+					v4l2_subdev_call(mipi_sensor, core, ioctl,
616
+							 RKISP_VICAP_CMD_INIT_BUF, &buf_cnt);
617
+				}
618
+			} else if (mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
619
+				buf_cnt = RKISP_VICAP_BUF_CNT;
620
+				v4l2_subdev_call(mipi_sensor, core, ioctl,
621
+						 RKISP_VICAP_CMD_INIT_BUF, &buf_cnt);
467622 			}
623
+		} else {
624
+			dev->hdr.op_mode = hdr_cfg.hdr_mode;
468625 		}
469626 
470
-		if (dev->hdr.op_mode == HDR_RDBK_FRAME2)
471
-			val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX2;
472
-		else if (dev->hdr.op_mode == HDR_RDBK_FRAME3)
473
-			val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX3;
474
-
475627 		if (!dev->hw_dev->is_mi_update)
476
-			rkisp_write(dev, CSI2RX_CTRL0,
477
-				    SW_IBUF_OP_MODE(dev->hdr.op_mode), true);
628
+			rkisp_unite_write(dev, CSI2RX_CTRL0,
629
+					  SW_IBUF_OP_MODE(dev->hdr.op_mode),
630
+					  true, dev->hw_dev->is_unite);
478631 
632
+		/* hdr merge */
633
+		switch (dev->hdr.op_mode) {
634
+		case HDR_RDBK_FRAME2:
635
+		case HDR_FRAMEX2_DDR:
636
+		case HDR_LINEX2_DDR:
637
+		case HDR_LINEX2_NO_DDR:
638
+			val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX2;
639
+			break;
640
+		case HDR_RDBK_FRAME3:
641
+		case HDR_FRAMEX3_DDR:
642
+		case HDR_LINEX3_DDR:
643
+			val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX3;
644
+			break;
645
+		default:
646
+			val = 0;
647
+		}
479648 		if (is_feature_on) {
480649 			if ((ISP2X_MODULE_HDRMGE & ~iq_feature) && (val & SW_HDRMGE_EN)) {
481650 				v4l2_err(&dev->v4l2_dev, "hdrmge is not supported\n");
482651 				return -EINVAL;
483652 			}
484653 		}
485
-		rkisp_write(dev, ISP_HDRMGE_BASE, val, false);
654
+		rkisp_unite_write(dev, ISP_HDRMGE_BASE, val, false, dev->hw_dev->is_unite);
486655 
487
-		rkisp_set_bits(dev, CSI2RX_MASK_STAT, 0, RAW_RD_SIZE_ERR, true);
656
+		val = RAW_RD_SIZE_ERR;
657
+		if (!IS_HDR_RDBK(dev->hdr.op_mode))
658
+			val |= ISP21_MIPI_DROP_FRM;
659
+		rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT, 0, val, true, dev->hw_dev->is_unite);
488660 	}
489661 
490662 	if (IS_HDR_RDBK(dev->hdr.op_mode))
491
-		rkisp_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS, true);
663
+		rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS,
664
+				     true, dev->hw_dev->is_unite);
492665 
493
-	memset(dev->filt_state, 0, sizeof(dev->filt_state));
666
+	if (dev->isp_ver >= ISP_V30)
667
+		rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP3X_SW_ACK_FRM_PRO_DIS,
668
+				     true, dev->hw_dev->is_unite);
669
+	/* line counter from isp out, default from mp out */
670
+	if (dev->isp_ver == ISP_V32_L)
671
+		rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP32L_ISP2ENC_CNT_MUX,
672
+				     true, dev->hw_dev->is_unite);
494673 	dev->rdbk_cnt = -1;
495674 	dev->rdbk_cnt_x1 = -1;
496675 	dev->rdbk_cnt_x2 = -1;
....@@ -556,6 +735,8 @@
556735 		csi_dev->pads[CSI_SRC_CH2].flags = MEDIA_PAD_FL_SOURCE;
557736 		csi_dev->pads[CSI_SRC_CH3].flags = MEDIA_PAD_FL_SOURCE;
558737 		csi_dev->pads[CSI_SRC_CH4].flags = MEDIA_PAD_FL_SOURCE;
738
+	} else if (dev->isp_ver >= ISP_V30) {
739
+		return 0;
559740 	}
560741 
561742 	ret = media_entity_pads_init(&sd->entity, csi_dev->max_pad,