~hc/RK356X_SDK_RELEASE.git

..	..	@@ -13,8 +13,13 @@
13	13	* 1. add 2lane support.
14	14	* 2. add some debug info.
15	15	* 3. adjust gc8034_g_mbus_config function.
	16	+ * V0.0X01.0X07 support get channel info
	17	+ * V0.0X01.0X08
	18	+ * 1. default support 2lane full 30fps.
	19	+ * 2. default support rk otp spec.
	20	+ * V0.0X01.0X09 adjust supply sequence to suit spec
16	21	*/
17		-
	22	+//#define DEBUG
18	23	#include <linux/clk.h>
19	24	#include <linux/device.h>
20	25	#include <linux/delay.h>
..	..	@@ -39,8 +44,10 @@
39	44	#include <media/v4l2-subdev.h>
40	45	#include <linux/pinctrl/consumer.h>
41	46	#include <linux/slab.h>
	47	+#include <linux/of_graph.h>
	48	+#include "otp_eeprom.h"
42	49
43		-#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x06)
	50	+#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x09)
44	51
45	52	#ifndef V4L2_CID_DIGITAL_GAIN
46	53	#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
..	..	@@ -49,6 +56,7 @@
49	56	#define GC8034_LANES 4
50	57	#define GC8034_BITS_PER_SAMPLE 10
51	58	#define GC8034_MIPI_FREQ_336MHZ 336000000U
	59	+#define GC8034_MIPI_FREQ_634MHZ 634000000U
52	60
53	61	/* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
54	62	#define GC8034_PIXEL_RATE 288000000
..	..	@@ -92,15 +100,20 @@
92	100	#define GC8034_NAME "gc8034"
93	101	#define GC8034_MEDIA_BUS_FMT MEDIA_BUS_FMT_SRGGB10_1X10
94	102
	103	+/* use RK_OTP or old mode */
	104	+#define RK_OTP
	105	+/* choose 2lane support full 30fps or 15fps */
	106	+#define GC8034_2LANE_30FPS
	107	+
95	108	static const char * const gc8034_supply_names[] = {
96		- "avdd", /* Analog power */
97	109	"dovdd", /* Digital I/O power */
98	110	"dvdd", /* Digital core power */
	111	+ "avdd", /* Analog power */
99	112	};
100	113
101		-static const struct regval *gc8034_global_regs;
102	114	#define GC8034_NUM_SUPPLIES ARRAY_SIZE(gc8034_supply_names)
103	115
	116	+#ifndef RK_OTP
104	117	struct gc8034_dd {
105	118	u16 x;
106	119	u16 y;
..	..	@@ -145,6 +158,7 @@
145	158	{0xd0, "CK8401"},
146	159	{0x00, "Unknown"}
147	160	};
	161	+#endif
148	162
149	163	struct regval {
150	164	u8 addr;
..	..	@@ -158,7 +172,10 @@
158	172	u32 hts_def;
159	173	u32 vts_def;
160	174	u32 exp_def;
	175	+ u32 mipi_freq_idx;
	176	+ const struct regval *global_reg_list;
161	177	const struct regval *reg_list;
	178	+ u32 vc[PAD_MAX];
162	179	};
163	180
164	181	struct gc8034 {
..	..	@@ -192,7 +209,11 @@
192	209	const char *module_name;
193	210	const char *len_name;
194	211	u32 Dgain_ratio;
	212	+#ifdef RK_OTP
	213	+ struct otp_info *otp;
	214	+#else
195	215	struct gc8034_otp_info *otp;
	216	+#endif
196	217	struct rkmodule_inf module_inf;
197	218	struct rkmodule_awb_cfg awb_cfg;
198	219	};
..	..	@@ -244,6 +265,217 @@
244	265	* Xclk 24Mhz
245	266	*/
246	267	static const struct regval gc8034_global_regs_2lane[] = {
	268	+#ifdef GC8034_2LANE_30FPS
	269	+ /* SYS */
	270	+ {0xf2, 0x00},
	271	+ {0xf4, 0x90},
	272	+ {0xf5, 0x3d},
	273	+ {0xf6, 0x44},
	274	+ {0xf8, 0x63},
	275	+ {0xfa, 0x42},
	276	+ {0xf9, 0x00},
	277	+ {0xf7, 0x95},
	278	+ {0xfc, 0x00},
	279	+ {0xfc, 0x00},
	280	+ {0xfc, 0xea},
	281	+ {0xfe, 0x03},
	282	+ {0x03, 0x9a},
	283	+ {0xfc, 0xee},
	284	+ {0xfe, 0x00},
	285	+ {0x88, 0x03},
	286	+
	287	+ /Cisctl&Analog/
	288	+ {0xfe, 0x00},
	289	+ {0x03, 0x08},
	290	+ {0x04, 0xc6},
	291	+ {0x05, 0x02},
	292	+ {0x06, 0x16},
	293	+ {0x07, 0x00},
	294	+ {0x08, 0x10},
	295	+ {0x0a, 0x3a}, //row start
	296	+ {0x0b, 0x00},
	297	+ {0x0c, 0x04}, //col start
	298	+ {0x0d, 0x09},
	299	+ {0x0e, 0xa0}, //win_height 2464
	300	+ {0x0f, 0x0c},
	301	+ {0x10, 0xd4}, //win_width 3284
	302	+ {0x17, GC8034_MIRROR},
	303	+ {0x18, 0x02},
	304	+ {0x19, 0x17},
	305	+ {0x1e, 0x50},
	306	+ {0x1f, 0x80},
	307	+ {0x21, 0x4c},
	308	+ {0x25, 0x00},
	309	+ {0x28, 0x4a},
	310	+ {0x2d, 0x89},
	311	+ {0xca, 0x02},
	312	+ {0xcb, 0x00},
	313	+ {0xcc, 0x39},
	314	+ {0xce, 0xd0},
	315	+ {0xcf, 0x93},
	316	+ {0xd0, 0x1b},
	317	+ {0xd1, 0xaa},
	318	+ {0xd2, 0xcb},
	319	+ {0xd8, 0x40},
	320	+ {0xd9, 0xff},
	321	+ {0xda, 0x0e},
	322	+ {0xdb, 0xb0},
	323	+ {0xdc, 0x0e},
	324	+ {0xde, 0x08},
	325	+ {0xe4, 0xc6},
	326	+ {0xe5, 0x08},
	327	+ {0xe6, 0x10},
	328	+ {0xed, 0x2a},
	329	+ {0xfe, 0x02},
	330	+ {0x59, 0x02},
	331	+ {0x5a, 0x04},
	332	+ {0x5b, 0x08},
	333	+ {0x5c, 0x20},
	334	+ {0xfe, 0x00},
	335	+ {0x1a, 0x09},
	336	+ {0x1d, 0x13},
	337	+ {0xfe, 0x10},
	338	+ {0xfe, 0x00},
	339	+ {0xfe, 0x10},
	340	+ {0xfe, 0x00},
	341	+
	342	+ /* Gamma */
	343	+ {0xfe, 0x00},
	344	+ {0x20, 0x54},
	345	+ {0x33, 0x82},
	346	+ {0xfe, 0x01},
	347	+ {0xdf, 0x06},
	348	+ {0xe7, 0x18},
	349	+ {0xe8, 0x20},
	350	+ {0xe9, 0x16},
	351	+ {0xea, 0x17},
	352	+ {0xeb, 0x50},
	353	+ {0xec, 0x6c},
	354	+ {0xed, 0x9b},
	355	+ {0xee, 0xd8},
	356	+
	357	+ /ISP/
	358	+ {0xfe, 0x00},
	359	+ {0x80, 0x13},
	360	+ {0x84, 0x01},
	361	+ {0x89, 0x03},
	362	+ {0x8d, 0x03},
	363	+ {0x8f, 0x14},
	364	+ {0xad, 0x00},
	365	+ {0x66, 0x0c},
	366	+ {0xbc, 0x09},
	367	+ {0xc2, 0x7f},
	368	+ {0xc3, 0xff},
	369	+
	370	+ /Crop window/
	371	+ {0x90, 0x01},
	372	+ {0x92, FULL_STARTY},
	373	+ {0x94, FULL_STARTX},
	374	+ {0x95, 0x09},
	375	+ {0x96, 0x90},
	376	+ {0x97, 0x0c},
	377	+ {0x98, 0xc0},
	378	+
	379	+ /Gain/
	380	+ {0xb0, 0x90},
	381	+ {0xb1, 0x01},
	382	+ {0xb2, 0x00},
	383	+ {0xb6, 0x00},
	384	+
	385	+ /BLK/
	386	+ {0xfe, 0x00},
	387	+ {0x40, 0x22},
	388	+ {0x41, 0x20},
	389	+ {0x42, 0x02},
	390	+ {0x43, 0x08},
	391	+ {0x4e, 0x0f},
	392	+ {0x4f, 0xf0},
	393	+ {0x58, 0x80},
	394	+ {0x59, 0x80},
	395	+ {0x5a, 0x80},
	396	+ {0x5b, 0x80},
	397	+ {0x5c, 0x00},
	398	+ {0x5d, 0x00},
	399	+ {0x5e, 0x00},
	400	+ {0x5f, 0x00},
	401	+ {0x6b, 0x01},
	402	+ {0x6c, 0x00},
	403	+ {0x6d, 0x0c},
	404	+
	405	+ /WB offset/
	406	+ {0xfe, 0x01},
	407	+ {0xbf, 0x40},
	408	+
	409	+ /Dark Sun/
	410	+ {0xfe, 0x01},
	411	+ {0x68, 0x77},
	412	+
	413	+ /DPC/
	414	+ {0xfe, 0x01},
	415	+ {0x60, 0x00},
	416	+ {0x61, 0x10},
	417	+ {0x62, 0x60},
	418	+ {0x63, 0x30},
	419	+ {0x64, 0x00},
	420	+
	421	+ /* LSC */
	422	+ {0xfe, 0x01},
	423	+ {0xa8, 0x60},
	424	+ {0xa2, 0xd1},
	425	+ {0xc8, 0x57},
	426	+ {0xa1, 0xb8},
	427	+ {0xa3, 0x91},
	428	+ {0xc0, 0x50},
	429	+ {0xd0, 0x05},
	430	+ {0xd1, 0xb2},
	431	+ {0xd2, 0x1f},
	432	+ {0xd3, 0x00},
	433	+ {0xd4, 0x00},
	434	+ {0xd5, 0x00},
	435	+ {0xd6, 0x00},
	436	+ {0xd7, 0x00},
	437	+ {0xd8, 0x00},
	438	+ {0xd9, 0x00},
	439	+ {0xa4, 0x10},
	440	+ {0xa5, 0x20},
	441	+ {0xa6, 0x60},
	442	+ {0xa7, 0x80},
	443	+ {0xab, 0x18},
	444	+ {0xc7, 0xc0},
	445	+
	446	+ /ABB/
	447	+ {0xfe, 0x01},
	448	+ {0x20, 0x02},
	449	+ {0x21, 0x02},
	450	+ {0x23, 0x42},
	451	+
	452	+ /MIPI/
	453	+ {0xfe, 0x03},
	454	+ {0x01, 0x07},
	455	+ {0x02, 0x04},
	456	+ {0x04, 0x80},
	457	+ {0x11, 0x2b},
	458	+ {0x12, 0xf0}, //lwc 3264*5/4
	459	+ {0x13, 0x0f},
	460	+ {0x15, 0x10}, //LP
	461	+ {0x16, 0x29},
	462	+ {0x17, 0xff},
	463	+ {0x18, 0x01},
	464	+ {0x19, 0xaa},
	465	+ {0x1a, 0x02},
	466	+ {0x21, 0x0c},
	467	+ {0x22, 0x0e},
	468	+ {0x23, 0x45},
	469	+ {0x24, 0x01},
	470	+ {0x25, 0x1c},
	471	+ {0x26, 0x0b},
	472	+ {0x29, 0x0e},
	473	+ {0x2a, 0x1d},
	474	+ {0x2b, 0x0b},
	475	+ {0xfe, 0x00},
	476	+ //{0x3f, 0x91},
	477	+ {0x3f, 0x00},
	478	+#else
247	479	/SYS/
248	480	{0xf2, 0x00},
249	481	{0xf4, 0x80},
..	..	@@ -433,10 +665,11 @@
433	665	{0xfe, 0x00},
434	666	//{0x3f, 0x91},
435	667	{0x3f, 0x00},
436		-
	668	+#endif
437	669	{REG_NULL, 0x00},
438	670	};
439	671
	672	+#ifndef GC8034_2LANE_30FPS
440	673	/*
441	674	* Xclk 24Mhz
442	675	* max_framerate 30fps
..	..	@@ -507,6 +740,7 @@
507	740
508	741	{REG_NULL, 0x00},
509	742	};
	743	+#endif
510	744
511	745	/*
512	746	* Xclk 24Mhz
..	..	@@ -514,6 +748,72 @@
514	748	* mipi_datarate per lane 672Mbps
515	749	*/
516	750	static const struct regval gc8034_3264x2448_regs_2lane[] = {
	751	+#ifdef GC8034_2LANE_30FPS
	752	+ /* SYS */
	753	+ {0xf2, 0x00},
	754	+ {0xf4, 0x90},
	755	+ {0xf5, 0x3d},
	756	+ {0xf6, 0x44},
	757	+ {0xf8, 0x63},
	758	+ {0xfa, 0x42},
	759	+ {0xf9, 0x00},
	760	+ {0xf7, 0x95},
	761	+ {0xfc, 0x00},
	762	+ {0xfc, 0x00},
	763	+ {0xfc, 0xea},
	764	+ {0xfe, 0x03},
	765	+ {0x03, 0x9a},
	766	+ {0xfc, 0xee},
	767	+ {0xfe, 0x00},
	768	+ {0x3f, 0x00},
	769	+ {0xfe, 0x10},
	770	+ {0xfe, 0x00},
	771	+ {0xfe, 0x10},
	772	+ {0xfe, 0x00},
	773	+
	774	+ /* ISP */
	775	+ {0xfe, 0x00},
	776	+ {0x80, 0x13},
	777	+ {0xad, 0x00},
	778	+ {0x66, 0x0c},
	779	+ {0xbc, 0x06},
	780	+
	781	+ /* Crop window */
	782	+ {0x90, 0x01},
	783	+ {0x92, FULL_STARTY},
	784	+ {0x94, FULL_STARTX},
	785	+ {0x95, 0x09},
	786	+ {0x96, 0x90},
	787	+ {0x97, 0x0c},
	788	+ {0x98, 0xc0},
	789	+
	790	+ /* MIPI */
	791	+ {0xfe, 0x03},
	792	+ {0x01, 0x07},
	793	+ {0x02, 0x04},
	794	+ {0x04, 0x80},
	795	+ {0x11, 0x2b},
	796	+ {0x12, 0xf0}, //lwc 3264*5/4
	797	+ {0x13, 0x0f},
	798	+ {0x15, 0x10}, //LP
	799	+ {0x16, 0x29},
	800	+ {0x17, 0xff},
	801	+ {0x18, 0x01},
	802	+ {0x19, 0xaa},
	803	+ {0x1a, 0x02},
	804	+ {0x21, 0x0c},
	805	+ {0x22, 0x0c},
	806	+ {0x23, 0x56},
	807	+ {0x24, 0x00},
	808	+ {0x25, 0x1c},
	809	+ {0x26, 0x0b},
	810	+ {0x29, 0x0e},
	811	+ {0x2a, 0x1d},
	812	+ {0x2b, 0x0b},
	813	+ {0xfe, 0x00},
	814	+ //{0x3f, 0x91},
	815	+ {0x3f, 0x00},
	816	+#else
517	817	/SYS/
518	818	{0xf2, 0x00},
519	819	{0xf4, 0x80},
..	..	@@ -570,6 +870,7 @@
570	870	{0xfe, 0x00},
571	871	//{0x3f, 0x91},
572	872	{0x3f, 0x00},
	873	+#endif
573	874	{REG_NULL, 0x00},
574	875	};
575	876
..	..	@@ -843,6 +1144,23 @@
843	1144	};
844	1145
845	1146	static const struct gc8034_mode supported_modes_2lane[] = {
	1147	+#ifdef GC8034_2LANE_30FPS
	1148	+ {
	1149	+ .width = 3264,
	1150	+ .height = 2448,
	1151	+ .max_fps = {
	1152	+ .numerator = 10000,
	1153	+ .denominator = 300000,
	1154	+ },
	1155	+ .exp_def = 0x0900,
	1156	+ .hts_def = 0x0858 * 2,
	1157	+ .vts_def = 0x09c0,
	1158	+ .mipi_freq_idx = 1,
	1159	+ .global_reg_list = gc8034_global_regs_2lane,
	1160	+ .reg_list = gc8034_3264x2448_regs_2lane,
	1161	+ .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
	1162	+ },
	1163	+#else
846	1164	{
847	1165	.width = 3264,
848	1166	.height = 2448,
..	..	@@ -853,7 +1171,10 @@
853	1171	.exp_def = 0x09a0,
854	1172	.hts_def = 0x0858 * 2,
855	1173	.vts_def = 0x09c4,
	1174	+ .mipi_freq_idx = 0,
	1175	+ .global_reg_list = gc8034_global_regs_2lane,
856	1176	.reg_list = gc8034_3264x2448_regs_2lane,
	1177	+ .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
857	1178	},
858	1179	{
859	1180	.width = 1632,
..	..	@@ -865,8 +1186,12 @@
865	1186	.exp_def = 0x09a0,
866	1187	.hts_def = 0x0858 * 2,
867	1188	.vts_def = 0x09c4,
	1189	+ .mipi_freq_idx = 0,
	1190	+ .global_reg_list = gc8034_global_regs_2lane,
868	1191	.reg_list = gc8034_1632x1224_regs_2lane,
	1192	+ .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
869	1193	},
	1194	+#endif
870	1195	};
871	1196
872	1197	static const struct gc8034_mode supported_modes_4lane[] = {
..	..	@@ -880,7 +1205,10 @@
880	1205	.exp_def = 0x08c6,
881	1206	.hts_def = 0x10b0,
882	1207	.vts_def = 0x09c0,
	1208	+ .mipi_freq_idx = 0,
	1209	+ .global_reg_list = gc8034_global_regs_4lane,
883	1210	.reg_list = gc8034_3264x2448_regs_4lane,
	1211	+ .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
884	1212	},
885	1213	};
886	1214
..	..	@@ -888,6 +1216,7 @@
888	1216
889	1217	static const s64 link_freq_menu_items[] = {
890	1218	GC8034_MIPI_FREQ_336MHZ,
	1219	+ GC8034_MIPI_FREQ_634MHZ
891	1220	};
892	1221
893	1222	/* Write registers up to 4 at a time */
..	..	@@ -1017,8 +1346,8 @@
1017	1346	__v4l2_ctrl_modify_range(gc8034->vblank, vblank_def,
1018	1347	GC8034_VTS_MAX - mode->height,
1019	1348	1, vblank_def);
1020		- __v4l2_ctrl_s_ctrl(gc8034->link_freq,
1021		- link_freq_menu_items[0]);
	1349	+ __v4l2_ctrl_s_ctrl(gc8034->vblank, vblank_def);
	1350	+ __v4l2_ctrl_s_ctrl(gc8034->link_freq, mode->mipi_freq_idx);
1022	1351	}
1023	1352
1024	1353	mutex_unlock(&gc8034->mutex);
..	..	@@ -1089,13 +1418,91 @@
1089	1418	struct gc8034 *gc8034 = to_gc8034(sd);
1090	1419	const struct gc8034_mode *mode = gc8034->cur_mode;
1091	1420
1092		- mutex_lock(&gc8034->mutex);
1093	1421	fi->interval = mode->max_fps;
1094		- mutex_unlock(&gc8034->mutex);
1095	1422
1096	1423	return 0;
1097	1424	}
1098	1425
	1426	+#ifdef RK_OTP
	1427	+static void gc8034_get_otp(struct otp_info *otp,
	1428	+ struct rkmodule_inf *inf)
	1429	+{
	1430	+ u32 i, j;
	1431	+ u32 w, h;
	1432	+
	1433	+ /* awb */
	1434	+ if (otp->awb_data.flag) {
	1435	+ inf->awb.flag = 1;
	1436	+ inf->awb.r_value = otp->awb_data.r_ratio;
	1437	+ inf->awb.b_value = otp->awb_data.b_ratio;
	1438	+ inf->awb.gr_value = otp->awb_data.g_ratio;
	1439	+ inf->awb.gb_value = 0x0;
	1440	+
	1441	+ inf->awb.golden_r_value = otp->awb_data.r_golden;
	1442	+ inf->awb.golden_b_value = otp->awb_data.b_golden;
	1443	+ inf->awb.golden_gr_value = otp->awb_data.g_golden;
	1444	+ inf->awb.golden_gb_value = 0x0;
	1445	+ }
	1446	+
	1447	+ /* lsc */
	1448	+ if (otp->lsc_data.flag) {
	1449	+ inf->lsc.flag = 1;
	1450	+ inf->lsc.width = otp->basic_data.size.width;
	1451	+ inf->lsc.height = otp->basic_data.size.height;
	1452	+ inf->lsc.table_size = otp->lsc_data.table_size;
	1453	+
	1454	+ for (i = 0; i < 289; i++) {
	1455	+ inf->lsc.lsc_r[i] = (otp->lsc_data.data[i * 2] << 8) \|
	1456	+ otp->lsc_data.data[i * 2 + 1];
	1457	+ inf->lsc.lsc_gr[i] = (otp->lsc_data.data[i * 2 + 578] << 8) \|
	1458	+ otp->lsc_data.data[i * 2 + 579];
	1459	+ inf->lsc.lsc_gb[i] = (otp->lsc_data.data[i * 2 + 1156] << 8) \|
	1460	+ otp->lsc_data.data[i * 2 + 1157];
	1461	+ inf->lsc.lsc_b[i] = (otp->lsc_data.data[i * 2 + 1734] << 8) \|
	1462	+ otp->lsc_data.data[i * 2 + 1735];
	1463	+ }
	1464	+ }
	1465	+
	1466	+ /* pdaf */
	1467	+ if (otp->pdaf_data.flag) {
	1468	+ inf->pdaf.flag = 1;
	1469	+ inf->pdaf.gainmap_width = otp->pdaf_data.gainmap_width;
	1470	+ inf->pdaf.gainmap_height = otp->pdaf_data.gainmap_height;
	1471	+ inf->pdaf.dcc_mode = otp->pdaf_data.dcc_mode;
	1472	+ inf->pdaf.dcc_dir = otp->pdaf_data.dcc_dir;
	1473	+ inf->pdaf.dccmap_width = otp->pdaf_data.dccmap_width;
	1474	+ inf->pdaf.dccmap_height = otp->pdaf_data.dccmap_height;
	1475	+ w = otp->pdaf_data.gainmap_width;
	1476	+ h = otp->pdaf_data.gainmap_height;
	1477	+ for (i = 0; i < h; i++) {
	1478	+ for (j = 0; j < w; j++) {
	1479	+ inf->pdaf.gainmap[i * w + j] =
	1480	+ (otp->pdaf_data.gainmap[(i * w + j) * 2] << 8) \|
	1481	+ otp->pdaf_data.gainmap[(i * w + j) * 2 + 1];
	1482	+ }
	1483	+ }
	1484	+ w = otp->pdaf_data.dccmap_width;
	1485	+ h = otp->pdaf_data.dccmap_height;
	1486	+ for (i = 0; i < h; i++) {
	1487	+ for (j = 0; j < w; j++) {
	1488	+ inf->pdaf.dccmap[i * w + j] =
	1489	+ (otp->pdaf_data.dccmap[(i * w + j) * 2] << 8) \|
	1490	+ otp->pdaf_data.dccmap[(i * w + j) * 2 + 1];
	1491	+ }
	1492	+ }
	1493	+ }
	1494	+
	1495	+ /* af */
	1496	+ if (otp->af_data.flag) {
	1497	+ inf->af.flag = 1;
	1498	+ inf->af.dir_cnt = 1;
	1499	+ inf->af.af_otp[0].vcm_start = otp->af_data.af_inf;
	1500	+ inf->af.af_otp[0].vcm_end = otp->af_data.af_macro;
	1501	+ inf->af.af_otp[0].vcm_dir = 0;
	1502	+ }
	1503	+
	1504	+}
	1505	+#else
1099	1506	#define DD_WIDTH 3284
1100	1507	#define DD_HEIGHT 2464
1101	1508
..	..	@@ -1605,11 +2012,16 @@
1605	2012	inf->af.af_otp[0].vcm_dir = otp->vcm_dir;
1606	2013	}
1607	2014	}
	2015	+#endif
1608	2016
1609	2017	static void gc8034_get_module_inf(struct gc8034 *gc8034,
1610	2018	struct rkmodule_inf *inf)
1611	2019	{
	2020	+#ifdef RK_OTP
	2021	+ struct otp_info *otp = gc8034->otp;
	2022	+#else
1612	2023	struct gc8034_otp_info *otp = gc8034->otp;
	2024	+#endif
1613	2025
1614	2026	strlcpy(inf->base.sensor,
1615	2027	GC8034_NAME,
..	..	@@ -1632,11 +2044,23 @@
1632	2044	mutex_unlock(&gc8034->mutex);
1633	2045	}
1634	2046
	2047	+static int gc8034_get_channel_info(struct gc8034 gc8034, struct rkmodule_channel_info ch_info)
	2048	+{
	2049	+ if (ch_info->index < PAD0 \|\| ch_info->index >= PAD_MAX)
	2050	+ return -EINVAL;
	2051	+ ch_info->vc = gc8034->cur_mode->vc[ch_info->index];
	2052	+ ch_info->width = gc8034->cur_mode->width;
	2053	+ ch_info->height = gc8034->cur_mode->height;
	2054	+ ch_info->bus_fmt = GC8034_MEDIA_BUS_FMT;
	2055	+ return 0;
	2056	+}
	2057	+
1635	2058	static long gc8034_ioctl(struct v4l2_subdev sd, unsigned int cmd, void arg)
1636	2059	{
1637	2060	struct gc8034 *gc8034 = to_gc8034(sd);
1638	2061	long ret = 0;
1639	2062	u32 stream = 0;
	2063	+ struct rkmodule_channel_info *ch_info;
1640	2064
1641	2065	switch (cmd) {
1642	2066	case RKMODULE_GET_MODULE_INFO:
..	..	@@ -1671,6 +2095,10 @@
1671	2095	GC8034_MODE_SW_STANDBY);
1672	2096	}
1673	2097	break;
	2098	+ case RKMODULE_GET_CHANNEL_INFO:
	2099	+ ch_info = (struct rkmodule_channel_info *)arg;
	2100	+ ret = gc8034_get_channel_info(gc8034, ch_info);
	2101	+ break;
1674	2102	default:
1675	2103	ret = -ENOTTY;
1676	2104	break;
..	..	@@ -1688,6 +2116,7 @@
1688	2116	struct rkmodule_awb_cfg *cfg;
1689	2117	long ret = 0;
1690	2118	u32 stream = 0;
	2119	+ struct rkmodule_channel_info *ch_info;
1691	2120
1692	2121	switch (cmd) {
1693	2122	case RKMODULE_GET_MODULE_INFO:
..	..	@@ -1698,8 +2127,11 @@
1698	2127	}
1699	2128
1700	2129	ret = gc8034_ioctl(sd, cmd, inf);
1701		- if (!ret)
	2130	+ if (!ret) {
1702	2131	ret = copy_to_user(up, inf, sizeof(*inf));
	2132	+ if (ret)
	2133	+ ret = -EFAULT;
	2134	+ }
1703	2135	kfree(inf);
1704	2136	break;
1705	2137	case RKMODULE_AWB_CFG:
..	..	@@ -1712,12 +2144,31 @@
1712	2144	ret = copy_from_user(cfg, up, sizeof(*cfg));
1713	2145	if (!ret)
1714	2146	ret = gc8034_ioctl(sd, cmd, cfg);
	2147	+ else
	2148	+ ret = -EFAULT;
1715	2149	kfree(cfg);
1716	2150	break;
1717	2151	case RKMODULE_SET_QUICK_STREAM:
1718	2152	ret = copy_from_user(&stream, up, sizeof(u32));
1719	2153	if (!ret)
1720	2154	ret = gc8034_ioctl(sd, cmd, &stream);
	2155	+ else
	2156	+ ret = -EFAULT;
	2157	+ break;
	2158	+ case RKMODULE_GET_CHANNEL_INFO:
	2159	+ ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
	2160	+ if (!ch_info) {
	2161	+ ret = -ENOMEM;
	2162	+ return ret;
	2163	+ }
	2164	+
	2165	+ ret = gc8034_ioctl(sd, cmd, ch_info);
	2166	+ if (!ret) {
	2167	+ ret = copy_to_user(up, ch_info, sizeof(*ch_info));
	2168	+ if (ret)
	2169	+ ret = -EFAULT;
	2170	+ }
	2171	+ kfree(ch_info);
1721	2172	break;
1722	2173	default:
1723	2174	ret = -ENOTTY;
..	..	@@ -1728,6 +2179,7 @@
1728	2179	}
1729	2180	#endif
1730	2181
	2182	+#ifndef RK_OTP
1731	2183	/--------------------------------------------------------------------------/
1732	2184	static int gc8034_apply_otp(struct gc8034 *gc8034)
1733	2185	{
..	..	@@ -1908,11 +2360,12 @@
1908	2360	}
1909	2361	return 0;
1910	2362	}
	2363	+#endif
1911	2364
1912	2365	static int __gc8034_start_stream(struct gc8034 *gc8034)
1913	2366	{
1914	2367	int ret;
1915		-
	2368	+#ifndef RK_OTP
1916	2369	if (gc8034->otp) {
1917	2370	ret = gc8034_otp_enable(gc8034);
1918	2371	gc8034_check_prsel(gc8034);
..	..	@@ -1922,6 +2375,7 @@
1922	2375	if (ret)
1923	2376	return ret;
1924	2377	}
	2378	+#endif
1925	2379	ret = gc8034_write_array(gc8034->client, gc8034->cur_mode->reg_list);
1926	2380	if (ret)
1927	2381	return ret;
..	..	@@ -2006,6 +2460,7 @@
2006	2460	{
2007	2461	struct gc8034 *gc8034 = to_gc8034(sd);
2008	2462	struct i2c_client *client = gc8034->client;
	2463	+ const struct gc8034_mode *mode = gc8034->cur_mode;
2009	2464	int ret = 0;
2010	2465
2011	2466	dev_info(&client->dev, "%s(%d) on(%d)\n", __func__, __LINE__, on);
..	..	@@ -2022,7 +2477,7 @@
2022	2477	goto unlock_and_return;
2023	2478	}
2024	2479
2025		- ret = gc8034_write_array(gc8034->client, gc8034_global_regs);
	2480	+ ret = gc8034_write_array(gc8034->client, mode->global_reg_list);
2026	2481	if (ret) {
2027	2482	v4l2_err(sd, "could not set init registers\n");
2028	2483	pm_runtime_put_noidle(&client->dev);
..	..	@@ -2047,6 +2502,31 @@
2047	2502	return DIV_ROUND_UP(cycles, GC8034_XVCLK_FREQ / 1000 / 1000);
2048	2503	}
2049	2504
	2505	+static int gc8034_enable_regulators(struct gc8034 *gc8034,
	2506	+ struct regulator_bulk_data *consumers)
	2507	+{
	2508	+ int i, j;
	2509	+ int ret = 0;
	2510	+ struct device *dev = &gc8034->client->dev;
	2511	+ int num_consumers = GC8034_NUM_SUPPLIES;
	2512	+
	2513	+ for (i = 0; i < num_consumers; i++) {
	2514	+
	2515	+ ret = regulator_enable(consumers[i].consumer);
	2516	+ if (ret < 0) {
	2517	+ dev_err(dev, "Failed to enable regulator: %s\n",
	2518	+ consumers[i].supply);
	2519	+ goto err;
	2520	+ }
	2521	+ }
	2522	+ return 0;
	2523	+err:
	2524	+ for (j = 0; j < i; j++)
	2525	+ regulator_disable(consumers[j].consumer);
	2526	+
	2527	+ return ret;
	2528	+}
	2529	+
2050	2530	static int __gc8034_power_on(struct gc8034 *gc8034)
2051	2531	{
2052	2532	int ret;
..	..	@@ -2069,27 +2549,30 @@
2069	2549	dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
2070	2550	if (clk_get_rate(gc8034->xvclk) != GC8034_XVCLK_FREQ)
2071	2551	dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
2072		- ret = clk_prepare_enable(gc8034->xvclk);
2073		- if (ret < 0) {
2074		- dev_err(dev, "Failed to enable xvclk\n");
2075		- return ret;
2076		- }
	2552	+
2077	2553	if (!IS_ERR(gc8034->reset_gpio))
2078	2554	gpiod_set_value_cansleep(gc8034->reset_gpio, 1);
2079	2555
2080		- ret = regulator_bulk_enable(GC8034_NUM_SUPPLIES, gc8034->supplies);
	2556	+ ret = gc8034_enable_regulators(gc8034, gc8034->supplies);
2081	2557	if (ret < 0) {
2082	2558	dev_err(dev, "Failed to enable regulators\n");
2083	2559	goto disable_clk;
2084	2560	}
2085	2561
2086		- usleep_range(1000, 1100);
2087		- if (!IS_ERR(gc8034->reset_gpio))
2088		- gpiod_set_value_cansleep(gc8034->reset_gpio, 0);
	2562	+ usleep_range(100, 200);
	2563	+ ret = clk_prepare_enable(gc8034->xvclk);
	2564	+ if (ret < 0) {
	2565	+ dev_err(dev, "Failed to enable xvclk\n");
	2566	+ return ret;
	2567	+ }
2089	2568
2090		- usleep_range(500, 1000);
	2569	+ usleep_range(1000, 1100);
2091	2570	if (!IS_ERR(gc8034->pwdn_gpio))
2092	2571	gpiod_set_value_cansleep(gc8034->pwdn_gpio, 0);
	2572	+
	2573	+ usleep_range(500, 1000);
	2574	+ if (!IS_ERR(gc8034->reset_gpio))
	2575	+ gpiod_set_value_cansleep(gc8034->reset_gpio, 0);
2093	2576
2094	2577	/* 8192 cycles prior to first SCCB transaction */
2095	2578	delay_us = gc8034_cal_delay(8192);
..	..	@@ -2109,9 +2592,11 @@
2109	2592
2110	2593	if (!IS_ERR(gc8034->pwdn_gpio))
2111	2594	gpiod_set_value_cansleep(gc8034->pwdn_gpio, 1);
2112		- clk_disable_unprepare(gc8034->xvclk);
	2595	+
2113	2596	if (!IS_ERR(gc8034->reset_gpio))
2114	2597	gpiod_set_value_cansleep(gc8034->reset_gpio, 1);
	2598	+
	2599	+ clk_disable_unprepare(gc8034->xvclk);
2115	2600	if (!IS_ERR_OR_NULL(gc8034->pins_sleep)) {
2116	2601	ret = pinctrl_select_state(gc8034->pinctrl,
2117	2602	gc8034->pins_sleep);
..	..	@@ -2124,7 +2609,7 @@
2124	2609	regulator_bulk_disable(GC8034_NUM_SUPPLIES, gc8034->supplies);
2125	2610	}
2126	2611
2127		-static int gc8034_runtime_resume(struct device *dev)
	2612	+static int __maybe_unused gc8034_runtime_resume(struct device *dev)
2128	2613	{
2129	2614	struct i2c_client *client = to_i2c_client(dev);
2130	2615	struct v4l2_subdev *sd = i2c_get_clientdata(client);
..	..	@@ -2133,7 +2618,7 @@
2133	2618	return __gc8034_power_on(gc8034);
2134	2619	}
2135	2620
2136		-static int gc8034_runtime_suspend(struct device *dev)
	2621	+static int __maybe_unused gc8034_runtime_suspend(struct device *dev)
2137	2622	{
2138	2623	struct i2c_client *client = to_i2c_client(dev);
2139	2624	struct v4l2_subdev *sd = i2c_get_clientdata(client);
..	..	@@ -2175,16 +2660,14 @@
2175	2660	if (fie->index >= gc8034->cfg_num)
2176	2661	return -EINVAL;
2177	2662
2178		- if (fie->code != GC8034_MEDIA_BUS_FMT)
2179		- return -EINVAL;
2180		-
	2663	+ fie->code = GC8034_MEDIA_BUS_FMT;
2181	2664	fie->width = supported_modes[fie->index].width;
2182	2665	fie->height = supported_modes[fie->index].height;
2183	2666	fie->interval = supported_modes[fie->index].max_fps;
2184	2667	return 0;
2185	2668	}
2186	2669
2187		-static int gc8034_g_mbus_config(struct v4l2_subdev *sd,
	2670	+static int gc8034_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
2188	2671	struct v4l2_mbus_config *config)
2189	2672	{
2190	2673	struct gc8034 *sensor = to_gc8034(sd);
..	..	@@ -2193,12 +2676,12 @@
2193	2676	dev_info(dev, "%s(%d) enter!\n", __func__, __LINE__);
2194	2677
2195	2678	if (2 == sensor->lane_num) {
2196		- config->type = V4L2_MBUS_CSI2;
	2679	+ config->type = V4L2_MBUS_CSI2_DPHY;
2197	2680	config->flags = V4L2_MBUS_CSI2_2_LANE \|
2198	2681	V4L2_MBUS_CSI2_CHANNEL_0 \|
2199	2682	V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
2200	2683	} else if (4 == sensor->lane_num) {
2201		- config->type = V4L2_MBUS_CSI2;
	2684	+ config->type = V4L2_MBUS_CSI2_DPHY;
2202	2685	config->flags = V4L2_MBUS_CSI2_4_LANE \|
2203	2686	V4L2_MBUS_CSI2_CHANNEL_0 \|
2204	2687	V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
..	..	@@ -2231,7 +2714,6 @@
2231	2714	static const struct v4l2_subdev_video_ops gc8034_video_ops = {
2232	2715	.s_stream = gc8034_s_stream,
2233	2716	.g_frame_interval = gc8034_g_frame_interval,
2234		- .g_mbus_config = gc8034_g_mbus_config,
2235	2717	};
2236	2718
2237	2719	static const struct v4l2_subdev_pad_ops gc8034_pad_ops = {
..	..	@@ -2240,6 +2722,7 @@
2240	2722	.enum_frame_interval = gc8034_enum_frame_interval,
2241	2723	.get_fmt = gc8034_get_fmt,
2242	2724	.set_fmt = gc8034_set_fmt,
	2725	+ .get_mbus_config = gc8034_g_mbus_config,
2243	2726	};
2244	2727
2245	2728	static const struct v4l2_subdev_ops gc8034_subdev_ops = {
..	..	@@ -2388,15 +2871,15 @@
2388	2871	switch (ctrl->id) {
2389	2872	case V4L2_CID_EXPOSURE:
2390	2873	/* 4 least significant bits of expsoure are fractional part */
2391		- dev_info(&client->dev, "set exposure value 0x%x\n", ctrl->val);
	2874	+ dev_dbg(&client->dev, "set exposure value 0x%x\n", ctrl->val);
2392	2875	ret = gc8034_set_exposure_reg(gc8034, ctrl->val);
2393	2876	break;
2394	2877	case V4L2_CID_ANALOGUE_GAIN:
2395		- dev_info(&client->dev, "set analog gain value 0x%x\n", ctrl->val);
	2878	+ dev_dbg(&client->dev, "set analog gain value 0x%x\n", ctrl->val);
2396	2879	ret = gc8034_set_gain_reg(gc8034, ctrl->val);
2397	2880	break;
2398	2881	case V4L2_CID_VBLANK:
2399		- dev_info(&client->dev, "set vb value 0x%x\n", ctrl->val);
	2882	+ dev_dbg(&client->dev, "set vb value 0x%x\n", ctrl->val);
2400	2883	/* VB = VTS - 2448 -36, according android8.1 driver */
2401	2884	temp = ctrl->val + gc8034->cur_mode->height - 2448 - 36;
2402	2885	ret = gc8034_write_reg(gc8034->client,
..	..	@@ -2440,8 +2923,10 @@
2440	2923	handler->lock = &gc8034->mutex;
2441	2924
2442	2925	gc8034->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
2443		- V4L2_CID_LINK_FREQ, 0, 0,
	2926	+ V4L2_CID_LINK_FREQ,
	2927	+ ARRAY_SIZE(link_freq_menu_items) - 1, 0,
2444	2928	link_freq_menu_items);
	2929	+ v4l2_ctrl_s_ctrl(gc8034->link_freq, mode->mipi_freq_idx);
2445	2930
2446	2931	v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
2447	2932	0, gc8034->pixel_rate, 1, gc8034->pixel_rate);
..	..	@@ -2542,7 +3027,6 @@
2542	3027	gc8034->cur_mode = &supported_modes_4lane[0];
2543	3028	supported_modes = supported_modes_4lane;
2544	3029	gc8034->cfg_num = ARRAY_SIZE(supported_modes_4lane);
2545		- gc8034_global_regs = gc8034_global_regs_4lane;
2546	3030	/* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
2547	3031	fps = DIV_ROUND_CLOSEST(gc8034->cur_mode->max_fps.denominator,
2548	3032	gc8034->cur_mode->max_fps.numerator);
..	..	@@ -2555,7 +3039,6 @@
2555	3039	gc8034->cur_mode = &supported_modes_2lane[0];
2556	3040	supported_modes = supported_modes_2lane;
2557	3041	gc8034->cfg_num = ARRAY_SIZE(supported_modes_2lane);
2558		- gc8034_global_regs = gc8034_global_regs_2lane;
2559	3042	/pixel rate = link frequency 2 * lanes / BITS_PER_SAMPLE */
2560	3043	fps = DIV_ROUND_CLOSEST(gc8034->cur_mode->max_fps.denominator,
2561	3044	gc8034->cur_mode->max_fps.numerator);
..	..	@@ -2580,6 +3063,10 @@
2580	3063	struct v4l2_subdev *sd;
2581	3064	char facing[2];
2582	3065	int ret;
	3066	+ struct device_node *eeprom_ctrl_node;
	3067	+ struct i2c_client *eeprom_ctrl_client;
	3068	+ struct v4l2_subdev *eeprom_ctrl;
	3069	+ struct otp_info *otp_ptr;
2583	3070
2584	3071	dev_info(dev, "driver version: %02x.%02x.%02x",
2585	3072	DRIVER_VERSION >> 16,
..	..	@@ -2661,10 +3148,40 @@
2661	3148	ret = gc8034_check_sensor_id(gc8034, client);
2662	3149	if (ret)
2663	3150	goto err_power_off;
2664		-
	3151	+#ifdef RK_OTP
	3152	+ eeprom_ctrl_node = of_parse_phandle(node, "eeprom-ctrl", 0);
	3153	+ if (eeprom_ctrl_node) {
	3154	+ eeprom_ctrl_client =
	3155	+ of_find_i2c_device_by_node(eeprom_ctrl_node);
	3156	+ of_node_put(eeprom_ctrl_node);
	3157	+ if (IS_ERR_OR_NULL(eeprom_ctrl_client)) {
	3158	+ dev_err(dev, "can not get node\n");
	3159	+ goto continue_probe;
	3160	+ }
	3161	+ eeprom_ctrl = i2c_get_clientdata(eeprom_ctrl_client);
	3162	+ if (IS_ERR_OR_NULL(eeprom_ctrl)) {
	3163	+ dev_err(dev, "can not get eeprom i2c client\n");
	3164	+ } else {
	3165	+ otp_ptr = devm_kzalloc(dev, sizeof(*otp_ptr), GFP_KERNEL);
	3166	+ if (!otp_ptr)
	3167	+ return -ENOMEM;
	3168	+ ret = v4l2_subdev_call(eeprom_ctrl,
	3169	+ core, ioctl, 0, otp_ptr);
	3170	+ if (!ret) {
	3171	+ gc8034->otp = otp_ptr;
	3172	+ } else {
	3173	+ gc8034->otp = NULL;
	3174	+ devm_kfree(dev, otp_ptr);
	3175	+ dev_warn(dev, "can not get otp info, skip!\n");
	3176	+ }
	3177	+ }
	3178	+ }
	3179	+continue_probe:
	3180	+#else
2665	3181	gc8034_otp_enable(gc8034);
2666	3182	gc8034_otp_read(gc8034);
2667	3183	gc8034_otp_disable(gc8034);
	3184	+#endif
2668	3185
2669	3186	#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2670	3187	sd->internal_ops = &gc8034_internal_ops;