| .. | .. |
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| 4 | 4 | */ |
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| 5 | 5 | #include <linux/cpu.h> |
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| 6 | 6 | |
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| 7 | | -#include <asm/pat.h> |
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| 7 | +#include <asm/memtype.h> |
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| 8 | +#include <asm/apic.h> |
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| 8 | 9 | #include <asm/processor.h> |
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| 9 | 10 | |
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| 10 | | -#include <asm/apic.h> |
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| 11 | +#include "cpu.h" |
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| 11 | 12 | |
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| 12 | 13 | struct cpuid_bit { |
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| 13 | 14 | u16 feature; |
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| .. | .. |
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| 17 | 18 | u32 sub_leaf; |
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| 18 | 19 | }; |
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| 19 | 20 | |
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| 20 | | -/* Please keep the leaf sorted by cpuid_bit.level for faster search. */ |
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| 21 | +/* |
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| 22 | + * Please keep the leaf sorted by cpuid_bit.level for faster search. |
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| 23 | + * X86_FEATURE_MBA is supported by both Intel and AMD. But the CPUID |
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| 24 | + * levels are different and there is a separate entry for each. |
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| 25 | + */ |
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| 21 | 26 | static const struct cpuid_bit cpuid_bits[] = { |
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| 22 | 27 | { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, |
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| 23 | 28 | { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, |
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| 29 | + { X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 }, |
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| 24 | 30 | { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 }, |
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| 25 | 31 | { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 }, |
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| 26 | 32 | { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 }, |
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| .. | .. |
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| 30 | 36 | { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 }, |
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| 31 | 37 | { X86_FEATURE_CDP_L2, CPUID_ECX, 2, 0x00000010, 2 }, |
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| 32 | 38 | { X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 }, |
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| 39 | + { X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 }, |
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| 33 | 40 | { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, |
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| 34 | 41 | { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, |
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| 35 | 42 | { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, |
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| 43 | + { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, |
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| 36 | 44 | { X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 }, |
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| 37 | 45 | { X86_FEATURE_SEV, CPUID_EAX, 1, 0x8000001f, 0 }, |
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| 46 | + { X86_FEATURE_SEV_ES, CPUID_EAX, 3, 0x8000001f, 0 }, |
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| 47 | + { X86_FEATURE_SME_COHERENT, CPUID_EAX, 10, 0x8000001f, 0 }, |
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| 38 | 48 | { 0, 0, 0, 0, 0 } |
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| 39 | 49 | }; |
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| 40 | 50 | |
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| .. | .. |
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| 60 | 70 | set_cpu_cap(c, cb->feature); |
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| 61 | 71 | } |
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| 62 | 72 | } |
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| 63 | | - |
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| 64 | | -u32 get_scattered_cpuid_leaf(unsigned int level, unsigned int sub_leaf, |
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| 65 | | - enum cpuid_regs_idx reg) |
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| 66 | | -{ |
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| 67 | | - const struct cpuid_bit *cb; |
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| 68 | | - u32 cpuid_val = 0; |
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| 69 | | - |
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| 70 | | - for (cb = cpuid_bits; cb->feature; cb++) { |
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| 71 | | - |
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| 72 | | - if (level > cb->level) |
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| 73 | | - continue; |
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| 74 | | - |
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| 75 | | - if (level < cb->level) |
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| 76 | | - break; |
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| 77 | | - |
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| 78 | | - if (reg == cb->reg && sub_leaf == cb->sub_leaf) { |
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| 79 | | - if (cpu_has(&boot_cpu_data, cb->feature)) |
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| 80 | | - cpuid_val |= BIT(cb->bit); |
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| 81 | | - } |
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| 82 | | - } |
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| 83 | | - |
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| 84 | | - return cpuid_val; |
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| 85 | | -} |
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| 86 | | -EXPORT_SYMBOL_GPL(get_scattered_cpuid_leaf); |
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