| .. | .. |
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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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| 1 | 2 | /* |
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| 2 | 3 | * AMD Memory Encryption Support |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
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| 5 | 6 | * |
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| 6 | 7 | * Author: Tom Lendacky <thomas.lendacky@amd.com> |
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| 7 | | - * |
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| 8 | | - * This program is free software; you can redistribute it and/or modify |
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| 9 | | - * it under the terms of the GNU General Public License version 2 as |
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| 10 | | - * published by the Free Software Foundation. |
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| 11 | 8 | */ |
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| 12 | 9 | |
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| 13 | 10 | #include <linux/linkage.h> |
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| .. | .. |
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| 18 | 15 | |
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| 19 | 16 | .text |
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| 20 | 17 | .code32 |
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| 21 | | -ENTRY(get_sev_encryption_bit) |
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| 18 | +SYM_FUNC_START(get_sev_encryption_bit) |
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| 22 | 19 | xor %eax, %eax |
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| 23 | 20 | |
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| 24 | 21 | #ifdef CONFIG_AMD_MEM_ENCRYPT |
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| 25 | 22 | push %ebx |
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| 26 | 23 | push %ecx |
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| 27 | 24 | push %edx |
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| 28 | | - |
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| 29 | | - /* Check if running under a hypervisor */ |
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| 30 | | - movl $1, %eax |
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| 31 | | - cpuid |
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| 32 | | - bt $31, %ecx /* Check the hypervisor bit */ |
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| 33 | | - jnc .Lno_sev |
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| 34 | 25 | |
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| 35 | 26 | movl $0x80000000, %eax /* CPUID to check the highest leaf */ |
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| 36 | 27 | cpuid |
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| .. | .. |
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| 67 | 58 | |
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| 68 | 59 | #endif /* CONFIG_AMD_MEM_ENCRYPT */ |
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| 69 | 60 | |
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| 70 | | - ret |
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| 71 | | -ENDPROC(get_sev_encryption_bit) |
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| 61 | + RET |
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| 62 | +SYM_FUNC_END(get_sev_encryption_bit) |
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| 72 | 63 | |
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| 73 | 64 | .code64 |
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| 74 | | -ENTRY(set_sev_encryption_mask) |
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| 65 | + |
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| 66 | +#include "../../kernel/sev_verify_cbit.S" |
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| 67 | + |
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| 68 | +SYM_FUNC_START(set_sev_encryption_mask) |
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| 75 | 69 | #ifdef CONFIG_AMD_MEM_ENCRYPT |
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| 76 | 70 | push %rbp |
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| 77 | 71 | push %rdx |
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| .. | .. |
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| 84 | 78 | |
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| 85 | 79 | bts %rax, sme_me_mask(%rip) /* Create the encryption mask */ |
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| 86 | 80 | |
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| 81 | + /* |
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| 82 | + * Read MSR_AMD64_SEV again and store it to sev_status. Can't do this in |
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| 83 | + * get_sev_encryption_bit() because this function is 32-bit code and |
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| 84 | + * shared between 64-bit and 32-bit boot path. |
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| 85 | + */ |
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| 86 | + movl $MSR_AMD64_SEV, %ecx /* Read the SEV MSR */ |
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| 87 | + rdmsr |
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| 88 | + |
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| 89 | + /* Store MSR value in sev_status */ |
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| 90 | + shlq $32, %rdx |
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| 91 | + orq %rdx, %rax |
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| 92 | + movq %rax, sev_status(%rip) |
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| 93 | + |
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| 87 | 94 | .Lno_sev_mask: |
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| 88 | 95 | movq %rbp, %rsp /* Restore original stack pointer */ |
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| 89 | 96 | |
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| .. | .. |
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| 92 | 99 | #endif |
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| 93 | 100 | |
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| 94 | 101 | xor %rax, %rax |
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| 95 | | - ret |
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| 96 | | -ENDPROC(set_sev_encryption_mask) |
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| 102 | + RET |
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| 103 | +SYM_FUNC_END(set_sev_encryption_mask) |
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| 97 | 104 | |
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| 98 | 105 | .data |
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| 99 | 106 | |
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| 100 | 107 | #ifdef CONFIG_AMD_MEM_ENCRYPT |
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| 101 | 108 | .balign 8 |
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| 102 | | -GLOBAL(sme_me_mask) |
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| 103 | | - .quad 0 |
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| 109 | +SYM_DATA(sme_me_mask, .quad 0) |
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| 110 | +SYM_DATA(sev_status, .quad 0) |
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| 111 | +SYM_DATA(sev_check_data, .quad 0) |
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| 104 | 112 | #endif |
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