| .. | .. |
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| 147 | 147 | flush_tlb_page(vma, address); |
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| 148 | 148 | } |
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| 149 | 149 | |
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| 150 | | -/* |
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| 151 | | - * flush the page walk cache for the address |
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| 152 | | - */ |
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| 153 | | -static inline void flush_tlb_pgtable(struct mmu_gather *tlb, unsigned long address) |
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| 154 | | -{ |
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| 155 | | - /* |
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| 156 | | - * Flush the page table walk cache on freeing a page table. We already |
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| 157 | | - * have marked the upper/higher level page table entry none by now. |
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| 158 | | - * So it is safe to flush PWC here. |
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| 159 | | - */ |
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| 160 | | - if (!radix_enabled()) |
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| 161 | | - return; |
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| 150 | +extern bool tlbie_capable; |
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| 151 | +extern bool tlbie_enabled; |
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| 162 | 152 | |
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| 163 | | - radix__flush_tlb_pwc(tlb, address); |
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| 153 | +static inline bool cputlb_use_tlbie(void) |
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| 154 | +{ |
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| 155 | + return tlbie_enabled; |
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| 164 | 156 | } |
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| 157 | + |
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| 165 | 158 | #endif /* _ASM_POWERPC_BOOK3S_64_TLBFLUSH_H */ |
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