disable cpu isolcpus

hc

2023-12-09 958e46acc8e900e8569dd467c1af9b8d2d019394

 kernel/arch/powerpc/include/asm/book3s/64/mmu.h
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@@ -2,6 +2,8 @@
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 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
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 #define _ASM_POWERPC_BOOK3S_64_MMU_H_
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+#include <asm/page.h>
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+
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 #ifndef __ASSEMBLY__
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 /*
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  * Page size definition
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@@ -23,7 +25,6 @@
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 	};
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 };
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 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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-
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 #endif /* __ASSEMBLY__ */
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29
 
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 /* 64-bit classic hash table MMU */
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@@ -66,6 +67,11 @@
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 /* Base PID to allocate from */
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 extern unsigned int mmu_base_pid;
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69
 
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+/*
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+ * memory block size used with radix translation.
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+ */
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+extern unsigned long __ro_after_init radix_mem_block_size;
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+
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 #define PRTB_SIZE_SHIFT	(mmu_pid_bits + 4)
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 #define PRTB_ENTRIES	(1ul << mmu_pid_bits)
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@@ -80,16 +86,6 @@
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 /* Maximum possible number of NPUs in a system. */
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 #define NV_MAX_NPUS 8
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88
 
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-/*
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- * One bit per slice. We have lower slices which cover 256MB segments
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- * upto 4G range. That gets us 16 low slices. For the rest we track slices
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- * in 1TB size.
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- */
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-struct slice_mask {
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-	u64 low_slices;
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-	DECLARE_BITMAP(high_slices, SLICE_NUM_HIGH);
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-};
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-
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 typedef struct {
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 	union {
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 		/*
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@@ -103,7 +99,6 @@
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 		mm_context_id_t id;
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 		mm_context_id_t extended_id[TASK_SIZE_USER64/TASK_CONTEXT_SIZE];
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 	};
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-	u16 user_psize;		/* page size index */
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 	/* Number of bits in the mm_cpumask */
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 	atomic_t active_cpus;
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@@ -111,29 +106,12 @@
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 	/* Number of users of the external (Nest) MMU */
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 	atomic_t copros;
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-	/* NPU NMMU context */
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-	struct npu_context *npu_context;
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+	/* Number of user space windows opened in process mm_context */
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+	atomic_t vas_windows;
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-#ifdef CONFIG_PPC_MM_SLICES
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-	 /* SLB page size encodings*/
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-	unsigned char low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE];
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-	unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
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-	unsigned long slb_addr_limit;
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-# ifdef CONFIG_PPC_64K_PAGES
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-	struct slice_mask mask_64k;
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-# endif
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-	struct slice_mask mask_4k;
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-# ifdef CONFIG_HUGETLB_PAGE
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-	struct slice_mask mask_16m;
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-	struct slice_mask mask_16g;
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-# endif
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-#else
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-	u16 sllp;		/* SLB page size encoding */
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-#endif
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+	struct hash_mm_context *hash_context;
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+
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 	unsigned long vdso_base;
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-#ifdef CONFIG_PPC_SUBPAGE_PROT
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-	struct subpage_prot_table spt;
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-#endif /* CONFIG_PPC_SUBPAGE_PROT */
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 	/*
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 	 * pagetable fragment support
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 	 */
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@@ -154,6 +132,60 @@
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 #endif
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 } mm_context_t;
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+static inline u16 mm_ctx_user_psize(mm_context_t *ctx)
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+{
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+	return ctx->hash_context->user_psize;
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+}
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+
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+static inline void mm_ctx_set_user_psize(mm_context_t *ctx, u16 user_psize)
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+{
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+	ctx->hash_context->user_psize = user_psize;
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+}
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+
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+static inline unsigned char *mm_ctx_low_slices(mm_context_t *ctx)
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+{
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+	return ctx->hash_context->low_slices_psize;
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+}
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+
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+static inline unsigned char *mm_ctx_high_slices(mm_context_t *ctx)
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+{
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+	return ctx->hash_context->high_slices_psize;
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+}
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+
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+static inline unsigned long mm_ctx_slb_addr_limit(mm_context_t *ctx)
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+{
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+	return ctx->hash_context->slb_addr_limit;
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+}
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+
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+static inline void mm_ctx_set_slb_addr_limit(mm_context_t *ctx, unsigned long limit)
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+{
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+	ctx->hash_context->slb_addr_limit = limit;
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+}
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+
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+static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize)
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+{
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+#ifdef CONFIG_PPC_64K_PAGES
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+	if (psize == MMU_PAGE_64K)
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+		return &ctx->hash_context->mask_64k;
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+#endif
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+#ifdef CONFIG_HUGETLB_PAGE
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+	if (psize == MMU_PAGE_16M)
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+		return &ctx->hash_context->mask_16m;
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+	if (psize == MMU_PAGE_16G)
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+		return &ctx->hash_context->mask_16g;
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+#endif
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+	BUG_ON(psize != MMU_PAGE_4K);
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+
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+	return &ctx->hash_context->mask_4k;
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+}
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+
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+#ifdef CONFIG_PPC_SUBPAGE_PROT
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+static inline struct subpage_prot_table *mm_ctx_subpage_prot(mm_context_t *ctx)
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+{
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+	return ctx->hash_context->spt;
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+}
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+#endif
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+
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 /*
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  * The current system page and segment sizes
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  */
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@@ -167,10 +199,15 @@
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 void mmu_early_init_devtree(void);
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 void hash__early_init_devtree(void);
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 void radix__early_init_devtree(void);
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-extern void radix_init_native(void);
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+#ifdef CONFIG_PPC_MEM_KEYS
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+void pkey_early_init_devtree(void);
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+#else
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+static inline void pkey_early_init_devtree(void) {}
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+#endif
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+
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 extern void hash__early_init_mmu(void);
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 extern void radix__early_init_mmu(void);
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-static inline void early_init_mmu(void)
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+static inline void __init early_init_mmu(void)
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 {
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 	if (radix_enabled())
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 		return radix__early_init_mmu();
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@@ -187,20 +224,17 @@
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224
 
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 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
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 					 phys_addr_t first_memblock_size);
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-extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
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-					 phys_addr_t first_memblock_size);
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 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
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 					      phys_addr_t first_memblock_size)
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 {
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-	if (early_radix_enabled())
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-		return radix__setup_initial_memory_limit(first_memblock_base,
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-						   first_memblock_size);
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+	/*
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+	 * Hash has more strict restrictions. At this point we don't
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+	 * know which translations we will pick. Hence go with hash
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+	 * restrictions.
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+	 */
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 	return hash__setup_initial_memory_limit(first_memblock_base,
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 					   first_memblock_size);
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 }
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-
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-extern int (*register_process_table)(unsigned long base, unsigned long page_size,
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-				     unsigned long tbl_size);
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 #ifdef CONFIG_PPC_PSERIES
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 extern void radix_init_pseries(void);
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@@ -208,7 +242,19 @@
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 static inline void radix_init_pseries(void) { };
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 #endif
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-static inline int get_ea_context(mm_context_t *ctx, unsigned long ea)
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+#ifdef CONFIG_HOTPLUG_CPU
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+#define arch_clear_mm_cpumask_cpu(cpu, mm)				\
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+	do {								\
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+		if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {		\
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+			atomic_dec(&(mm)->context.active_cpus);		\
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+			cpumask_clear_cpu(cpu, mm_cpumask(mm));		\
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+		}							\
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+	} while (0)
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+
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+void cleanup_cpu_mmu_context(void);
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+#endif
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+
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+static inline int get_user_context(mm_context_t *ctx, unsigned long ea)
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 {
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 	int index = ea >> MAX_EA_BITS_PER_CONTEXT;
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@@ -223,7 +269,7 @@
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 static inline unsigned long get_user_vsid(mm_context_t *ctx,
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 					  unsigned long ea, int ssize)
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 {
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-	unsigned long context = get_ea_context(ctx, ea);
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+	unsigned long context = get_user_context(ctx, ea);
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 	return get_vsid(context, ea, ssize);
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 }