disable cpu isolcpus

hc

2023-12-09 958e46acc8e900e8569dd467c1af9b8d2d019394

 kernel/arch/powerpc/include/asm/book3s/64/hash-64k.h
..
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@@ -2,16 +2,42 @@
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 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_64K_H
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 #define _ASM_POWERPC_BOOK3S_64_HASH_64K_H
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-#define H_PTE_INDEX_SIZE  8
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-#define H_PMD_INDEX_SIZE  10
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-#define H_PUD_INDEX_SIZE  10
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-#define H_PGD_INDEX_SIZE  8
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+#define H_PTE_INDEX_SIZE   8  // size: 8B <<  8 = 2KB, maps 2^8  x 64KB = 16MB
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+#define H_PMD_INDEX_SIZE  10  // size: 8B << 10 = 8KB, maps 2^10 x 16MB = 16GB
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+#define H_PUD_INDEX_SIZE  10  // size: 8B << 10 = 8KB, maps 2^10 x 16GB = 16TB
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+#define H_PGD_INDEX_SIZE   8  // size: 8B <<  8 = 2KB, maps 2^8  x 16TB =  4PB
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+
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+/*
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+ * If we store section details in page->flags we can't increase the MAX_PHYSMEM_BITS
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+ * if we increase SECTIONS_WIDTH we will not store node details in page->flags and
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+ * page_to_nid does a page->section->node lookup
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+ * Hence only increase for VMEMMAP. Further depending on SPARSEMEM_EXTREME reduce
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+ * memory requirements with large number of sections.
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+ * 51 bits is the max physical real address on POWER9
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+ */
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+#if defined(CONFIG_SPARSEMEM_VMEMMAP) && defined(CONFIG_SPARSEMEM_EXTREME)
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+#define H_MAX_PHYSMEM_BITS	51
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+#else
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+#define H_MAX_PHYSMEM_BITS	46
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+#endif
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 /*
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  * Each context is 512TB size. SLB miss for first context/default context
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  * is handled in the hotpath.
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  */
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 #define MAX_EA_BITS_PER_CONTEXT		49
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+#define REGION_SHIFT		MAX_EA_BITS_PER_CONTEXT
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+
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+/*
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+ * We use one context for each MAP area.
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+ */
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+#define H_KERN_MAP_SIZE		(1UL << MAX_EA_BITS_PER_CONTEXT)
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+
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+/*
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+ * Define the address range of the kernel non-linear virtual area
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+ * 2PB
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+ */
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+#define H_KERN_VIRT_START	ASM_CONST(0xc008000000000000)
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 /*
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  * 64k aligned address free up few of the lower bits of RPN for us
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@@ -19,15 +45,15 @@
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  */
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 #define H_PAGE_COMBO	_RPAGE_RPN0 /* this is a combo 4k page */
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 #define H_PAGE_4K_PFN	_RPAGE_RPN1 /* PFN is for a single 4k page */
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-#define H_PAGE_BUSY	_RPAGE_RPN44     /* software: PTE & hash are busy */
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+#define H_PAGE_BUSY	_RPAGE_RSV1     /* software: PTE & hash are busy */
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 #define H_PAGE_HASHPTE	_RPAGE_RPN43	/* PTE has associated HPTE */
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 /* memory key bits. */
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-#define H_PTE_PKEY_BIT0	_RPAGE_RSV1
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-#define H_PTE_PKEY_BIT1	_RPAGE_RSV2
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-#define H_PTE_PKEY_BIT2	_RPAGE_RSV3
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-#define H_PTE_PKEY_BIT3	_RPAGE_RSV4
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-#define H_PTE_PKEY_BIT4	_RPAGE_RSV5
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+#define H_PTE_PKEY_BIT4		_RPAGE_PKEY_BIT4
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+#define H_PTE_PKEY_BIT3		_RPAGE_PKEY_BIT3
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+#define H_PTE_PKEY_BIT2		_RPAGE_PKEY_BIT2
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+#define H_PTE_PKEY_BIT1		_RPAGE_PKEY_BIT1
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+#define H_PTE_PKEY_BIT0		_RPAGE_PKEY_BIT0
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 /*
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  * We need to differentiate between explicit huge page and THP huge