disable cpu isolcpus

hc

2023-12-09 958e46acc8e900e8569dd467c1af9b8d2d019394

 kernel/arch/powerpc/include/asm/book3s/64/hash-4k.h
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@@ -1,15 +1,11 @@
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 /* SPDX-License-Identifier: GPL-2.0 */
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 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H
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 #define _ASM_POWERPC_BOOK3S_64_HASH_4K_H
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-/*
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- * Entries per page directory level.  The PTE level must use a 64b record
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- * for each page table entry.  The PMD and PGD level use a 32b record for
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- * each entry by assuming that each entry is page aligned.
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- */
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-#define H_PTE_INDEX_SIZE  9
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-#define H_PMD_INDEX_SIZE  7
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-#define H_PUD_INDEX_SIZE  9
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-#define H_PGD_INDEX_SIZE  9
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+
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+#define H_PTE_INDEX_SIZE  9  // size: 8B << 9 = 4KB, maps: 2^9 x   4KB =   2MB
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+#define H_PMD_INDEX_SIZE  7  // size: 8B << 7 = 1KB, maps: 2^7 x   2MB = 256MB
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+#define H_PUD_INDEX_SIZE  9  // size: 8B << 9 = 4KB, maps: 2^9 x 256MB = 128GB
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+#define H_PGD_INDEX_SIZE  9  // size: 8B << 9 = 4KB, maps: 2^9 x 128GB =  64TB
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 /*
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  * Each context is 512TB. But on 4k we restrict our max TASK size to 64TB
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@@ -17,17 +13,36 @@
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  */
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 #define MAX_EA_BITS_PER_CONTEXT		46
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+
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+/*
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+ * Our page table limit us to 64TB. For 64TB physical memory, we only need 64GB
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+ * of vmemmap space. To better support sparse memory layout, we use 61TB
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+ * linear map range, 1TB of vmalloc, 1TB of I/O and 1TB of vmememmap.
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+ */
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+#define REGION_SHIFT		(40)
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+#define H_KERN_MAP_SIZE		(ASM_CONST(1) << REGION_SHIFT)
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+
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+/*
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+ * Limits the linear mapping range
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+ */
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+#define H_MAX_PHYSMEM_BITS	46
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+
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+/*
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+ * Define the address range of the kernel non-linear virtual area (61TB)
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+ */
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+#define H_KERN_VIRT_START	ASM_CONST(0xc0003d0000000000)
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+
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 #ifndef __ASSEMBLY__
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 #define H_PTE_TABLE_SIZE	(sizeof(pte_t) << H_PTE_INDEX_SIZE)
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 #define H_PMD_TABLE_SIZE	(sizeof(pmd_t) << H_PMD_INDEX_SIZE)
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 #define H_PUD_TABLE_SIZE	(sizeof(pud_t) << H_PUD_INDEX_SIZE)
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 #define H_PGD_TABLE_SIZE	(sizeof(pgd_t) << H_PGD_INDEX_SIZE)
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-#define H_PAGE_F_GIX_SHIFT	53
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-#define H_PAGE_F_SECOND	_RPAGE_RPN44	/* HPTE is in 2ndary HPTEG */
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-#define H_PAGE_F_GIX	(_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41)
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-#define H_PAGE_BUSY	_RPAGE_RSV1     /* software: PTE & hash are busy */
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-#define H_PAGE_HASHPTE	_RPAGE_RSV2     /* software: PTE & hash are busy */
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+#define H_PAGE_F_GIX_SHIFT	_PAGE_PA_MAX
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+#define H_PAGE_F_SECOND		_RPAGE_PKEY_BIT0 /* HPTE is in 2ndary HPTEG */
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+#define H_PAGE_F_GIX		(_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41)
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+#define H_PAGE_BUSY		_RPAGE_RSV1
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+#define H_PAGE_HASHPTE		_RPAGE_PKEY_BIT4
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 /* PTE flags to conserve for HPTE identification */
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 #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \
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@@ -46,11 +61,12 @@
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 #define H_PMD_FRAG_NR	(PAGE_SIZE >> H_PMD_FRAG_SIZE_SHIFT)
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 /* memory key bits, only 8 keys supported */
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-#define H_PTE_PKEY_BIT0	0
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-#define H_PTE_PKEY_BIT1	0
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-#define H_PTE_PKEY_BIT2	_RPAGE_RSV3
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-#define H_PTE_PKEY_BIT3	_RPAGE_RSV4
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-#define H_PTE_PKEY_BIT4	_RPAGE_RSV5
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+#define H_PTE_PKEY_BIT4	0
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+#define H_PTE_PKEY_BIT3	0
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+#define H_PTE_PKEY_BIT2	_RPAGE_PKEY_BIT3
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+#define H_PTE_PKEY_BIT1	_RPAGE_PKEY_BIT2
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+#define H_PTE_PKEY_BIT0	_RPAGE_PKEY_BIT1
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+
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 /*
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  * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range()
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@@ -66,7 +82,7 @@
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 	 * if it is not a pte and have hugepd shift mask
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 	 * set, then it is a hugepd directory pointer
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 	 */
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-	if (!(hpdval & _PAGE_PTE) &&
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+	if (!(hpdval & _PAGE_PTE) && (hpdval & _PAGE_PRESENT) &&
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 	    ((hpdval & HUGEPD_SHIFT_MASK) != 0))
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 		return true;
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 	return false;