disable cpu isolcpus

hc

2023-12-09 958e46acc8e900e8569dd467c1af9b8d2d019394

 kernel/arch/alpha/include/asm/atomic.h
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@@ -16,15 +16,14 @@
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 /*
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  * To ensure dependency ordering is preserved for the _relaxed and
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- * _release atomics, an smp_read_barrier_depends() is unconditionally
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- * inserted into the _relaxed variants, which are used to build the
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- * barriered versions. Avoid redundant back-to-back fences in the
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- * _acquire and _fence versions.
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+ * _release atomics, an smp_mb() is unconditionally inserted into the
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+ * _relaxed variants, which are used to build the barriered versions.
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+ * Avoid redundant back-to-back fences in the _acquire and _fence
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+ * versions.
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  */
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 #define __atomic_acquire_fence()
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 #define __atomic_post_full_fence()
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-#define ATOMIC_INIT(i)		{ (i) }
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 #define ATOMIC64_INIT(i)	{ (i) }
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 #define atomic_read(v)		READ_ONCE((v)->counter)
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@@ -70,7 +69,7 @@
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 	".previous"							\
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 	:"=&r" (temp), "=m" (v->counter), "=&r" (result)		\
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 	:"Ir" (i), "m" (v->counter) : "memory");			\
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-	smp_read_barrier_depends();					\
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+	smp_mb();							\
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 	return result;							\
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 }
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@@ -88,14 +87,14 @@
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 	".previous"							\
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 	:"=&r" (temp), "=m" (v->counter), "=&r" (result)		\
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 	:"Ir" (i), "m" (v->counter) : "memory");			\
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-	smp_read_barrier_depends();					\
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+	smp_mb();							\
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 	return result;							\
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 }
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 #define ATOMIC64_OP(op, asm_op)						\
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-static __inline__ void atomic64_##op(long i, atomic64_t * v)		\
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+static __inline__ void atomic64_##op(s64 i, atomic64_t * v)		\
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 {									\
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-	unsigned long temp;						\
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+	s64 temp;							\
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 	__asm__ __volatile__(						\
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 	"1:	ldq_l %0,%1\n"						\
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 	"	" #asm_op " %0,%2,%0\n"					\
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@@ -109,9 +108,9 @@
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 }									\
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 #define ATOMIC64_OP_RETURN(op, asm_op)					\
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-static __inline__ long atomic64_##op##_return_relaxed(long i, atomic64_t * v)	\
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+static __inline__ s64 atomic64_##op##_return_relaxed(s64 i, atomic64_t * v)	\
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 {									\
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-	long temp, result;						\
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+	s64 temp, result;						\
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 	__asm__ __volatile__(						\
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 	"1:	ldq_l %0,%1\n"						\
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 	"	" #asm_op " %0,%3,%2\n"					\
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@@ -123,14 +122,14 @@
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 	".previous"							\
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 	:"=&r" (temp), "=m" (v->counter), "=&r" (result)		\
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 	:"Ir" (i), "m" (v->counter) : "memory");			\
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-	smp_read_barrier_depends();					\
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+	smp_mb();							\
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 	return result;							\
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 }
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 #define ATOMIC64_FETCH_OP(op, asm_op)					\
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-static __inline__ long atomic64_fetch_##op##_relaxed(long i, atomic64_t * v)	\
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+static __inline__ s64 atomic64_fetch_##op##_relaxed(s64 i, atomic64_t * v)	\
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 {									\
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-	long temp, result;						\
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+	s64 temp, result;						\
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 	__asm__ __volatile__(						\
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 	"1:	ldq_l %2,%1\n"						\
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 	"	" #asm_op " %2,%3,%0\n"					\
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@@ -141,7 +140,7 @@
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 	".previous"							\
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 	:"=&r" (temp), "=m" (v->counter), "=&r" (result)		\
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 	:"Ir" (i), "m" (v->counter) : "memory");			\
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-	smp_read_barrier_depends();					\
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+	smp_mb();							\
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 	return result;							\
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 }
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@@ -246,9 +245,9 @@
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  * Atomically adds @a to @v, so long as it was not @u.
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  * Returns the old value of @v.
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  */
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-static __inline__ long atomic64_fetch_add_unless(atomic64_t *v, long a, long u)
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+static __inline__ s64 atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
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 {
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-	long c, new, old;
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+	s64 c, new, old;
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 	smp_mb();
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 	__asm__ __volatile__(
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 	"1:	ldq_l	%[old],%[mem]\n"
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@@ -276,9 +275,9 @@
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  * The function returns the old value of *v minus 1, even if
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  * the atomic variable, v, was not decremented.
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  */
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-static inline long atomic64_dec_if_positive(atomic64_t *v)
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+static inline s64 atomic64_dec_if_positive(atomic64_t *v)
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 {
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-	long old, tmp;
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+	s64 old, tmp;
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 	smp_mb();
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 	__asm__ __volatile__(
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 	"1:	ldq_l	%[old],%[mem]\n"