disable cpu isolcpus

hc

2023-12-09 958e46acc8e900e8569dd467c1af9b8d2d019394

 kernel/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt
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@@ -23,7 +23,7 @@
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 - marvell,spi-base     : List of GIC base SPI interrupts, one for each
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                          ODMI frame. Those SPI interrupts are 0-based,
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                          i.e marvell,spi-base = <128> will use SPI #96.
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-                         See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
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+                         See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
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                          for details about the GIC Device Tree binding.
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 Example: