enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/sound/hda/hdac_stream.c
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@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * HD-audio stream operations
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  */
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@@ -11,6 +12,40 @@
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 #include <sound/hdaudio.h>
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 #include <sound/hda_register.h>
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 #include "trace.h"
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+
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+/**
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+ * snd_hdac_get_stream_stripe_ctl - get stripe control value
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+ * @bus: HD-audio core bus
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+ * @substream: PCM substream
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+ */
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+int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
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+				   struct snd_pcm_substream *substream)
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+{
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+	struct snd_pcm_runtime *runtime = substream->runtime;
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+	unsigned int channels = runtime->channels,
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+		     rate = runtime->rate,
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+		     bits_per_sample = runtime->sample_bits,
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+		     max_sdo_lines, value, sdo_line;
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+
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+	/* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
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+	max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
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+
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+	/* following is from HD audio spec */
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+	for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
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+		if (rate > 48000)
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+			value = (channels * bits_per_sample *
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+					(rate / 48000)) / sdo_line;
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+		else
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+			value = (channels * bits_per_sample) / sdo_line;
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+
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+		if (value >= bus->sdo_limit)
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+			break;
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+	}
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+
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+	/* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
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+	return sdo_line >> 1;
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+}
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+EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
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49
 
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 /**
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  * snd_hdac_stream_init - initialize each stream (aka device)
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@@ -48,6 +83,7 @@
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 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
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 {
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 	struct hdac_bus *bus = azx_dev->bus;
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+	int stripe_ctl;
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87
 
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 	trace_snd_hdac_stream_start(bus, azx_dev);
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89
 
..
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@@ -56,7 +92,18 @@
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 		azx_dev->start_wallclk -= azx_dev->period_wallclk;
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93
 
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 	/* enable SIE */
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-	snd_hdac_chip_updatel(bus, INTCTL, 0, 1 << azx_dev->index);
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+	snd_hdac_chip_updatel(bus, INTCTL,
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+			      1 << azx_dev->index,
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+			      1 << azx_dev->index);
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+	/* set stripe control */
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+	if (azx_dev->stripe) {
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+		if (azx_dev->substream)
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+			stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
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+		else
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+			stripe_ctl = 0;
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+		snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
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+					stripe_ctl);
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+	}
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107
 	/* set DMA start and interrupt mask */
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 	snd_hdac_stream_updateb(azx_dev, SD_CTL,
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 				0, SD_CTL_DMA_START | SD_INT_MASK);
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..
@@ -73,6 +120,8 @@
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 	snd_hdac_stream_updateb(azx_dev, SD_CTL,
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 				SD_CTL_DMA_START | SD_INT_MASK, 0);
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122
 	snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
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+	if (azx_dev->stripe)
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+		snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
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 	azx_dev->running = false;
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126
 }
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127
 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
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@@ -101,8 +150,11 @@
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 {
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 	unsigned char val;
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152
 	int timeout;
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+	int dma_run_state;
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154
 
105
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 	snd_hdac_stream_clear(azx_dev);
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+
157
+	dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
106
158
 
107
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 	snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
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160
 	udelay(3);
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@@ -113,6 +165,10 @@
113
165
 		if (val)
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166
 			break;
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167
 	} while (--timeout);
168
+
169
+	if (azx_dev->bus->dma_stop_delay && dma_run_state)
170
+		udelay(azx_dev->bus->dma_stop_delay);
171
+
116
172
 	val &= ~SD_CTL_STREAM_RESET;
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173
 	snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
118
174
 	udelay(3);
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@@ -183,11 +239,7 @@
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 	/* set the interrupt enable bits in the descriptor control register */
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 	snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
185
241
 
186
-	if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK)
187
-		azx_dev->fifo_size =
188
-			snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
189
-	else
190
-		azx_dev->fifo_size = 0;
242
+	azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
191
243
 
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244
 	/* when LPIB delay correction gives a small negative value,
193
245
 	 * we ignore it; currently set the threshold statically to
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@@ -244,6 +296,7 @@
244
296
 	int key = (substream->pcm->device << 16) | (substream->number << 2) |
245
297
 		(substream->stream + 1);
246
298
 
299
+	spin_lock_irq(&bus->reg_lock);
247
300
 	list_for_each_entry(azx_dev, &bus->stream_list, list) {
248
301
 		if (azx_dev->direction != substream->stream)
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302
 			continue;
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@@ -257,13 +310,12 @@
257
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 			res = azx_dev;
258
311
 	}
259
312
 	if (res) {
260
-		spin_lock_irq(&bus->reg_lock);
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 		res->opened = 1;
262
314
 		res->running = 0;
263
315
 		res->assigned_key = key;
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316
 		res->substream = substream;
265
-		spin_unlock_irq(&bus->reg_lock);
266
317
 	}
318
+	spin_unlock_irq(&bus->reg_lock);
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 	return res;
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320
 }
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321
 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
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@@ -545,7 +597,9 @@
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 /**
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  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
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  * @azx_dev: HD-audio core stream (master stream)
600
+ * @set: true = set, false = clear
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  * @streams: bit flags of streams to sync
602
+ * @reg: the stream sync register address
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  */
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 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
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 				  unsigned int streams, unsigned int reg)
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@@ -584,20 +638,27 @@
584
638
 		nwait = 0;
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639
 		i = 0;
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640
 		list_for_each_entry(s, &bus->stream_list, list) {
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-			if (streams & (1 << i)) {
588
-				if (start) {
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-					/* check FIFO gets ready */
590
-					if (!(snd_hdac_stream_readb(s, SD_STS) &
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-					      SD_STS_FIFO_READY))
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-						nwait++;
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-				} else {
594
-					/* check RUN bit is cleared */
595
-					if (snd_hdac_stream_readb(s, SD_CTL) &
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-					    SD_CTL_DMA_START)
597
-						nwait++;
641
+			if (!(streams & (1 << i++)))
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+				continue;
643
+
644
+			if (start) {
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+				/* check FIFO gets ready */
646
+				if (!(snd_hdac_stream_readb(s, SD_STS) &
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+				      SD_STS_FIFO_READY))
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+					nwait++;
649
+			} else {
650
+				/* check RUN bit is cleared */
651
+				if (snd_hdac_stream_readb(s, SD_CTL) &
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+				    SD_CTL_DMA_START) {
653
+					nwait++;
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+					/*
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+					 * Perform stream reset if DMA RUN
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+					 * bit not cleared within given timeout
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+					 */
658
+					if (timeout == 1)
659
+						snd_hdac_stream_reset(s);
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660
 				}
599
661
 			}
600
-			i++;
601
662
 		}
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663
 		if (!nwait)
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664
 			break;
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@@ -634,8 +695,8 @@
634
695
 	azx_dev->locked = true;
635
696
 	spin_unlock_irq(&bus->reg_lock);
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697
 
637
-	err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV_SG,
638
-					   byte_size, bufp);
698
+	err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
699
+				  byte_size, bufp);
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 	if (err < 0)
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701
 		goto err_alloc;
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702
 
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@@ -661,7 +722,7 @@
661
722
 	return azx_dev->stream_tag;
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723
 
663
724
  error:
664
-	bus->io_ops->dma_free_pages(bus, bufp);
725
+	snd_dma_free_pages(bufp);
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726
  err_alloc:
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727
 	spin_lock_irq(&bus->reg_lock);
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 	azx_dev->locked = false;
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@@ -708,7 +769,7 @@
708
769
 	azx_dev->period_bytes = 0;
709
770
 	azx_dev->format_val = 0;
710
771
 
711
-	bus->io_ops->dma_free_pages(bus, dmab);
772
+	snd_dma_free_pages(dmab);
712
773
 	dmab->area = NULL;
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774
 
714
775
 	spin_lock_irq(&bus->reg_lock);