| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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| 1 | 2 | /* |
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| 2 | 3 | * sp5100_tco : TCO timer driver for sp5100 chipsets |
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| 3 | 4 | * |
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| .. | .. |
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| 6 | 7 | * Based on i8xx_tco.c: |
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| 7 | 8 | * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights |
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| 8 | 9 | * Reserved. |
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| 9 | | - * http://www.kernelconcepts.de |
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| 10 | | - * |
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| 11 | | - * This program is free software; you can redistribute it and/or |
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| 12 | | - * modify it under the terms of the GNU General Public License |
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| 13 | | - * as published by the Free Software Foundation; either version |
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| 14 | | - * 2 of the License, or (at your option) any later version. |
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| 10 | + * https://www.kernelconcepts.de |
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| 15 | 11 | * |
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| 16 | 12 | * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide", |
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| 17 | 13 | * AMD Publication 45482 "AMD SB800-Series Southbridges Register |
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| .. | .. |
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| 21 | 17 | * AMD Publication 51192 "AMD Bolton FCH Register Reference Guide" |
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| 22 | 18 | * AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG) |
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| 23 | 19 | * for AMD Family 16h Models 30h-3Fh Processors" |
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| 20 | + * AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR) |
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| 21 | + * for AMD Family 17h Model 18h, Revision B1 |
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| 22 | + * Processors (PUB) |
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| 23 | + * AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR) |
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| 24 | + * for AMD Family 17h Model 20h, Revision A1 |
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| 25 | + * Processors (PUB) |
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| 24 | 26 | */ |
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| 25 | 27 | |
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| 26 | 28 | /* |
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| .. | .. |
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| 245 | 247 | break; |
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| 246 | 248 | case efch: |
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| 247 | 249 | dev_name = SB800_DEVNAME; |
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| 250 | + /* |
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| 251 | + * On Family 17h devices, the EFCH_PM_DECODEEN_WDT_TMREN bit of |
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| 252 | + * EFCH_PM_DECODEEN not only enables the EFCH_PM_WDT_ADDR memory |
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| 253 | + * region, it also enables the watchdog itself. |
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| 254 | + */ |
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| 255 | + if (boot_cpu_data.x86 == 0x17) { |
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| 256 | + val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN); |
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| 257 | + if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) { |
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| 258 | + sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN, 0xff, |
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| 259 | + EFCH_PM_DECODEEN_WDT_TMREN); |
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| 260 | + } |
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| 261 | + } |
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| 248 | 262 | val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN); |
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| 249 | 263 | if (val & EFCH_PM_DECODEEN_WDT_TMREN) |
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| 250 | 264 | mmio_addr = EFCH_PM_WDT_ADDR; |
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| .. | .. |
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| 395 | 409 | wdd->min_timeout = 1; |
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| 396 | 410 | wdd->max_timeout = 0xffff; |
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| 397 | 411 | |
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| 398 | | - if (watchdog_init_timeout(wdd, heartbeat, NULL)) |
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| 399 | | - dev_info(dev, "timeout value invalid, using %d\n", |
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| 400 | | - wdd->timeout); |
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| 412 | + watchdog_init_timeout(wdd, heartbeat, NULL); |
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| 401 | 413 | watchdog_set_nowayout(wdd, nowayout); |
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| 402 | 414 | watchdog_stop_on_reboot(wdd); |
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| 403 | 415 | watchdog_stop_on_unregister(wdd); |
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| .. | .. |
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| 408 | 420 | return ret; |
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| 409 | 421 | |
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| 410 | 422 | ret = devm_watchdog_register_device(dev, wdd); |
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| 411 | | - if (ret) { |
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| 412 | | - dev_err(dev, "cannot register watchdog device (err=%d)\n", ret); |
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| 423 | + if (ret) |
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| 413 | 424 | return ret; |
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| 414 | | - } |
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| 415 | 425 | |
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| 416 | 426 | /* Show module parameters */ |
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| 417 | 427 | dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n", |
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