~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,21 +1,13 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3	4	* Author: Addy Ke <addy.ke@rock-chips.com>
4		- *
5		- * This program is free software; you can redistribute it and/or modify it
6		- * under the terms and conditions of the GNU General Public License,
7		- * version 2, as published by the Free Software Foundation.
8		- *
9		- * This program is distributed in the hope it will be useful, but WITHOUT
10		- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11		- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12		- * more details.
13		- *
14	5	*/
15	6
	7	+#include <linux/acpi.h>
16	8	#include <linux/clk.h>
	9	+#include <linux/delay.h>
17	10	#include <linux/dmaengine.h>
18		-#include <linux/gpio.h>
19	11	#include <linux/interrupt.h>
20	12	#include <linux/miscdevice.h>
21	13	#include <linux/module.h>
..	..	@@ -181,6 +173,12 @@
181	173
182	174	#define ROCKCHIP_SPI_REGISTER_SIZE 0x1000
183	175
	176	+enum rockchip_spi_xfer_mode {
	177	+ ROCKCHIP_SPI_DMA,
	178	+ ROCKCHIP_SPI_IRQ,
	179	+ ROCKCHIP_SPI_POLL,
	180	+};
	181	+
184	182	struct rockchip_spi_quirks {
185	183	u32 max_baud_div_in_cpha;
186	184	};
..	..	@@ -190,6 +188,7 @@
190	188
191	189	struct clk *spiclk;
192	190	struct clk *apb_pclk;
	191	+ struct clk *sclk_in;
193	192
194	193	void __iomem *regs;
195	194	dma_addr_t dma_addr_rx;
..	..	@@ -201,7 +200,9 @@
201	200	unsigned int rx_left;
202	201
203	202	atomic_t state;
	203	+ struct completion xfer_done;
204	204
	205	+ u32 version;
205	206	/depth of the FIFO buffer /
206	207	u32 fifo_len;
207	208	/* frequency of spiclk */
..	..	@@ -211,13 +212,16 @@
211	212
212	213	u8 n_bytes;
213	214	u8 rsd;
	215	+ u8 csm;
	216	+ bool poll; /* only support transfer data by cpu polling */
214	217
215	218	bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
216	219
217	220	struct pinctrl_state *high_speed_state;
218		- bool slave_abort;
219		- bool gpio_requested;
	221	+ bool slave_aborted;
220	222	bool cs_inactive; /* spi slave tansmition stop when cs inactive */
	223	+ bool cs_high_supported; /* native CS supports active-high polarity */
	224	+
221	225	struct spi_transfer xfer; / Store xfer temporarily */
222	226	phys_addr_t base_addr_phy;
223	227	struct miscdevice miscdev;
..	..	@@ -231,17 +235,29 @@
231	235	writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
232	236	}
233	237
234		-static inline void wait_for_idle(struct rockchip_spi *rs, bool slave_mode)
	238	+static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
235	239	{
236	240	unsigned long timeout = jiffies + msecs_to_jiffies(5);
	241	+ u32 bit_filed = SR_BUSY;
	242	+ u32 idle_val = 0;
	243	+ uint32_t speed, us;
	244	+
	245	+ if (slave_mode && rs->version == ROCKCHIP_SPI_VER2_TYPE2) {
	246	+ bit_filed = SR_SLAVE_TX_BUSY;
	247	+ idle_val = 0;
	248	+ } else if (slave_mode) {
	249	+ bit_filed = SR_TF_EMPTY;
	250	+ idle_val = 1;
	251	+ }
237	252
238	253	do {
239		- if (slave_mode) {
240		- if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY))
241		- return;
242		- } else {
243		- if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
244		- return;
	254	+ if ((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & bit_filed) == idle_val) {
	255	+ if (bit_filed == SR_TF_EMPTY) {
	256	+ speed = rs->speed_hz;
	257	+ us = (8 * 1000000 / speed) * 2;
	258	+ udelay(us);
	259	+ }
	260	+ return;
245	261	}
246	262	} while (!time_after(jiffies, timeout));
247	263
..	..	@@ -250,11 +266,7 @@
250	266
251	267	static u32 get_fifo_len(struct rockchip_spi *rs)
252	268	{
253		- u32 ver;
254		-
255		- ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
256		-
257		- switch (ver) {
	269	+ switch (rs->version) {
258	270	case ROCKCHIP_SPI_VER2_TYPE1:
259	271	case ROCKCHIP_SPI_VER2_TYPE2:
260	272	return 64;
..	..	@@ -277,12 +289,12 @@
277	289	/* Keep things powered as long as CS is asserted */
278	290	pm_runtime_get_sync(rs->dev);
279	291
280		- if (gpio_is_valid(spi->cs_gpio))
	292	+ if (spi->cs_gpiod)
281	293	ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
282	294	else
283	295	ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
284	296	} else {
285		- if (gpio_is_valid(spi->cs_gpio))
	297	+ if (spi->cs_gpiod)
286	298	ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
287	299	else
288	300	ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
..	..	@@ -299,6 +311,11 @@
299	311	{
300	312	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
301	313
	314	+ dev_err(rs->dev, "state=%x\n", atomic_read(&rs->state));
	315	+ dev_err(rs->dev, "tx_left=%x\n", rs->tx_left);
	316	+ dev_err(rs->dev, "rx_left=%x\n", rs->rx_left);
	317	+ print_hex_dump(KERN_ERR, "regs ", DUMP_PREFIX_OFFSET, 4, 4, rs->regs, 0x4c, 0);
	318	+
302	319	/* stop running spi transfer
303	320	* this also flushes both rx and tx fifos
304	321	*/
..	..	@@ -313,6 +330,7 @@
313	330
314	331	if (atomic_read(&rs->state) & RXDMA)
315	332	dmaengine_terminate_async(ctlr->dma_rx);
	333	+ atomic_set(&rs->state, 0);
316	334	}
317	335
318	336	static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
..	..	@@ -337,7 +355,7 @@
337	355	static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
338	356	{
339	357	u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
340		- u32 rx_left = rs->rx_left > words ? rs->rx_left - words : 0;
	358	+ u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
341	359
342	360	/* the hardware doesn't allow us to change fifo threshold
343	361	* level while spi is enabled, so instead make sure to leave
..	..	@@ -374,7 +392,7 @@
374	392	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
375	393
376	394	/* When int_cs_inactive comes, spi slave abort */
377		- if (readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
	395	+ if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_ISR) & INT_CS_INACTIVE) {
378	396	ctlr->slave_abort(ctlr);
379	397	writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
380	398	writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
..	..	@@ -390,7 +408,7 @@
390	408	spi_enable_chip(rs, false);
391	409	writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
392	410	writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
393		- spi_finalize_current_transfer(ctlr);
	411	+ complete(&rs->xfer_done);
394	412	}
395	413
396	414	return IRQ_HANDLED;
..	..	@@ -400,8 +418,6 @@
400	418	struct spi_controller *ctlr,
401	419	struct spi_transfer *xfer)
402	420	{
403		- rs->tx = xfer->tx_buf;
404		- rs->rx = xfer->rx_buf;
405	421	rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
406	422	rs->rx_left = xfer->len / rs->n_bytes;
407	423
..	..	@@ -427,14 +443,16 @@
427	443	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
428	444	int state = atomic_fetch_andnot(RXDMA, &rs->state);
429	445
430		- if (state & TXDMA && !rs->slave_abort)
	446	+ if (state & TXDMA && !rs->slave_aborted)
431	447	return;
432	448
433	449	if (rs->cs_inactive)
434	450	writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
435	451
436	452	spi_enable_chip(rs, false);
437		- spi_finalize_current_transfer(ctlr);
	453	+ writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
	454	+ writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
	455	+ complete(&rs->xfer_done);
438	456	}
439	457
440	458	static void rockchip_spi_dma_txcb(void *data)
..	..	@@ -443,14 +461,16 @@
443	461	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
444	462	int state = atomic_fetch_andnot(TXDMA, &rs->state);
445	463
446		- if (state & RXDMA && !rs->slave_abort)
	464	+ if (state & RXDMA && !rs->slave_aborted)
447	465	return;
448	466
449	467	/* Wait until the FIFO data completely. */
450		- wait_for_idle(rs, ctlr->slave);
	468	+ wait_for_tx_idle(rs, ctlr->slave);
451	469
452	470	spi_enable_chip(rs, false);
453		- spi_finalize_current_transfer(ctlr);
	471	+ writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
	472	+ writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
	473	+ complete(&rs->xfer_done);
454	474	}
455	475
456	476	static u32 rockchip_spi_calc_burst_size(u32 data_len)
..	..	@@ -472,9 +492,6 @@
472	492	struct dma_async_tx_descriptor rxdesc, txdesc;
473	493
474	494	atomic_set(&rs->state, 0);
475		-
476		- rs->tx = xfer->tx_buf;
477		- rs->rx = xfer->rx_buf;
478	495
479	496	rxdesc = NULL;
480	497	if (xfer->rx_buf) {
..	..	@@ -504,7 +521,7 @@
504	521	.direction = DMA_MEM_TO_DEV,
505	522	.dst_addr = rs->dma_addr_tx,
506	523	.dst_addr_width = rs->n_bytes,
507		- .dst_maxburst = 8,
	524	+ .dst_maxburst = rs->fifo_len / 4,
508	525	};
509	526
510	527	dmaengine_slave_config(ctlr->dma_tx, &txconf);
..	..	@@ -545,9 +562,59 @@
545	562	return 1;
546	563	}
547	564
548		-static void rockchip_spi_config(struct rockchip_spi *rs,
	565	+static int rockchip_spi_pio_transfer(struct rockchip_spi *rs,
	566	+ struct spi_controller ctlr, struct spi_transfer xfer)
	567	+{
	568	+ unsigned long time, timeout;
	569	+ u32 speed_hz = xfer->speed_hz;
	570	+ unsigned long long ms;
	571	+ int ret = 0;
	572	+
	573	+ if (!speed_hz)
	574	+ speed_hz = 100000;
	575	+
	576	+ ms = 8LL * 1000LL * xfer->len;
	577	+ do_div(ms, speed_hz);
	578	+ ms += ms + 200; /* some tolerance */
	579	+
	580	+ if (ms > UINT_MAX \|\| ctlr->slave)
	581	+ ms = UINT_MAX;
	582	+
	583	+ timeout = jiffies + msecs_to_jiffies(ms);
	584	+ time = jiffies;
	585	+ rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
	586	+ rs->rx_left = rs->rx ? xfer->len / rs->n_bytes : 0;
	587	+
	588	+ spi_enable_chip(rs, true);
	589	+
	590	+ while (rs->tx_left \|\| rs->rx_left) {
	591	+ if (rs->tx)
	592	+ rockchip_spi_pio_writer(rs);
	593	+
	594	+ if (rs->rx)
	595	+ rockchip_spi_pio_reader(rs);
	596	+
	597	+ cpu_relax();
	598	+
	599	+ if (time_after(time, timeout)) {
	600	+ ret = -EIO;
	601	+ goto out;
	602	+ }
	603	+ };
	604	+
	605	+ /* If tx, wait until the FIFO data completely. */
	606	+ if (rs->tx)
	607	+ wait_for_tx_idle(rs, ctlr->slave);
	608	+
	609	+out:
	610	+ spi_enable_chip(rs, false);
	611	+
	612	+ return ret;
	613	+}
	614	+
	615	+static int rockchip_spi_config(struct rockchip_spi *rs,
549	616	struct spi_device spi, struct spi_transfer xfer,
550		- bool use_dma, bool slave_mode)
	617	+ enum rockchip_spi_xfer_mode xfer_mode, bool slave_mode)
551	618	{
552	619	u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET
553	620	\| CR0_BHT_8BIT << CR0_BHT_OFFSET
..	..	@@ -558,21 +625,33 @@
558	625
559	626	if (slave_mode)
560	627	cr0 \|= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
561		- rs->slave_abort = false;
	628	+ rs->slave_aborted = false;
562	629
563	630	cr0 \|= rs->rsd << CR0_RSD_OFFSET;
	631	+ cr0 \|= rs->csm << CR0_CSM_OFFSET;
564	632	cr0 \|= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
565	633	if (spi->mode & SPI_LSB_FIRST)
566	634	cr0 \|= CR0_FBM_LSB << CR0_FBM_OFFSET;
567	635	if (spi->mode & SPI_CS_HIGH)
568	636	cr0 \|= BIT(spi->chip_select) << CR0_SOI_OFFSET;
569	637
570		- if (xfer->rx_buf && xfer->tx_buf)
	638	+ if (xfer->rx_buf && xfer->tx_buf) {
571	639	cr0 \|= CR0_XFM_TR << CR0_XFM_OFFSET;
572		- else if (xfer->rx_buf)
	640	+ } else if (xfer->rx_buf) {
573	641	cr0 \|= CR0_XFM_RO << CR0_XFM_OFFSET;
574		- else if (use_dma)
575		- cr0 \|= CR0_XFM_TO << CR0_XFM_OFFSET;
	642	+ } else if (xfer->tx_buf) {
	643	+ /*
	644	+ * Use the water line of rx fifo in full duplex mode to trigger
	645	+ * the interruption of tx irq transmission completion.
	646	+ */
	647	+ if (xfer_mode == ROCKCHIP_SPI_IRQ)
	648	+ cr0 \|= CR0_XFM_TR << CR0_XFM_OFFSET;
	649	+ else
	650	+ cr0 \|= CR0_XFM_TO << CR0_XFM_OFFSET;
	651	+ } else {
	652	+ dev_err(rs->dev, "no transmission buffer\n");
	653	+ return -EINVAL;
	654	+ }
576	655
577	656	switch (xfer->bits_per_word) {
578	657	case 4:
..	..	@@ -592,10 +671,12 @@
592	671	* ctlr->bits_per_word_mask, so this shouldn't
593	672	* happen
594	673	*/
595		- unreachable();
	674	+ dev_err(rs->dev, "unknown bits per word: %d\n",
	675	+ xfer->bits_per_word);
	676	+ return -EINVAL;
596	677	}
597	678
598		- if (use_dma) {
	679	+ if (xfer_mode == ROCKCHIP_SPI_DMA) {
599	680	if (xfer->tx_buf)
600	681	dmacr \|= TF_DMA_EN;
601	682	if (xfer->rx_buf)
..	..	@@ -652,6 +733,8 @@
652	733	writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
653	734	rs->regs + ROCKCHIP_SPI_BAUDR);
654	735	rs->speed_hz = xfer->speed_hz;
	736	+
	737	+ return 0;
655	738	}
656	739
657	740	static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
..	..	@@ -663,50 +746,54 @@
663	746	{
664	747	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
665	748	u32 rx_fifo_left;
666		- struct dma_tx_state state;
667		- enum dma_status status;
668	749
669		- /* Get current dma rx point */
670		- if (atomic_read(&rs->state) & RXDMA) {
671		- dmaengine_pause(ctlr->dma_rx);
672		- status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state);
673		- if (status == DMA_ERROR) {
674		- rs->rx = rs->xfer->rx_buf;
675		- rs->xfer->len = 0;
676		- rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
677		- for (; rx_fifo_left; rx_fifo_left--)
678		- readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
679		- goto out;
680		- } else {
681		- rs->rx += rs->xfer->len - rs->n_bytes * state.residue;
682		- }
683		- }
	750	+ /* Flush rx fifo */
	751	+ rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
	752	+ for (; rx_fifo_left; rx_fifo_left--)
	753	+ readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
684	754
685		- /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */
686		- if (rs->rx) {
687		- rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
688		- for (; rx_fifo_left; rx_fifo_left--) {
689		- u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
	755	+ rs->slave_aborted = true;
	756	+ complete(&rs->xfer_done);
690	757
691		- if (rs->n_bytes == 1)
692		- (u8 )rs->rx = (u8)rxw;
693		- else
694		- (u16 )rs->rx = (u16)rxw;
695		- rs->rx += rs->n_bytes;
	758	+ return 0;
	759	+}
	760	+
	761	+static int rockchip_spi_transfer_wait(struct spi_controller *ctlr,
	762	+ struct spi_transfer *xfer)
	763	+{
	764	+ struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
	765	+ u32 speed_hz = xfer->speed_hz;
	766	+ unsigned long long ms;
	767	+
	768	+ if (spi_controller_is_slave(ctlr)) {
	769	+ if (wait_for_completion_interruptible(&rs->xfer_done)) {
	770	+ dev_dbg(rs->dev, "RK SPI transfer interrupted\n");
	771	+ return -EINTR;
696	772	}
697	773
698		- rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf);
699		- }
	774	+ if (rs->slave_aborted) {
	775	+ dev_err(rs->dev, "RK SPI transfer slave abort\n");
	776	+ return -EIO;
	777	+ }
	778	+ } else {
	779	+ if (!speed_hz)
	780	+ speed_hz = 100000;
700	781
701		-out:
702		- if (atomic_read(&rs->state) & RXDMA)
703		- dmaengine_terminate_sync(ctlr->dma_rx);
704		- if (atomic_read(&rs->state) & TXDMA)
705		- dmaengine_terminate_sync(ctlr->dma_tx);
706		- atomic_set(&rs->state, 0);
707		- spi_enable_chip(rs, false);
708		- rs->slave_abort = true;
709		- complete(&ctlr->xfer_completion);
	782	+ ms = 8LL * 1000LL * xfer->len;
	783	+ do_div(ms, speed_hz);
	784	+ ms += ms + 200; /* some tolerance */
	785	+
	786	+ if (ms > UINT_MAX)
	787	+ ms = UINT_MAX;
	788	+
	789	+ ms = wait_for_completion_timeout(&rs->xfer_done,
	790	+ msecs_to_jiffies(ms));
	791	+
	792	+ if (ms == 0) {
	793	+ dev_err(rs->dev, "RK SPI transfer timed out\n");
	794	+ return -ETIMEDOUT;
	795	+ }
	796	+ }
710	797
711	798	return 0;
712	799	}
..	..	@@ -717,11 +804,13 @@
717	804	struct spi_transfer *xfer)
718	805	{
719	806	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
	807	+ int ret;
720	808	bool use_dma;
	809	+ enum rockchip_spi_xfer_mode xfer_mode;
721	810
722	811	/* Zero length transfers won't trigger an interrupt on completion */
723	812	if (!xfer->len) {
724		- spi_finalize_current_transfer(ctlr);
	813	+ complete(&rs->xfer_done);
725	814	return 1;
726	815	}
727	816
..	..	@@ -740,14 +829,40 @@
740	829
741	830	rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
742	831	rs->xfer = xfer;
743		- use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
	832	+ if (rs->poll) {
	833	+ xfer_mode = ROCKCHIP_SPI_POLL;
	834	+ } else {
	835	+ use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
	836	+ if (use_dma)
	837	+ xfer_mode = ROCKCHIP_SPI_DMA;
	838	+ else
	839	+ xfer_mode = ROCKCHIP_SPI_IRQ;
	840	+ }
744	841
745		- rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
	842	+ ret = rockchip_spi_config(rs, spi, xfer, xfer_mode, ctlr->slave);
	843	+ if (ret)
	844	+ return ret;
746	845
747		- if (use_dma)
748		- return rockchip_spi_prepare_dma(rs, ctlr, xfer);
	846	+ rs->tx = xfer->tx_buf;
	847	+ rs->rx = xfer->rx_buf;
749	848
750		- return rockchip_spi_prepare_irq(rs, ctlr, xfer);
	849	+ reinit_completion(&rs->xfer_done);
	850	+
	851	+ switch (xfer_mode) {
	852	+ case ROCKCHIP_SPI_POLL:
	853	+ ret = rockchip_spi_pio_transfer(rs, ctlr, xfer);
	854	+ break;
	855	+ case ROCKCHIP_SPI_DMA:
	856	+ ret = rockchip_spi_prepare_dma(rs, ctlr, xfer);
	857	+ break;
	858	+ default:
	859	+ ret = rockchip_spi_prepare_irq(rs, ctlr, xfer);
	860	+ }
	861	+
	862	+ if (ret > 0)
	863	+ ret = rockchip_spi_transfer_wait(ctlr, xfer);
	864	+
	865	+ return ret;
751	866	}
752	867
753	868	static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
..	..	@@ -766,10 +881,13 @@
766	881
767	882	static int rockchip_spi_setup(struct spi_device *spi)
768	883	{
769		-
770		- int ret = -EINVAL;
771	884	struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
772	885	u32 cr0;
	886	+
	887	+ if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
	888	+ dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
	889	+ return -EINVAL;
	890	+ }
773	891
774	892	pm_runtime_get_sync(rs->dev);
775	893
..	..	@@ -783,39 +901,7 @@
783	901
784	902	pm_runtime_put(rs->dev);
785	903
786		- if (spi->cs_gpio == -ENOENT)
787		- return 0;
788		-
789		- if (!rs->gpio_requested && gpio_is_valid(spi->cs_gpio)) {
790		- ret = gpio_request_one(spi->cs_gpio,
791		- (spi->mode & SPI_CS_HIGH) ?
792		- GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,
793		- dev_name(&spi->dev));
794		- if (ret)
795		- dev_err(&spi->dev, "can't request chipselect gpio %d\n",
796		- spi->cs_gpio);
797		- else
798		- rs->gpio_requested = true;
799		- } else {
800		- if (gpio_is_valid(spi->cs_gpio)) {
801		- int mode = ((spi->mode & SPI_CS_HIGH) ? 0 : 1);
802		-
803		- ret = gpio_direction_output(spi->cs_gpio, mode);
804		- if (ret)
805		- dev_err(&spi->dev, "chipselect gpio %d setup failed (%d)\n",
806		- spi->cs_gpio, ret);
807		- }
808		- }
809		-
810		- return ret;
811		-}
812		-
813		-static void rockchip_spi_cleanup(struct spi_device *spi)
814		-{
815		- struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
816		-
817		- if (rs->gpio_requested)
818		- gpio_free(spi->cs_gpio);
	904	+ return 0;
819	905	}
820	906
821	907	static int rockchip_spi_misc_open(struct inode inode, struct file filp)
..	..	@@ -879,7 +965,7 @@
879	965	struct spi_controller *ctlr;
880	966	struct resource *mem;
881	967	struct device_node *np = pdev->dev.of_node;
882		- u32 rsd_nsecs;
	968	+ u32 rsd_nsecs, num_cs, csm;
883	969	bool slave_mode;
884	970	struct pinctrl *pinctrl = NULL;
885	971	const struct rockchip_spi_quirks *quirks_cfg;
..	..	@@ -910,17 +996,26 @@
910	996	}
911	997	rs->base_addr_phy = mem->start;
912	998
913		- rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
	999	+ if (!has_acpi_companion(&pdev->dev))
	1000	+ rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
914	1001	if (IS_ERR(rs->apb_pclk)) {
915	1002	dev_err(&pdev->dev, "Failed to get apb_pclk\n");
916	1003	ret = PTR_ERR(rs->apb_pclk);
917	1004	goto err_put_ctlr;
918	1005	}
919	1006
920		- rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
	1007	+ if (!has_acpi_companion(&pdev->dev))
	1008	+ rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
921	1009	if (IS_ERR(rs->spiclk)) {
922	1010	dev_err(&pdev->dev, "Failed to get spi_pclk\n");
923	1011	ret = PTR_ERR(rs->spiclk);
	1012	+ goto err_put_ctlr;
	1013	+ }
	1014	+
	1015	+ rs->sclk_in = devm_clk_get_optional(&pdev->dev, "sclk_in");
	1016	+ if (IS_ERR(rs->sclk_in)) {
	1017	+ dev_err(&pdev->dev, "Failed to get sclk_in\n");
	1018	+ ret = PTR_ERR(rs->sclk_in);
924	1019	goto err_put_ctlr;
925	1020	}
926	1021
..	..	@@ -936,23 +1031,35 @@
936	1031	goto err_disable_apbclk;
937	1032	}
938	1033
	1034	+ ret = clk_prepare_enable(rs->sclk_in);
	1035	+ if (ret < 0) {
	1036	+ dev_err(&pdev->dev, "Failed to enable sclk_in\n");
	1037	+ goto err_disable_spiclk;
	1038	+ }
	1039	+
939	1040	spi_enable_chip(rs, false);
940	1041
941	1042	ret = platform_get_irq(pdev, 0);
942	1043	if (ret < 0)
943		- goto err_disable_spiclk;
	1044	+ goto err_disable_sclk_in;
944	1045
945	1046	ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
946	1047	IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
947	1048	if (ret)
948		- goto err_disable_spiclk;
	1049	+ goto err_disable_sclk_in;
949	1050
950	1051	rs->dev = &pdev->dev;
951		- rs->freq = clk_get_rate(rs->spiclk);
952		- rs->gpio_requested = false;
953	1052
954		- if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
955		- &rsd_nsecs)) {
	1053	+ rs->freq = clk_get_rate(rs->spiclk);
	1054	+ if (!rs->freq) {
	1055	+ ret = device_property_read_u32(&pdev->dev, "clock-frequency", &rs->freq);
	1056	+ if (ret) {
	1057	+ dev_warn(rs->dev, "Failed to get clock or clock-frequency property\n");
	1058	+ goto err_disable_sclk_in;
	1059	+ }
	1060	+ }
	1061	+
	1062	+ if (!device_property_read_u32(&pdev->dev, "rx-sample-delay-ns", &rsd_nsecs)) {
956	1063	/* rx sample delay is expressed in parent clock cycles (max 3) */
957	1064	u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
958	1065	1000000000 >> 8);
..	..	@@ -968,11 +1075,21 @@
968	1075	rs->rsd = rsd;
969	1076	}
970	1077
	1078	+ if (!device_property_read_u32(&pdev->dev, "csm", &csm)) {
	1079	+ if (csm > CR0_CSM_ONE) {
	1080	+ dev_warn(rs->dev, "The csm value %u exceeds the limit, clamping at %u\n",
	1081	+ csm, CR0_CSM_ONE);
	1082	+ csm = CR0_CSM_ONE;
	1083	+ }
	1084	+ rs->csm = csm;
	1085	+ }
	1086	+
	1087	+ rs->version = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
971	1088	rs->fifo_len = get_fifo_len(rs);
972	1089	if (!rs->fifo_len) {
973	1090	dev_err(&pdev->dev, "Failed to get fifo length\n");
974	1091	ret = -EINVAL;
975		- goto err_disable_spiclk;
	1092	+ goto err_disable_sclk_in;
976	1093	}
977	1094	quirks_cfg = device_get_match_data(&pdev->dev);
978	1095	if (quirks_cfg)
..	..	@@ -983,22 +1100,29 @@
983	1100
984	1101	ctlr->auto_runtime_pm = true;
985	1102	ctlr->bus_num = pdev->id;
986		- ctlr->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_LOOP \| SPI_LSB_FIRST \| SPI_CS_HIGH;
	1103	+ ctlr->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_LOOP \| SPI_LSB_FIRST;
987	1104	if (slave_mode) {
988	1105	ctlr->mode_bits \|= SPI_NO_CS;
989	1106	ctlr->slave_abort = rockchip_spi_slave_abort;
990	1107	} else {
991	1108	ctlr->flags = SPI_MASTER_GPIO_SS;
	1109	+ ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
	1110	+ /*
	1111	+ * rk spi0 has two native cs, spi1..5 one cs only
	1112	+ * if num-cs is missing in the dts, default to 1
	1113	+ */
	1114	+ if (device_property_read_u32(&pdev->dev, "num-cs", &num_cs))
	1115	+ num_cs = 1;
	1116	+ ctlr->num_chipselect = num_cs;
	1117	+ ctlr->use_gpio_descriptors = true;
992	1118	}
993		- ctlr->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM;
994	1119	ctlr->dev.of_node = pdev->dev.of_node;
995	1120	ctlr->bits_per_word_mask = SPI_BPW_MASK(16) \| SPI_BPW_MASK(8) \| SPI_BPW_MASK(4);
996	1121	ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
997	1122	ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
998	1123
999		- ctlr->set_cs = rockchip_spi_set_cs;
1000	1124	ctlr->setup = rockchip_spi_setup;
1001		- ctlr->cleanup = rockchip_spi_cleanup;
	1125	+ ctlr->set_cs = rockchip_spi_set_cs;
1002	1126	ctlr->transfer_one = rockchip_spi_transfer_one;
1003	1127	ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
1004	1128	ctlr->handle_err = rockchip_spi_handle_err;
..	..	@@ -1030,16 +1154,26 @@
1030	1154	ctlr->can_dma = rockchip_spi_can_dma;
1031	1155	}
1032	1156
1033		- switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
1034		- case ROCKCHIP_SPI_VER2_TYPE1:
	1157	+ rs->poll = device_property_read_bool(&pdev->dev, "rockchip,poll-only");
	1158	+ init_completion(&rs->xfer_done);
	1159	+ if (rs->poll && slave_mode) {
	1160	+ dev_err(rs->dev, "only support rockchip,poll-only property in master mode\n");
	1161	+ ret = -EINVAL;
	1162	+ goto err_free_dma_rx;
	1163	+ }
	1164	+
	1165	+ switch (rs->version) {
1035	1166	case ROCKCHIP_SPI_VER2_TYPE2:
1036		- if (ctlr->can_dma && slave_mode)
	1167	+ rs->cs_high_supported = true;
	1168	+ ctlr->mode_bits \|= SPI_CS_HIGH;
	1169	+ if (slave_mode)
1037	1170	rs->cs_inactive = true;
1038	1171	else
1039	1172	rs->cs_inactive = false;
1040	1173	break;
1041	1174	default:
1042	1175	rs->cs_inactive = false;
	1176	+ break;
1043	1177	}
1044	1178
1045	1179	pinctrl = devm_pinctrl_get(&pdev->dev);
..	..	@@ -1073,6 +1207,8 @@
1073	1207	dev_info(&pdev->dev, "register misc device %s\n", misc_name);
1074	1208	}
1075	1209
	1210	+ dev_info(rs->dev, "probed, poll=%d, rsd=%d\n", rs->poll, rs->rsd);
	1211	+
1076	1212	return 0;
1077	1213
1078	1214	err_free_dma_rx:
..	..	@@ -1083,6 +1219,8 @@
1083	1219	dma_release_channel(ctlr->dma_tx);
1084	1220	err_disable_pm_runtime:
1085	1221	pm_runtime_disable(&pdev->dev);
	1222	+err_disable_sclk_in:
	1223	+ clk_disable_unprepare(rs->sclk_in);
1086	1224	err_disable_spiclk:
1087	1225	clk_disable_unprepare(rs->spiclk);
1088	1226	err_disable_apbclk:
..	..	@@ -1103,6 +1241,7 @@
1103	1241
1104	1242	pm_runtime_get_sync(&pdev->dev);
1105	1243
	1244	+ clk_disable_unprepare(rs->sclk_in);
1106	1245	clk_disable_unprepare(rs->spiclk);
1107	1246	clk_disable_unprepare(rs->apb_pclk);
1108	1247
..	..	@@ -1119,51 +1258,6 @@
1119	1258
1120	1259	return 0;
1121	1260	}
1122		-
1123		-#ifdef CONFIG_PM_SLEEP
1124		-static int rockchip_spi_suspend(struct device *dev)
1125		-{
1126		- int ret;
1127		- struct spi_controller *ctlr = dev_get_drvdata(dev);
1128		- struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1129		-
1130		- ret = spi_controller_suspend(ctlr);
1131		- if (ret < 0)
1132		- return ret;
1133		-
1134		- clk_disable_unprepare(rs->spiclk);
1135		- clk_disable_unprepare(rs->apb_pclk);
1136		-
1137		- pinctrl_pm_select_sleep_state(dev);
1138		-
1139		- return 0;
1140		-}
1141		-
1142		-static int rockchip_spi_resume(struct device *dev)
1143		-{
1144		- int ret;
1145		- struct spi_controller *ctlr = dev_get_drvdata(dev);
1146		- struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1147		-
1148		- pinctrl_pm_select_default_state(dev);
1149		-
1150		- ret = clk_prepare_enable(rs->apb_pclk);
1151		- if (ret < 0)
1152		- return ret;
1153		-
1154		- ret = clk_prepare_enable(rs->spiclk);
1155		- if (ret < 0)
1156		- clk_disable_unprepare(rs->apb_pclk);
1157		-
1158		- ret = spi_controller_resume(ctlr);
1159		- if (ret < 0) {
1160		- clk_disable_unprepare(rs->spiclk);
1161		- clk_disable_unprepare(rs->apb_pclk);
1162		- }
1163		-
1164		- return 0;
1165		-}
1166		-#endif /* CONFIG_PM_SLEEP */
1167	1261
1168	1262	#ifdef CONFIG_PM
1169	1263	static int rockchip_spi_runtime_suspend(struct device *dev)
..	..	@@ -1195,6 +1289,46 @@
1195	1289	}
1196	1290	#endif /* CONFIG_PM */
1197	1291
	1292	+#ifdef CONFIG_PM_SLEEP
	1293	+static int rockchip_spi_suspend(struct device *dev)
	1294	+{
	1295	+ int ret;
	1296	+ struct spi_controller *ctlr = dev_get_drvdata(dev);
	1297	+
	1298	+ ret = spi_controller_suspend(ctlr);
	1299	+ if (ret < 0)
	1300	+ return ret;
	1301	+
	1302	+ /* Avoid redundant clock disable */
	1303	+ if (!pm_runtime_status_suspended(dev))
	1304	+ rockchip_spi_runtime_suspend(dev);
	1305	+
	1306	+ pinctrl_pm_select_sleep_state(dev);
	1307	+
	1308	+ return 0;
	1309	+}
	1310	+
	1311	+static int rockchip_spi_resume(struct device *dev)
	1312	+{
	1313	+ int ret;
	1314	+ struct spi_controller *ctlr = dev_get_drvdata(dev);
	1315	+
	1316	+ pinctrl_pm_select_default_state(dev);
	1317	+
	1318	+ if (!pm_runtime_status_suspended(dev)) {
	1319	+ ret = rockchip_spi_runtime_resume(dev);
	1320	+ if (ret < 0)
	1321	+ return ret;
	1322	+ }
	1323	+
	1324	+ ret = spi_controller_resume(ctlr);
	1325	+ if (ret < 0)
	1326	+ rockchip_spi_runtime_suspend(dev);
	1327	+
	1328	+ return 0;
	1329	+}
	1330	+#endif /* CONFIG_PM_SLEEP */
	1331	+
1198	1332	static const struct dev_pm_ops rockchip_spi_pm = {
1199	1333	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
1200	1334	SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
..	..	@@ -1210,15 +1344,18 @@
1210	1344	.compatible = "rockchip,px30-spi",
1211	1345	.data = &rockchip_spi_quirks_cfg,
1212	1346	},
1213		- { .compatible = "rockchip,rv1108-spi", },
1214		- { .compatible = "rockchip,rv1126-spi", },
1215	1347	{ .compatible = "rockchip,rk3036-spi", },
1216	1348	{ .compatible = "rockchip,rk3066-spi", },
1217	1349	{ .compatible = "rockchip,rk3188-spi", },
1218	1350	{ .compatible = "rockchip,rk3228-spi", },
1219	1351	{ .compatible = "rockchip,rk3288-spi", },
	1352	+ { .compatible = "rockchip,rk3308-spi", },
	1353	+ { .compatible = "rockchip,rk3328-spi", },
1220	1354	{ .compatible = "rockchip,rk3368-spi", },
1221	1355	{ .compatible = "rockchip,rk3399-spi", },
	1356	+ { .compatible = "rockchip,rv1106-spi", },
	1357	+ { .compatible = "rockchip,rv1108-spi", },
	1358	+ { .compatible = "rockchip,rv1126-spi", },
1222	1359	{ },
1223	1360	};
1224	1361	MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);