forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/spi/spi-rockchip.c
....@@ -1,22 +1,13 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
34  * Author: Addy Ke <addy.ke@rock-chips.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms and conditions of the GNU General Public License,
7
- * version 2, as published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
145  */
156 
7
+#include <linux/acpi.h>
168 #include <linux/clk.h>
179 #include <linux/delay.h>
1810 #include <linux/dmaengine.h>
19
-#include <linux/gpio.h>
2011 #include <linux/interrupt.h>
2112 #include <linux/miscdevice.h>
2213 #include <linux/module.h>
....@@ -197,6 +188,7 @@
197188 
198189 	struct clk *spiclk;
199190 	struct clk *apb_pclk;
191
+	struct clk *sclk_in;
200192 
201193 	void __iomem *regs;
202194 	dma_addr_t dma_addr_rx;
....@@ -227,8 +219,9 @@
227219 
228220 	struct pinctrl_state *high_speed_state;
229221 	bool slave_aborted;
230
-	bool gpio_requested;
231222 	bool cs_inactive; /* spi slave tansmition stop when cs inactive */
223
+	bool cs_high_supported; /* native CS supports active-high polarity */
224
+
232225 	struct spi_transfer *xfer; /* Store xfer temporarily */
233226 	phys_addr_t base_addr_phy;
234227 	struct miscdevice miscdev;
....@@ -296,12 +289,12 @@
296289 		/* Keep things powered as long as CS is asserted */
297290 		pm_runtime_get_sync(rs->dev);
298291 
299
-		if (gpio_is_valid(spi->cs_gpio))
292
+		if (spi->cs_gpiod)
300293 			ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
301294 		else
302295 			ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
303296 	} else {
304
-		if (gpio_is_valid(spi->cs_gpio))
297
+		if (spi->cs_gpiod)
305298 			ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
306299 		else
307300 			ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
....@@ -362,7 +355,7 @@
362355 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
363356 {
364357 	u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
365
-	u32 rx_left = rs->rx_left > words ? rs->rx_left - words : 0;
358
+	u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
366359 
367360 	/* the hardware doesn't allow us to change fifo threshold
368361 	 * level while spi is enabled, so instead make sure to leave
....@@ -528,7 +521,7 @@
528521 			.direction = DMA_MEM_TO_DEV,
529522 			.dst_addr = rs->dma_addr_tx,
530523 			.dst_addr_width = rs->n_bytes,
531
-			.dst_maxburst = 8,
524
+			.dst_maxburst = rs->fifo_len / 4,
532525 		};
533526 
534527 		dmaengine_slave_config(ctlr->dma_tx, &txconf);
....@@ -678,7 +671,9 @@
678671 		 * ctlr->bits_per_word_mask, so this shouldn't
679672 		 * happen
680673 		 */
681
-		unreachable();
674
+		dev_err(rs->dev, "unknown bits per word: %d\n",
675
+			xfer->bits_per_word);
676
+		return -EINVAL;
682677 	}
683678 
684679 	if (xfer_mode == ROCKCHIP_SPI_DMA) {
....@@ -886,10 +881,13 @@
886881 
887882 static int rockchip_spi_setup(struct spi_device *spi)
888883 {
889
-
890
-	int ret = -EINVAL;
891884 	struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
892885 	u32 cr0;
886
+
887
+	if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
888
+		dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
889
+		return -EINVAL;
890
+	}
893891 
894892 	pm_runtime_get_sync(rs->dev);
895893 
....@@ -903,39 +901,7 @@
903901 
904902 	pm_runtime_put(rs->dev);
905903 
906
-	if (spi->cs_gpio == -ENOENT)
907
-		return 0;
908
-
909
-	if (!rs->gpio_requested && gpio_is_valid(spi->cs_gpio)) {
910
-		ret = gpio_request_one(spi->cs_gpio,
911
-				       (spi->mode & SPI_CS_HIGH) ?
912
-				       GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,
913
-				       dev_name(&spi->dev));
914
-		if (ret)
915
-			dev_err(&spi->dev, "can't request chipselect gpio %d\n",
916
-				spi->cs_gpio);
917
-		else
918
-			rs->gpio_requested = true;
919
-	} else {
920
-		if (gpio_is_valid(spi->cs_gpio)) {
921
-			int mode = ((spi->mode & SPI_CS_HIGH) ? 0 : 1);
922
-
923
-			ret = gpio_direction_output(spi->cs_gpio, mode);
924
-			if (ret)
925
-				dev_err(&spi->dev, "chipselect gpio %d setup failed (%d)\n",
926
-					spi->cs_gpio, ret);
927
-		}
928
-	}
929
-
930
-	return ret;
931
-}
932
-
933
-static void rockchip_spi_cleanup(struct spi_device *spi)
934
-{
935
-	struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
936
-
937
-	if (rs->gpio_requested)
938
-		gpio_free(spi->cs_gpio);
904
+	return 0;
939905 }
940906 
941907 static int rockchip_spi_misc_open(struct inode *inode, struct file *filp)
....@@ -999,7 +965,7 @@
999965 	struct spi_controller *ctlr;
1000966 	struct resource *mem;
1001967 	struct device_node *np = pdev->dev.of_node;
1002
-	u32 rsd_nsecs, csm;
968
+	u32 rsd_nsecs, num_cs, csm;
1003969 	bool slave_mode;
1004970 	struct pinctrl *pinctrl = NULL;
1005971 	const struct rockchip_spi_quirks *quirks_cfg;
....@@ -1030,17 +996,26 @@
1030996 	}
1031997 	rs->base_addr_phy = mem->start;
1032998 
1033
-	rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
999
+	if (!has_acpi_companion(&pdev->dev))
1000
+		rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
10341001 	if (IS_ERR(rs->apb_pclk)) {
10351002 		dev_err(&pdev->dev, "Failed to get apb_pclk\n");
10361003 		ret = PTR_ERR(rs->apb_pclk);
10371004 		goto err_put_ctlr;
10381005 	}
10391006 
1040
-	rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
1007
+	if (!has_acpi_companion(&pdev->dev))
1008
+		rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
10411009 	if (IS_ERR(rs->spiclk)) {
10421010 		dev_err(&pdev->dev, "Failed to get spi_pclk\n");
10431011 		ret = PTR_ERR(rs->spiclk);
1012
+		goto err_put_ctlr;
1013
+	}
1014
+
1015
+	rs->sclk_in = devm_clk_get_optional(&pdev->dev, "sclk_in");
1016
+	if (IS_ERR(rs->sclk_in)) {
1017
+		dev_err(&pdev->dev, "Failed to get sclk_in\n");
1018
+		ret = PTR_ERR(rs->sclk_in);
10441019 		goto err_put_ctlr;
10451020 	}
10461021 
....@@ -1056,23 +1031,35 @@
10561031 		goto err_disable_apbclk;
10571032 	}
10581033 
1034
+	ret = clk_prepare_enable(rs->sclk_in);
1035
+	if (ret < 0) {
1036
+		dev_err(&pdev->dev, "Failed to enable sclk_in\n");
1037
+		goto err_disable_spiclk;
1038
+	}
1039
+
10591040 	spi_enable_chip(rs, false);
10601041 
10611042 	ret = platform_get_irq(pdev, 0);
10621043 	if (ret < 0)
1063
-		goto err_disable_spiclk;
1044
+		goto err_disable_sclk_in;
10641045 
10651046 	ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
10661047 			IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
10671048 	if (ret)
1068
-		goto err_disable_spiclk;
1049
+		goto err_disable_sclk_in;
10691050 
10701051 	rs->dev = &pdev->dev;
1071
-	rs->freq = clk_get_rate(rs->spiclk);
1072
-	rs->gpio_requested = false;
10731052 
1074
-	if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
1075
-				  &rsd_nsecs)) {
1053
+	rs->freq = clk_get_rate(rs->spiclk);
1054
+	if (!rs->freq) {
1055
+		ret = device_property_read_u32(&pdev->dev, "clock-frequency", &rs->freq);
1056
+		if (ret) {
1057
+			dev_warn(rs->dev, "Failed to get clock or clock-frequency property\n");
1058
+			goto err_disable_sclk_in;
1059
+		}
1060
+	}
1061
+
1062
+	if (!device_property_read_u32(&pdev->dev, "rx-sample-delay-ns", &rsd_nsecs)) {
10761063 		/* rx sample delay is expressed in parent clock cycles (max 3) */
10771064 		u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
10781065 				1000000000 >> 8);
....@@ -1102,7 +1089,7 @@
11021089 	if (!rs->fifo_len) {
11031090 		dev_err(&pdev->dev, "Failed to get fifo length\n");
11041091 		ret = -EINVAL;
1105
-		goto err_disable_spiclk;
1092
+		goto err_disable_sclk_in;
11061093 	}
11071094 	quirks_cfg = device_get_match_data(&pdev->dev);
11081095 	if (quirks_cfg)
....@@ -1113,22 +1100,29 @@
11131100 
11141101 	ctlr->auto_runtime_pm = true;
11151102 	ctlr->bus_num = pdev->id;
1116
-	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST | SPI_CS_HIGH;
1103
+	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
11171104 	if (slave_mode) {
11181105 		ctlr->mode_bits |= SPI_NO_CS;
11191106 		ctlr->slave_abort = rockchip_spi_slave_abort;
11201107 	} else {
11211108 		ctlr->flags = SPI_MASTER_GPIO_SS;
1109
+		ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
1110
+		/*
1111
+		 * rk spi0 has two native cs, spi1..5 one cs only
1112
+		 * if num-cs is missing in the dts, default to 1
1113
+		 */
1114
+		if (device_property_read_u32(&pdev->dev, "num-cs", &num_cs))
1115
+			num_cs = 1;
1116
+		ctlr->num_chipselect = num_cs;
1117
+		ctlr->use_gpio_descriptors = true;
11221118 	}
1123
-	ctlr->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM;
11241119 	ctlr->dev.of_node = pdev->dev.of_node;
11251120 	ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
11261121 	ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
11271122 	ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
11281123 
1129
-	ctlr->set_cs = rockchip_spi_set_cs;
11301124 	ctlr->setup = rockchip_spi_setup;
1131
-	ctlr->cleanup = rockchip_spi_cleanup;
1125
+	ctlr->set_cs = rockchip_spi_set_cs;
11321126 	ctlr->transfer_one = rockchip_spi_transfer_one;
11331127 	ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
11341128 	ctlr->handle_err = rockchip_spi_handle_err;
....@@ -1169,8 +1163,9 @@
11691163 	}
11701164 
11711165 	switch (rs->version) {
1172
-	case ROCKCHIP_SPI_VER2_TYPE1:
11731166 	case ROCKCHIP_SPI_VER2_TYPE2:
1167
+		rs->cs_high_supported = true;
1168
+		ctlr->mode_bits |= SPI_CS_HIGH;
11741169 		if (slave_mode)
11751170 			rs->cs_inactive = true;
11761171 		else
....@@ -1178,7 +1173,9 @@
11781173 		break;
11791174 	default:
11801175 		rs->cs_inactive = false;
1176
+		break;
11811177 	}
1178
+
11821179 	pinctrl = devm_pinctrl_get(&pdev->dev);
11831180 	if (!IS_ERR(pinctrl)) {
11841181 		rs->high_speed_state = pinctrl_lookup_state(pinctrl, "high_speed");
....@@ -1222,6 +1219,8 @@
12221219 		dma_release_channel(ctlr->dma_tx);
12231220 err_disable_pm_runtime:
12241221 	pm_runtime_disable(&pdev->dev);
1222
+err_disable_sclk_in:
1223
+	clk_disable_unprepare(rs->sclk_in);
12251224 err_disable_spiclk:
12261225 	clk_disable_unprepare(rs->spiclk);
12271226 err_disable_apbclk:
....@@ -1242,6 +1241,7 @@
12421241 
12431242 	pm_runtime_get_sync(&pdev->dev);
12441243 
1244
+	clk_disable_unprepare(rs->sclk_in);
12451245 	clk_disable_unprepare(rs->spiclk);
12461246 	clk_disable_unprepare(rs->apb_pclk);
12471247 
....@@ -1344,15 +1344,18 @@
13441344 		.compatible = "rockchip,px30-spi",
13451345 		.data = &rockchip_spi_quirks_cfg,
13461346 	},
1347
-	{ .compatible = "rockchip,rv1108-spi", },
1348
-	{ .compatible = "rockchip,rv1126-spi", },
13491347 	{ .compatible = "rockchip,rk3036-spi", },
13501348 	{ .compatible = "rockchip,rk3066-spi", },
13511349 	{ .compatible = "rockchip,rk3188-spi", },
13521350 	{ .compatible = "rockchip,rk3228-spi", },
13531351 	{ .compatible = "rockchip,rk3288-spi", },
1352
+	{ .compatible = "rockchip,rk3308-spi", },
1353
+	{ .compatible = "rockchip,rk3328-spi", },
13541354 	{ .compatible = "rockchip,rk3368-spi", },
13551355 	{ .compatible = "rockchip,rk3399-spi", },
1356
+	{ .compatible = "rockchip,rv1106-spi", },
1357
+	{ .compatible = "rockchip,rv1108-spi", },
1358
+	{ .compatible = "rockchip,rv1126-spi", },
13561359 	{ },
13571360 };
13581361 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);