~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,11 +1,8 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Rockchip Generic power domain support.
3	4	*
4	5	* Copyright (c) 2015 ROCKCHIP, Co. Ltd.
5		- *
6		- * This program is free software; you can redistribute it and/or modify
7		- * it under the terms of the GNU General Public License version 2 as
8		- * published by the Free Software Foundation.
9	6	*/
10	7
11	8	#include <linux/module.h>
..	..	@@ -30,7 +27,9 @@
30	27	#include <dt-bindings/power/rv1126-power.h>
31	28	#include <dt-bindings/power/rk1808-power.h>
32	29	#include <dt-bindings/power/rk3036-power.h>
	30	+#include <dt-bindings/power/rk3066-power.h>
33	31	#include <dt-bindings/power/rk3128-power.h>
	32	+#include <dt-bindings/power/rk3188-power.h>
34	33	#include <dt-bindings/power/rk3228-power.h>
35	34	#include <dt-bindings/power/rk3288-power.h>
36	35	#include <dt-bindings/power/rk3328-power.h>
..	..	@@ -38,9 +37,12 @@
38	37	#include <dt-bindings/power/rk3368-power.h>
39	38	#include <dt-bindings/power/rk3399-power.h>
40	39	#include <dt-bindings/power/rk3528-power.h>
	40	+#include <dt-bindings/power/rk3562-power.h>
41	41	#include <dt-bindings/power/rk3568-power.h>
	42	+#include <dt-bindings/power/rk3588-power.h>
42	43
43	44	struct rockchip_domain_info {
	45	+ const char *name;
44	46	int pwr_mask;
45	47	int status_mask;
46	48	int req_mask;
..	..	@@ -49,9 +51,15 @@
49	51	bool active_wakeup;
50	52	int pwr_w_mask;
51	53	int req_w_mask;
	54	+ int mem_status_mask;
	55	+ int repair_status_mask;
	56	+ int clk_ungate_mask;
	57	+ int clk_ungate_w_mask;
	58	+ int mem_num;
52	59	bool keepon_startup;
53	60	bool always_on;
54	61	u32 pwr_offset;
	62	+ u32 mem_offset;
55	63	u32 req_offset;
56	64	};
57	65
..	..	@@ -61,6 +69,12 @@
61	69	u32 req_offset;
62	70	u32 idle_offset;
63	71	u32 ack_offset;
	72	+ u32 mem_pwr_offset;
	73	+ u32 chain_status_offset;
	74	+ u32 mem_status_offset;
	75	+ u32 repair_status_offset;
	76	+ u32 clk_ungate_offset;
	77	+ u32 mem_sd_offset;
64	78
65	79	u32 core_pwrcnt_offset;
66	80	u32 gpu_pwrcnt_offset;
..	..	@@ -86,10 +100,12 @@
86	100	int num_qos;
87	101	struct regmap **qos_regmap;
88	102	u32 *qos_save_regs[MAX_QOS_REGS_NUM];
	103	+ bool *qos_is_need_init[MAX_QOS_REGS_NUM];
89	104	int num_clks;
90	105	struct clk_bulk_data *clks;
91	106	bool is_ignore_pwr;
92	107	bool is_qos_saved;
	108	+ bool is_qos_need_init;
93	109	struct regulator *supply;
94	110	};
95	111
..	..	@@ -109,6 +125,35 @@
109	125	MODULE_PARM_DESC(always_on,
110	126	"Always keep pm domains power on except for system suspend.");
111	127
	128	+#ifdef MODULE
	129	+static bool keepon_startup = true;
	130	+static void rockchip_pd_keepon_do_release(void);
	131	+
	132	+static int pd_param_set_keepon_startup(const char *val,
	133	+ const struct kernel_param *kp)
	134	+{
	135	+ int ret;
	136	+
	137	+ ret = param_set_bool(val, kp);
	138	+ if (ret)
	139	+ return ret;
	140	+
	141	+ if (!keepon_startup)
	142	+ rockchip_pd_keepon_do_release();
	143	+
	144	+ return 0;
	145	+}
	146	+
	147	+static const struct kernel_param_ops pd_keepon_startup_ops = {
	148	+ .set = pd_param_set_keepon_startup,
	149	+ .get = param_get_bool,
	150	+};
	151	+
	152	+module_param_cb(keepon_startup, &pd_keepon_startup_ops, &keepon_startup, 0644);
	153	+MODULE_PARM_DESC(keepon_startup,
	154	+ "Keep pm domains power on during system startup.");
	155	+#endif
	156	+
112	157	static void rockchip_pmu_lock(struct rockchip_pm_domain *pd)
113	158	{
114	159	mutex_lock(&pd->pmu->mutex);
..	..	@@ -123,8 +168,9 @@
123	168
124	169	#define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
125	170
126		-#define DOMAIN(pwr, status, req, idle, ack, wakeup, keepon) \
	171	+#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup, keepon) \
127	172	{ \
	173	+ .name = _name, \
128	174	.pwr_mask = (pwr), \
129	175	.status_mask = (status), \
130	176	.req_mask = (req), \
..	..	@@ -134,8 +180,9 @@
134	180	.keepon_startup = (keepon), \
135	181	}
136	182
137		-#define DOMAIN_M(pwr, status, req, idle, ack, wakeup, keepon) \
	183	+#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup, keepon) \
138	184	{ \
	185	+ .name = _name, \
139	186	.pwr_w_mask = (pwr) << 16, \
140	187	.pwr_mask = (pwr), \
141	188	.status_mask = (status), \
..	..	@@ -161,8 +208,26 @@
161	208	.keepon_startup = keepon, \
162	209	}
163	210
164		-#define DOMAIN_M_O(pwr, status, p_offset, req, idle, ack, r_offset, wakeup, keepon) \
	211	+#define DOMAIN_M_C_SD(_name, pwr, status, req, idle, ack, clk, mem, wakeup, keepon) \
165	212	{ \
	213	+ .name = _name, \
	214	+ .pwr_w_mask = (pwr) << 16, \
	215	+ .pwr_mask = (pwr), \
	216	+ .status_mask = (status), \
	217	+ .req_w_mask = (req) << 16, \
	218	+ .req_mask = (req), \
	219	+ .idle_mask = (idle), \
	220	+ .ack_mask = (ack), \
	221	+ .clk_ungate_mask = (clk), \
	222	+ .clk_ungate_w_mask = (clk) << 16, \
	223	+ .mem_num = (mem), \
	224	+ .active_wakeup = wakeup, \
	225	+ .keepon_startup = keepon, \
	226	+}
	227	+
	228	+#define DOMAIN_M_O(_name, pwr, status, p_offset, req, idle, ack, r_offset, wakeup, keepon) \
	229	+{ \
	230	+ .name = _name, \
166	231	.pwr_w_mask = (pwr) << 16, \
167	232	.pwr_mask = (pwr), \
168	233	.status_mask = (status), \
..	..	@@ -176,8 +241,28 @@
176	241	.req_offset = r_offset, \
177	242	}
178	243
179		-#define DOMAIN_RK3036(req, ack, idle, wakeup) \
	244	+#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup, keepon) \
180	245	{ \
	246	+ .name = _name, \
	247	+ .pwr_offset = p_offset, \
	248	+ .pwr_w_mask = (pwr) << 16, \
	249	+ .pwr_mask = (pwr), \
	250	+ .status_mask = (status), \
	251	+ .mem_offset = m_offset, \
	252	+ .mem_status_mask = (m_status), \
	253	+ .repair_status_mask = (r_status), \
	254	+ .req_offset = r_offset, \
	255	+ .req_w_mask = (req) << 16, \
	256	+ .req_mask = (req), \
	257	+ .idle_mask = (idle), \
	258	+ .ack_mask = (ack), \
	259	+ .active_wakeup = wakeup, \
	260	+ .keepon_startup = keepon, \
	261	+}
	262	+
	263	+#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
	264	+{ \
	265	+ .name = _name, \
181	266	.req_mask = (req), \
182	267	.req_w_mask = (req) << 16, \
183	268	.ack_mask = (ack), \
..	..	@@ -185,50 +270,62 @@
185	270	.active_wakeup = wakeup, \
186	271	}
187	272
188		-#define DOMAIN_PX30(pwr, status, req, wakeup) \
189		- DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup, false)
	273	+#define DOMAIN_PX30(name, pwr, status, req, wakeup) \
	274	+ DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup, false)
190	275
191		-#define DOMAIN_PX30_PROTECT(pwr, status, req, wakeup) \
192		- DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup, true)
	276	+#define DOMAIN_PX30_PROTECT(name, pwr, status, req, wakeup) \
	277	+ DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup, true)
193	278
194		-#define DOMAIN_RV1126(pwr, req, idle, wakeup) \
195		- DOMAIN_M(pwr, pwr, req, idle, idle, wakeup, false)
	279	+#define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \
	280	+ DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup, false)
196	281
197		-#define DOMAIN_RV1126_PROTECT(pwr, req, idle, wakeup) \
198		- DOMAIN_M(pwr, pwr, req, idle, idle, wakeup, true)
	282	+#define DOMAIN_RV1126_PROTECT(name, pwr, req, idle, wakeup) \
	283	+ DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup, true)
199	284
200		-#define DOMAIN_RV1126_O(pwr, req, idle, r_offset, wakeup) \
201		- DOMAIN_M_O(pwr, pwr, 0, req, idle, idle, r_offset, wakeup, false)
	285	+#define DOMAIN_RV1126_O(name, pwr, req, idle, r_offset, wakeup) \
	286	+ DOMAIN_M_O(name, pwr, pwr, 0, req, idle, idle, r_offset, wakeup, false)
202	287
203		-#define DOMAIN_RK3288(pwr, status, req, wakeup) \
204		- DOMAIN(pwr, status, req, req, (req) << 16, wakeup, false)
	288	+#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
	289	+ DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup, false)
205	290
206		-#define DOMAIN_RK3288_PROTECT(pwr, status, req, wakeup) \
207		- DOMAIN(pwr, status, req, req, (req) << 16, wakeup, true)
	291	+#define DOMAIN_RK3288_PROTECT(name, pwr, status, req, wakeup) \
	292	+ DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup, true)
208	293
209		-#define DOMAIN_RK3328(pwr, status, req, wakeup) \
210		- DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup, false)
	294	+#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \
	295	+ DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup, false)
211	296
212		-#define DOMAIN_RK3368(pwr, status, req, wakeup) \
213		- DOMAIN(pwr, status, req, (req) << 16, req, wakeup, false)
	297	+#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \
	298	+ DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup, false)
214	299
215		-#define DOMAIN_RK3368_PROTECT(pwr, status, req, wakeup) \
216		- DOMAIN(pwr, status, req, (req) << 16, req, wakeup, true)
	300	+#define DOMAIN_RK3368_PROTECT(name, pwr, status, req, wakeup) \
	301	+ DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup, true)
217	302
218		-#define DOMAIN_RK3399(pwr, status, req, wakeup) \
219		- DOMAIN(pwr, status, req, req, req, wakeup, false)
	303	+#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
	304	+ DOMAIN(name, pwr, status, req, req, req, wakeup, false)
220	305
221		-#define DOMAIN_RK3399_PROTECT(pwr, status, req, wakeup) \
222		- DOMAIN(pwr, status, req, req, req, wakeup, true)
	306	+#define DOMAIN_RK3399_PROTECT(name, pwr, status, req, wakeup) \
	307	+ DOMAIN(name, pwr, status, req, req, req, wakeup, true)
223	308
224	309	#define DOMAIN_RK3528(pwr, req, always, wakeup) \
225	310	DOMAIN_M_A(pwr, pwr, req, req, req, always, wakeup, false)
226	311
227		-#define DOMAIN_RK3568(pwr, req, wakeup) \
228		- DOMAIN_M(pwr, pwr, req, req, req, wakeup, false)
	312	+#define DOMAIN_RK3562(name, pwr, req, mem, wakeup) \
	313	+ DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, false)
229	314
230		-#define DOMAIN_RK3568_PROTECT(pwr, req, wakeup) \
231		- DOMAIN_M(pwr, pwr, req, req, req, wakeup, true)
	315	+#define DOMAIN_RK3562_PROTECT(name, pwr, req, mem, wakeup) \
	316	+ DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, true)
	317	+
	318	+#define DOMAIN_RK3568(name, pwr, req, wakeup) \
	319	+ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, false)
	320	+
	321	+#define DOMAIN_RK3568_PROTECT(name, pwr, req, wakeup) \
	322	+ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, true)
	323	+
	324	+#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \
	325	+ DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, false)
	326	+
	327	+#define DOMAIN_RK3588_P(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \
	328	+ DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, true)
232	329
233	330	static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
234	331	{
..	..	@@ -246,6 +343,42 @@
246	343
247	344	regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
248	345	return val;
	346	+}
	347	+
	348	+static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate)
	349	+{
	350	+ const struct rockchip_domain_info *pd_info = pd->info;
	351	+ struct rockchip_pmu *pmu = pd->pmu;
	352	+ unsigned int val;
	353	+
	354	+ if (!pd_info->clk_ungate_mask)
	355	+ return 0;
	356	+ if (!pmu->info->clk_ungate_offset)
	357	+ return 0;
	358	+
	359	+ val = ungate ? (pd_info->clk_ungate_mask \| pd_info->clk_ungate_w_mask) :
	360	+ pd_info->clk_ungate_w_mask;
	361	+ regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val);
	362	+
	363	+ return 0;
	364	+}
	365	+
	366	+static int rockchip_pmu_mem_shut_down(struct rockchip_pm_domain *pd, bool sd)
	367	+{
	368	+ const struct rockchip_domain_info *pd_info = pd->info;
	369	+ struct rockchip_pmu *pmu = pd->pmu;
	370	+ unsigned int i;
	371	+
	372	+ if (!pd_info->mem_num)
	373	+ return 0;
	374	+ if (!pmu->info->mem_sd_offset)
	375	+ return 0;
	376	+
	377	+ for (i = 0; i < pd_info->mem_num; i++)
	378	+ regmap_write(pmu->regmap, pmu->info->mem_sd_offset,
	379	+ (sd << i) \| (1 << (i + 16)));
	380	+
	381	+ return 0;
249	382	}
250	383
251	384	static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
..	..	@@ -375,6 +508,45 @@
375	508	return 0;
376	509	}
377	510
	511	+static void rockchip_pmu_init_qos(struct rockchip_pm_domain *pd)
	512	+{
	513	+ int i;
	514	+
	515	+ if (!pd->is_qos_need_init)
	516	+ return;
	517	+
	518	+ for (i = 0; i < pd->num_qos; i++) {
	519	+ if (pd->qos_is_need_init[0][i])
	520	+ regmap_write(pd->qos_regmap[i],
	521	+ QOS_PRIORITY,
	522	+ pd->qos_save_regs[0][i]);
	523	+
	524	+ if (pd->qos_is_need_init[1][i])
	525	+ regmap_write(pd->qos_regmap[i],
	526	+ QOS_MODE,
	527	+ pd->qos_save_regs[1][i]);
	528	+
	529	+ if (pd->qos_is_need_init[2][i])
	530	+ regmap_write(pd->qos_regmap[i],
	531	+ QOS_BANDWIDTH,
	532	+ pd->qos_save_regs[2][i]);
	533	+
	534	+ if (pd->qos_is_need_init[3][i])
	535	+ regmap_write(pd->qos_regmap[i],
	536	+ QOS_SATURATION,
	537	+ pd->qos_save_regs[3][i]);
	538	+
	539	+ if (pd->qos_is_need_init[4][i])
	540	+ regmap_write(pd->qos_regmap[i],
	541	+ QOS_EXTCONTROL,
	542	+ pd->qos_save_regs[4][i]);
	543	+ }
	544	+
	545	+ kfree(pd->qos_is_need_init[0]);
	546	+ pd->qos_is_need_init[0] = NULL;
	547	+ pd->is_qos_need_init = false;
	548	+}
	549	+
378	550	int rockchip_save_qos(struct device *dev)
379	551	{
380	552	struct generic_pm_domain *genpd;
..	..	@@ -421,10 +593,88 @@
421	593	}
422	594	EXPORT_SYMBOL(rockchip_restore_qos);
423	595
	596	+static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
	597	+{
	598	+ struct rockchip_pmu *pmu = pd->pmu;
	599	+ unsigned int val;
	600	+
	601	+ regmap_read(pmu->regmap,
	602	+ pmu->info->mem_status_offset + pd->info->mem_offset, &val);
	603	+
	604	+ /* 1'b0: power on, 1'b1: power off */
	605	+ return !(val & pd->info->mem_status_mask);
	606	+}
	607	+
	608	+static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
	609	+{
	610	+ struct rockchip_pmu *pmu = pd->pmu;
	611	+ unsigned int val;
	612	+
	613	+ regmap_read(pmu->regmap,
	614	+ pmu->info->chain_status_offset + pd->info->mem_offset, &val);
	615	+
	616	+ /* 1'b1: power on, 1'b0: power off */
	617	+ return val & pd->info->mem_status_mask;
	618	+}
	619	+
	620	+static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
	621	+{
	622	+ struct rockchip_pmu *pmu = pd->pmu;
	623	+ struct generic_pm_domain *genpd = &pd->genpd;
	624	+ bool is_on;
	625	+ int ret = 0;
	626	+
	627	+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
	628	+ is_on == true, 0, 10000);
	629	+ if (ret) {
	630	+ dev_err(pmu->dev,
	631	+ "failed to get chain status '%s', target_on=1, val=%d\n",
	632	+ genpd->name, is_on);
	633	+ goto error;
	634	+ }
	635	+
	636	+ udelay(60);
	637	+
	638	+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
	639	+ (pd->info->pwr_mask \| pd->info->pwr_w_mask));
	640	+ dsb(sy);
	641	+
	642	+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
	643	+ is_on == false, 0, 10000);
	644	+ if (ret) {
	645	+ dev_err(pmu->dev,
	646	+ "failed to get mem status '%s', target_on=0, val=%d\n",
	647	+ genpd->name, is_on);
	648	+ goto error;
	649	+ }
	650	+
	651	+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
	652	+ pd->info->pwr_w_mask);
	653	+ dsb(sy);
	654	+
	655	+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
	656	+ is_on == true, 0, 10000);
	657	+ if (ret) {
	658	+ dev_err(pmu->dev,
	659	+ "failed to get mem status '%s', target_on=1, val=%d\n",
	660	+ genpd->name, is_on);
	661	+ }
	662	+
	663	+error:
	664	+
	665	+ return ret;
	666	+}
	667	+
424	668	static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
425	669	{
426	670	struct rockchip_pmu *pmu = pd->pmu;
427	671	unsigned int val;
	672	+
	673	+ if (pd->info->repair_status_mask) {
	674	+ regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);
	675	+ /* 1'b1: power on, 1'b0: power off */
	676	+ return val & pd->info->repair_status_mask;
	677	+ }
428	678
429	679	/* check idle status for idle-only domains */
430	680	if (pd->info->status_mask == 0)
..	..	@@ -442,15 +692,19 @@
442	692	struct rockchip_pmu *pmu = pd->pmu;
443	693	struct generic_pm_domain *genpd = &pd->genpd;
444	694	u32 pd_pwr_offset = 0;
445		- bool is_on;
	695	+ bool is_on, is_mem_on = false;
446	696	int ret = 0;
	697	+
	698	+ if (pd->info->pwr_mask == 0)
	699	+ return 0;
	700	+
	701	+ if (on && pd->info->mem_status_mask)
	702	+ is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
447	703
448	704	if (pd->info->pwr_offset)
449	705	pd_pwr_offset = pd->info->pwr_offset;
450	706
451		- if (pd->info->pwr_mask == 0)
452		- return 0;
453		- else if (pd->info->pwr_w_mask)
	707	+ if (pd->info->pwr_w_mask)
454	708	regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
455	709	on ? pd->info->pwr_w_mask :
456	710	(pd->info->pwr_mask \| pd->info->pwr_w_mask));
..	..	@@ -460,6 +714,12 @@
460	714	on ? 0 : -1U);
461	715
462	716	dsb(sy);
	717	+
	718	+ if (is_mem_on) {
	719	+ ret = rockchip_pmu_domain_mem_reset(pd);
	720	+ if (ret)
	721	+ goto error;
	722	+ }
463	723
464	724	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
465	725	is_on == on, 0, 10000);
..	..	@@ -485,8 +745,8 @@
485	745	if (pm_domain_always_on && !power_on)
486	746	return 0;
487	747
488		- if (!power_on && (soc_is_px30s())) {
489		- if (genpd->name && !strcmp(genpd->name, "pd_gpu"))
	748	+ if (!power_on && soc_is_px30s()) {
	749	+ if (genpd->name && !strcmp(genpd->name, "gpu"))
490	750	return 0;
491	751	}
492	752
..	..	@@ -514,6 +774,7 @@
514	774	rockchip_pmu_unlock(pd);
515	775	return ret;
516	776	}
	777	+ rockchip_pmu_ungate_clk(pd, true);
517	778
518	779	if (!power_on) {
519	780	rockchip_pmu_save_qos(pd);
..	..	@@ -526,6 +787,7 @@
526	787	genpd->name);
527	788	goto out;
528	789	}
	790	+ rockchip_pmu_mem_shut_down(pd, true);
529	791	}
530	792
531	793	ret = rockchip_do_pmu_set_power_domain(pd, power_on);
..	..	@@ -536,6 +798,7 @@
536	798	}
537	799
538	800	if (power_on) {
	801	+ rockchip_pmu_mem_shut_down(pd, false);
539	802	/* if powering up, leave idle mode */
540	803	ret = rockchip_pmu_set_idle_request(pd, false);
541	804	if (ret) {
..	..	@@ -546,9 +809,12 @@
546	809
547	810	if (pd->is_qos_saved)
548	811	rockchip_pmu_restore_qos(pd);
	812	+ if (pd->is_qos_need_init)
	813	+ rockchip_pmu_init_qos(pd);
549	814	}
550	815
551	816	out:
	817	+ rockchip_pmu_ungate_clk(pd, false);
552	818	clk_bulk_disable(pd->num_clks, pd->clks);
553	819
554	820	if (!power_on && !IS_ERR(pd->supply))
..	..	@@ -676,44 +942,26 @@
676	942	pm_clk_destroy(dev);
677	943	}
678	944
679		-static void rockchip_pd_qos_init(struct rockchip_pm_domain *pd,
680		- bool **qos_is_need_init)
	945	+static void rockchip_pd_qos_init(struct rockchip_pm_domain *pd)
681	946	{
682		- int i, is_pd_on;
	947	+ int is_pd_on, ret = 0;
683	948
684		- is_pd_on = rockchip_pmu_domain_is_on(pd);
685		- if (!is_pd_on)
686		- rockchip_pd_power(pd, true);
687		-
688		- for (i = 0; i < pd->num_qos; i++) {
689		- if (qos_is_need_init[0][i])
690		- regmap_write(pd->qos_regmap[i],
691		- QOS_PRIORITY,
692		- pd->qos_save_regs[0][i]);
693		-
694		- if (qos_is_need_init[1][i])
695		- regmap_write(pd->qos_regmap[i],
696		- QOS_MODE,
697		- pd->qos_save_regs[1][i]);
698		-
699		- if (qos_is_need_init[2][i])
700		- regmap_write(pd->qos_regmap[i],
701		- QOS_BANDWIDTH,
702		- pd->qos_save_regs[2][i]);
703		-
704		- if (qos_is_need_init[3][i])
705		- regmap_write(pd->qos_regmap[i],
706		- QOS_SATURATION,
707		- pd->qos_save_regs[3][i]);
708		-
709		- if (qos_is_need_init[4][i])
710		- regmap_write(pd->qos_regmap[i],
711		- QOS_EXTCONTROL,
712		- pd->qos_save_regs[4][i]);
	949	+ if (!pd->is_qos_need_init) {
	950	+ kfree(pd->qos_is_need_init[0]);
	951	+ pd->qos_is_need_init[0] = NULL;
	952	+ return;
713	953	}
714	954
715		- if (!is_pd_on)
716		- rockchip_pd_power(pd, false);
	955	+ is_pd_on = rockchip_pmu_domain_is_on(pd);
	956	+ if (is_pd_on) {
	957	+ ret = clk_bulk_enable(pd->num_clks, pd->clks);
	958	+ if (ret < 0) {
	959	+ dev_err(pd->pmu->dev, "failed to enable clocks\n");
	960	+ return;
	961	+ }
	962	+ rockchip_pmu_init_qos(pd);
	963	+ clk_bulk_disable(pd->num_clks, pd->clks);
	964	+ }
717	965	}
718	966
719	967	static int rockchip_pd_add_alwasy_on_flag(struct rockchip_pm_domain *pd)
..	..	@@ -746,27 +994,27 @@
746	994	int i, j;
747	995	u32 id, val;
748	996	int error;
749		- bool *qos_is_need_init[MAX_QOS_REGS_NUM] = { NULL };
750		- bool is_qos_need_init = false;
751	997
752	998	error = of_property_read_u32(node, "reg", &id);
753	999	if (error) {
754	1000	dev_err(pmu->dev,
755		- "%s: failed to retrieve domain id (reg): %d\n",
756		- node->name, error);
	1001	+ "%pOFn: failed to retrieve domain id (reg): %d\n",
	1002	+ node, error);
757	1003	return -EINVAL;
758	1004	}
759	1005
760	1006	if (id >= pmu->info->num_domains) {
761		- dev_err(pmu->dev, "%s: invalid domain id %d\n",
762		- node->name, id);
	1007	+ dev_err(pmu->dev, "%pOFn: invalid domain id %d\n",
	1008	+ node, id);
763	1009	return -EINVAL;
764	1010	}
	1011	+ if (pmu->genpd_data.domains[id])
	1012	+ return 0;
765	1013
766	1014	pd_info = &pmu->info->domain_info[id];
767	1015	if (!pd_info) {
768		- dev_err(pmu->dev, "%s: undefined domain id %d\n",
769		- node->name, id);
	1016	+ dev_err(pmu->dev, "%pOFn: undefined domain id %d\n",
	1017	+ node, id);
770	1018	return -EINVAL;
771	1019	}
772	1020
..	..	@@ -786,8 +1034,8 @@
786	1034	if (!pd->clks)
787	1035	return -ENOMEM;
788	1036	} else {
789		- dev_dbg(pmu->dev, "%s: doesn't have clocks: %d\n",
790		- node->name, pd->num_clks);
	1037	+ dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n",
	1038	+ node, pd->num_clks);
791	1039	pd->num_clks = 0;
792	1040	}
793	1041
..	..	@@ -796,8 +1044,8 @@
796	1044	if (IS_ERR(pd->clks[i].clk)) {
797	1045	error = PTR_ERR(pd->clks[i].clk);
798	1046	dev_err(pmu->dev,
799		- "%s: failed to get clk at index %d: %d\n",
800		- node->name, i, error);
	1047	+ "%pOFn: failed to get clk at index %d: %d\n",
	1048	+ node, i, error);
801	1049	return error;
802	1050	}
803	1051	}
..	..	@@ -833,18 +1081,19 @@
833	1081	error = -ENOMEM;
834	1082	goto err_unprepare_clocks;
835	1083	}
836		- qos_is_need_init[0] = kzalloc(sizeof(bool) *
837		- MAX_QOS_REGS_NUM *
838		- pd->num_qos,
839		- GFP_KERNEL);
840		- if (!qos_is_need_init[0]) {
	1084	+ pd->qos_is_need_init[0] = kzalloc(sizeof(bool) *
	1085	+ MAX_QOS_REGS_NUM *
	1086	+ pd->num_qos,
	1087	+ GFP_KERNEL);
	1088	+ if (!pd->qos_is_need_init[0]) {
841	1089	error = -ENOMEM;
842	1090	goto err_unprepare_clocks;
843	1091	}
844	1092	for (i = 1; i < MAX_QOS_REGS_NUM; i++) {
845	1093	pd->qos_save_regs[i] = pd->qos_save_regs[i - 1] +
846	1094	num_qos;
847		- qos_is_need_init[i] = qos_is_need_init[i - 1] + num_qos;
	1095	+ pd->qos_is_need_init[i] = pd->qos_is_need_init[i - 1] +
	1096	+ num_qos;
848	1097	}
849	1098
850	1099	for (j = 0; j < num_qos; j++) {
..	..	@@ -865,71 +1114,68 @@
865	1114	"priority-init",
866	1115	&val)) {
867	1116	pd->qos_save_regs[0][j] = val;
868		- qos_is_need_init[0][j] = true;
869		- is_qos_need_init = true;
	1117	+ pd->qos_is_need_init[0][j] = true;
	1118	+ pd->is_qos_need_init = true;
870	1119	}
871	1120
872	1121	if (!of_property_read_u32(qos_node,
873	1122	"mode-init",
874	1123	&val)) {
875	1124	pd->qos_save_regs[1][j] = val;
876		- qos_is_need_init[1][j] = true;
877		- is_qos_need_init = true;
	1125	+ pd->qos_is_need_init[1][j] = true;
	1126	+ pd->is_qos_need_init = true;
878	1127	}
879	1128
880	1129	if (!of_property_read_u32(qos_node,
881	1130	"bandwidth-init",
882	1131	&val)) {
883	1132	pd->qos_save_regs[2][j] = val;
884		- qos_is_need_init[2][j] = true;
885		- is_qos_need_init = true;
	1133	+ pd->qos_is_need_init[2][j] = true;
	1134	+ pd->is_qos_need_init = true;
886	1135	}
887	1136
888	1137	if (!of_property_read_u32(qos_node,
889	1138	"saturation-init",
890	1139	&val)) {
891	1140	pd->qos_save_regs[3][j] = val;
892		- qos_is_need_init[3][j] = true;
893		- is_qos_need_init = true;
	1141	+ pd->qos_is_need_init[3][j] = true;
	1142	+ pd->is_qos_need_init = true;
894	1143	}
895	1144
896	1145	if (!of_property_read_u32(qos_node,
897	1146	"extcontrol-init",
898	1147	&val)) {
899	1148	pd->qos_save_regs[4][j] = val;
900		- qos_is_need_init[4][j] = true;
901		- is_qos_need_init = true;
	1149	+ pd->qos_is_need_init[4][j] = true;
	1150	+ pd->is_qos_need_init = true;
902	1151	}
903	1152
904	1153	num_qos_reg++;
905	1154	}
906	1155	of_node_put(qos_node);
907		- if (num_qos_reg > pd->num_qos)
	1156	+ if (num_qos_reg > pd->num_qos) {
	1157	+ error = -EINVAL;
908	1158	goto err_unprepare_clocks;
	1159	+ }
909	1160	}
910	1161	}
911	1162
912		- pd->genpd.name = node->name;
	1163	+ if (pd->info->name)
	1164	+ pd->genpd.name = pd->info->name;
	1165	+ else
	1166	+ pd->genpd.name = kbasename(node->full_name);
913	1167	pd->genpd.power_off = rockchip_pd_power_off;
914	1168	pd->genpd.power_on = rockchip_pd_power_on;
915	1169	pd->genpd.attach_dev = rockchip_pd_attach_dev;
916	1170	pd->genpd.detach_dev = rockchip_pd_detach_dev;
917	1171	if (pd_info->active_wakeup)
918	1172	pd->genpd.flags \|= GENPD_FLAG_ACTIVE_WAKEUP;
919		- if (pd_info->always_on) {
920		- if (rockchip_pd_add_alwasy_on_flag(pd))
	1173	+ if (pd_info->always_on \|\| pd_info->keepon_startup) {
	1174	+ error = rockchip_pd_add_alwasy_on_flag(pd);
	1175	+ if (error)
921	1176	goto err_unprepare_clocks;
922	1177	}
923		-#ifndef MODULE
924		- if (pd_info->keepon_startup) {
925		- if (rockchip_pd_add_alwasy_on_flag(pd))
926		- goto err_unprepare_clocks;
927		- }
928		-#endif
929		- if (is_qos_need_init)
930		- rockchip_pd_qos_init(pd, &qos_is_need_init[0]);
931		-
932		- kfree(qos_is_need_init[0]);
	1178	+ rockchip_pd_qos_init(pd);
933	1179
934	1180	pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));
935	1181
..	..	@@ -937,7 +1183,8 @@
937	1183	return 0;
938	1184
939	1185	err_unprepare_clocks:
940		- kfree(qos_is_need_init[0]);
	1186	+ kfree(pd->qos_is_need_init[0]);
	1187	+ pd->qos_is_need_init[0] = NULL;
941	1188	clk_bulk_unprepare(pd->num_clks, pd->clks);
942	1189	err_put_clocks:
943	1190	clk_bulk_put(pd->num_clks, pd->clks);
..	..	@@ -1009,24 +1256,24 @@
1009	1256	error = of_property_read_u32(parent, "reg", &idx);
1010	1257	if (error) {
1011	1258	dev_err(pmu->dev,
1012		- "%s: failed to retrieve domain id (reg): %d\n",
1013		- parent->name, error);
	1259	+ "%pOFn: failed to retrieve domain id (reg): %d\n",
	1260	+ parent, error);
1014	1261	goto err_out;
1015	1262	}
1016	1263	parent_domain = pmu->genpd_data.domains[idx];
1017	1264
1018	1265	error = rockchip_pm_add_one_domain(pmu, np);
1019	1266	if (error) {
1020		- dev_err(pmu->dev, "failed to handle node %s: %d\n",
1021		- np->name, error);
	1267	+ dev_err(pmu->dev, "failed to handle node %pOFn: %d\n",
	1268	+ np, error);
1022	1269	goto err_out;
1023	1270	}
1024	1271
1025	1272	error = of_property_read_u32(np, "reg", &idx);
1026	1273	if (error) {
1027	1274	dev_err(pmu->dev,
1028		- "%s: failed to retrieve domain id (reg): %d\n",
1029		- np->name, error);
	1275	+ "%pOFn: failed to retrieve domain id (reg): %d\n",
	1276	+ np, error);
1030	1277	goto err_out;
1031	1278	}
1032	1279	child_domain = pmu->genpd_data.domains[idx];
..	..	@@ -1062,37 +1309,14 @@
1062	1309	return error;
1063	1310	}
1064	1311
1065		-#ifndef MODULE
1066		-static void rockchip_pd_keepon_do_release(struct generic_pm_domain *genpd,
1067		- struct rockchip_pm_domain *pd)
1068		-{
1069		- struct pm_domain_data *pm_data;
1070		- int enable_count;
1071		-
1072		- pd->genpd.flags &= (~GENPD_FLAG_ALWAYS_ON);
1073		- list_for_each_entry(pm_data, &genpd->dev_list, list_node) {
1074		- if (!atomic_read(&pm_data->dev->power.usage_count)) {
1075		- enable_count = 0;
1076		- if (!pm_runtime_enabled(pm_data->dev)) {
1077		- pm_runtime_enable(pm_data->dev);
1078		- enable_count = 1;
1079		- }
1080		- pm_runtime_get_sync(pm_data->dev);
1081		- pm_runtime_put_sync(pm_data->dev);
1082		- if (enable_count)
1083		- pm_runtime_disable(pm_data->dev);
1084		- }
1085		- }
1086		-}
1087		-
1088		-static int __init rockchip_pd_keepon_release(void)
	1312	+static void rockchip_pd_keepon_do_release(void)
1089	1313	{
1090	1314	struct generic_pm_domain *genpd;
1091	1315	struct rockchip_pm_domain *pd;
1092	1316	int i;
1093	1317
1094	1318	if (!g_pmu)
1095		- return 0;
	1319	+ return;
1096	1320
1097	1321	for (i = 0; i < g_pmu->genpd_data.num_domains; i++) {
1098	1322	genpd = g_pmu->genpd_data.domains[i];
..	..	@@ -1100,10 +1324,21 @@
1100	1324	pd = to_rockchip_pd(genpd);
1101	1325	if (pd->info->always_on)
1102	1326	continue;
1103		- if (pd->info->keepon_startup)
1104		- rockchip_pd_keepon_do_release(genpd, pd);
	1327	+ if (!pd->info->keepon_startup)
	1328	+ continue;
	1329	+ if (!(genpd->flags & GENPD_FLAG_ALWAYS_ON))
	1330	+ continue;
	1331	+ genpd->flags &= (~GENPD_FLAG_ALWAYS_ON);
	1332	+ queue_work(pm_wq, &genpd->power_off_work);
1105	1333	}
1106	1334	}
	1335	+}
	1336	+
	1337	+#ifndef MODULE
	1338	+static int __init rockchip_pd_keepon_release(void)
	1339	+{
	1340	+ rockchip_pd_keepon_do_release();
	1341	+
1107	1342	return 0;
1108	1343	}
1109	1344	late_initcall_sync(rockchip_pd_keepon_release);
..	..	@@ -1111,14 +1346,32 @@
1111	1346
1112	1347	static void __iomem *pd_base;
1113	1348
	1349	+static void dump_offset(const char *name, u32 offset)
	1350	+{
	1351	+ if (!offset)
	1352	+ return;
	1353	+
	1354	+ pr_warn("%-9s 0x%04x: ", name, offset);
	1355	+ print_hex_dump(KERN_CONT, "", DUMP_PREFIX_NONE, 16, 4, pd_base + offset, 16, false);
	1356	+}
	1357	+
1114	1358	void rockchip_dump_pmu(void)
1115	1359	{
1116		- if (pd_base) {
1117		- pr_warn("PMU:\n");
1118		- print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1119		- 32, 4, pd_base,
1120		- 0x100, false);
1121		- }
	1360	+ if (!pd_base)
	1361	+ return;
	1362	+
	1363	+ pr_warn("PMU:\n");
	1364	+ dump_offset("pwr", g_pmu->info->pwr_offset);
	1365	+ dump_offset("status", g_pmu->info->status_offset);
	1366	+ dump_offset("req", g_pmu->info->req_offset);
	1367	+ dump_offset("idle", g_pmu->info->idle_offset);
	1368	+ dump_offset("ack", g_pmu->info->ack_offset);
	1369	+ dump_offset("mem_pwr", g_pmu->info->mem_pwr_offset);
	1370	+ dump_offset("chain_st", g_pmu->info->chain_status_offset);
	1371	+ dump_offset("mem_st", g_pmu->info->mem_status_offset);
	1372	+ dump_offset("repair_st", g_pmu->info->repair_status_offset);
	1373	+ dump_offset("clkungate", g_pmu->info->clk_ungate_offset);
	1374	+ dump_offset("mem_sd", g_pmu->info->mem_sd_offset);
1122	1375	}
1123	1376	EXPORT_SYMBOL_GPL(rockchip_dump_pmu);
1124	1377
..	..	@@ -1208,16 +1461,16 @@
1208	1461	for_each_available_child_of_node(np, node) {
1209	1462	error = rockchip_pm_add_one_domain(pmu, node);
1210	1463	if (error) {
1211		- dev_err(dev, "failed to handle node %s: %d\n",
1212		- node->name, error);
	1464	+ dev_err(dev, "failed to handle node %pOFn: %d\n",
	1465	+ node, error);
1213	1466	of_node_put(node);
1214	1467	goto err_out;
1215	1468	}
1216	1469
1217	1470	error = rockchip_pm_add_subdomain(pmu, node);
1218	1471	if (error < 0) {
1219		- dev_err(dev, "failed to handle subdomain node %s: %d\n",
1220		- node->name, error);
	1472	+ dev_err(dev, "failed to handle subdomain node %pOFn: %d\n",
	1473	+ node, error);
1221	1474	of_node_put(node);
1222	1475	goto err_out;
1223	1476	}
..	..	@@ -1246,133 +1499,149 @@
1246	1499	}
1247	1500
1248	1501	static const struct rockchip_domain_info px30_pm_domains[] = {
1249		- [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), true),
1250		- [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false),
1251		- [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false),
1252		- [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false),
1253		- [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false),
1254		- [PX30_PD_VO] = DOMAIN_PX30_PROTECT(BIT(13), BIT(13), BIT(7), false),
1255		- [PX30_PD_VI] = DOMAIN_PX30_PROTECT(BIT(14), BIT(14), BIT(8), false),
1256		- [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false),
	1502	+ [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), true),
	1503	+ [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
	1504	+ [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
	1505	+ [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false),
	1506	+ [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false),
	1507	+ [PX30_PD_VO] = DOMAIN_PX30_PROTECT("vo", BIT(13), BIT(13), BIT(7), false),
	1508	+ [PX30_PD_VI] = DOMAIN_PX30_PROTECT("vi", BIT(14), BIT(14), BIT(8), false),
	1509	+ [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
1257	1510	};
1258	1511
1259	1512	static const struct rockchip_domain_info rv1126_pm_domains[] = {
1260		- [RV1126_PD_CRYPTO] = DOMAIN_RV1126_O(BIT(10), BIT(4), BIT(20), 0x4, false),
1261		- [RV1126_PD_VEPU] = DOMAIN_RV1126(BIT(2), BIT(9), BIT(9), false),
1262		- [RV1126_PD_VI] = DOMAIN_RV1126(BIT(4), BIT(6), BIT(6), false),
1263		- [RV1126_PD_VO] = DOMAIN_RV1126_PROTECT(BIT(5), BIT(7), BIT(7), false),
1264		- [RV1126_PD_ISPP] = DOMAIN_RV1126(BIT(1), BIT(8), BIT(8), false),
1265		- [RV1126_PD_VDPU] = DOMAIN_RV1126(BIT(3), BIT(10), BIT(10), false),
1266		- [RV1126_PD_NVM] = DOMAIN_RV1126(BIT(7), BIT(11), BIT(11), false),
1267		- [RV1126_PD_SDIO] = DOMAIN_RV1126(BIT(8), BIT(13), BIT(13), false),
1268		- [RV1126_PD_USB] = DOMAIN_RV1126(BIT(9), BIT(15), BIT(15), true),
1269		- [RV1126_PD_NPU] = DOMAIN_RV1126_O(BIT(0), BIT(2), BIT(18), 0x4, false),
	1513	+ [RV1126_PD_CRYPTO] = DOMAIN_RV1126_O("crypto", BIT(10), BIT(4), BIT(20), 0x4, false),
	1514	+ [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
	1515	+ [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
	1516	+ [RV1126_PD_VO] = DOMAIN_RV1126_PROTECT("vo", BIT(5), BIT(7), BIT(7), false),
	1517	+ [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
	1518	+ [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
	1519	+ [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
	1520	+ [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false),
	1521	+ [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), true),
	1522	+ [RV1126_PD_NPU] = DOMAIN_RV1126_O("npu", BIT(0), BIT(2), BIT(18), 0x4, false),
1270	1523	};
1271	1524
1272	1525	static const struct rockchip_domain_info rk1808_pm_domains[] = {
1273		- [RK1808_VD_NPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false),
1274		- [RK1808_PD_PCIE] = DOMAIN_PX30(BIT(9), BIT(9), BIT(4), true),
1275		- [RK1808_PD_VPU] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false),
1276		- [RK1808_PD_VIO] = DOMAIN_PX30_PROTECT(BIT(14), BIT(14), BIT(8), false),
	1526	+ [RK1808_VD_NPU] = DOMAIN_PX30("npu", BIT(15), BIT(15), BIT(2), false),
	1527	+ [RK1808_PD_PCIE] = DOMAIN_PX30("pcie", BIT(9), BIT(9), BIT(4), true),
	1528	+ [RK1808_PD_VPU] = DOMAIN_PX30("vpu", BIT(13), BIT(13), BIT(7), false),
	1529	+ [RK1808_PD_VIO] = DOMAIN_PX30_PROTECT("vio", BIT(14), BIT(14), BIT(8), false),
1277	1530	};
1278	1531
1279	1532	static const struct rockchip_domain_info rk3036_pm_domains[] = {
1280		- [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true),
1281		- [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false),
1282		- [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false),
1283		- [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false),
1284		- [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false),
1285		- [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false),
1286		- [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false),
	1533	+ [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
	1534	+ [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
	1535	+ [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
	1536	+ [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false),
	1537	+ [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false),
	1538	+ [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false),
	1539	+ [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false),
	1540	+};
	1541	+
	1542	+static const struct rockchip_domain_info rk3066_pm_domains[] = {
	1543	+ [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false, false),
	1544	+ [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false, false),
	1545	+ [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false, true),
	1546	+ [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false, false),
	1547	+ [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false, false),
1287	1548	};
1288	1549
1289	1550	static const struct rockchip_domain_info rk3128_pm_domains[] = {
1290		- [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false),
1291		- [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true),
1292		- [RK3128_PD_VIO] = DOMAIN_RK3288_PROTECT(BIT(3), BIT(3), BIT(2), false),
1293		- [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false),
1294		- [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false),
	1551	+ [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false),
	1552	+ [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true),
	1553	+ [RK3128_PD_VIO] = DOMAIN_RK3288_PROTECT("vio", BIT(3), BIT(3), BIT(2), false),
	1554	+ [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
	1555	+ [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false),
	1556	+};
	1557	+
	1558	+static const struct rockchip_domain_info rk3188_pm_domains[] = {
	1559	+ [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false, false),
	1560	+ [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false, false),
	1561	+ [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false, true),
	1562	+ [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false, false),
	1563	+ [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false, false),
1295	1564	};
1296	1565
1297	1566	static const struct rockchip_domain_info rk3228_pm_domains[] = {
1298		- [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true),
1299		- [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true),
1300		- [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true),
1301		- [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true),
1302		- [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false),
1303		- [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false),
1304		- [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false),
1305		- [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false),
1306		- [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false),
1307		- [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true),
1308		- [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false),
	1567	+ [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true),
	1568	+ [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true),
	1569	+ [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true),
	1570	+ [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true),
	1571	+ [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false),
	1572	+ [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false),
	1573	+ [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false),
	1574	+ [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
	1575	+ [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false),
	1576	+ [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true),
	1577	+ [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
1309	1578	};
1310	1579
1311	1580	static const struct rockchip_domain_info rk3288_pm_domains[] = {
1312		- [RK3288_PD_VIO] = DOMAIN_RK3288_PROTECT(BIT(7), BIT(7), BIT(4), false),
1313		- [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false),
1314		- [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false),
1315		- [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false),
	1581	+ [RK3288_PD_VIO] = DOMAIN_RK3288_PROTECT("vio", BIT(7), BIT(7), BIT(4), false),
	1582	+ [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false),
	1583	+ [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false),
	1584	+ [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false),
1316	1585	};
1317	1586
1318	1587	static const struct rockchip_domain_info rk3328_pm_domains[] = {
1319		- [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false),
1320		- [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false),
1321		- [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true),
1322		- [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true),
1323		- [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true),
1324		- [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false),
1325		- [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false),
1326		- [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false),
1327		- [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false),
	1588	+ [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false),
	1589	+ [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false),
	1590	+ [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true),
	1591	+ [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true),
	1592	+ [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true),
	1593	+ [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
	1594	+ [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false),
	1595	+ [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false),
	1596	+ [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false),
1328	1597	};
1329	1598
1330	1599	static const struct rockchip_domain_info rk3366_pm_domains[] = {
1331		- [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true),
1332		- [RK3366_PD_VIO] = DOMAIN_RK3368_PROTECT(BIT(14), BIT(14), BIT(8), false),
1333		- [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false),
1334		- [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false),
1335		- [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false),
1336		- [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false),
1337		- [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false),
	1600	+ [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true),
	1601	+ [RK3366_PD_VIO] = DOMAIN_RK3368_PROTECT("vio", BIT(14), BIT(14), BIT(8), false),
	1602	+ [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false),
	1603	+ [RK3366_PD_RKVDEC] = DOMAIN_RK3368("rkvdec", BIT(11), BIT(11), BIT(7), false),
	1604	+ [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false),
	1605	+ [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false),
	1606	+ [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false),
1338	1607	};
1339	1608
1340	1609	static const struct rockchip_domain_info rk3368_pm_domains[] = {
1341		- [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true),
1342		- [RK3368_PD_VIO] = DOMAIN_RK3368_PROTECT(BIT(15), BIT(14), BIT(8), false),
1343		- [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false),
1344		- [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false),
1345		- [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false),
	1610	+ [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true),
	1611	+ [RK3368_PD_VIO] = DOMAIN_RK3368_PROTECT("vio", BIT(15), BIT(14), BIT(8), false),
	1612	+ [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false),
	1613	+ [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false),
	1614	+ [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false),
1346	1615	};
1347	1616
1348	1617	static const struct rockchip_domain_info rk3399_pm_domains[] = {
1349		- [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false),
1350		- [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false),
1351		- [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true),
1352		- [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true),
1353		- [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true),
1354		- [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true),
1355		- [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true),
1356		- [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true),
1357		- [RK3399_PD_VIO] = DOMAIN_RK3399_PROTECT(BIT(14), BIT(14), BIT(17), false),
1358		- [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false),
1359		- [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false),
1360		- [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false),
1361		- [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false),
1362		- [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false),
1363		- [RK3399_PD_VO] = DOMAIN_RK3399_PROTECT(BIT(20), BIT(20), 0, false),
1364		- [RK3399_PD_VOPB] = DOMAIN_RK3399_PROTECT(0, 0, BIT(7), false),
1365		- [RK3399_PD_VOPL] = DOMAIN_RK3399_PROTECT(0, 0, BIT(8), false),
1366		- [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false),
1367		- [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false),
1368		- [RK3399_PD_HDCP] = DOMAIN_RK3399_PROTECT(BIT(24), BIT(24), BIT(11), false),
1369		- [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true),
1370		- [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true),
1371		- [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true),
1372		- [RK3399_PD_EDP] = DOMAIN_RK3399_PROTECT(BIT(28), BIT(28), BIT(22), false),
1373		- [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true),
1374		- [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true),
1375		- [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true),
	1618	+ [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false),
	1619	+ [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false),
	1620	+ [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true),
	1621	+ [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true),
	1622	+ [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true),
	1623	+ [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true),
	1624	+ [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true),
	1625	+ [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true),
	1626	+ [RK3399_PD_VIO] = DOMAIN_RK3399_PROTECT("vio", BIT(14), BIT(14), BIT(17), false),
	1627	+ [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false),
	1628	+ [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false),
	1629	+ [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false),
	1630	+ [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false),
	1631	+ [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false),
	1632	+ [RK3399_PD_VO] = DOMAIN_RK3399_PROTECT("vo", BIT(20), BIT(20), 0, false),
	1633	+ [RK3399_PD_VOPB] = DOMAIN_RK3399_PROTECT("vopb", 0, 0, BIT(7), false),
	1634	+ [RK3399_PD_VOPL] = DOMAIN_RK3399_PROTECT("vopl", 0, 0, BIT(8), false),
	1635	+ [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false),
	1636	+ [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false),
	1637	+ [RK3399_PD_HDCP] = DOMAIN_RK3399_PROTECT("hdcp", BIT(24), BIT(24), BIT(11), false),
	1638	+ [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true),
	1639	+ [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true),
	1640	+ [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true),
	1641	+ [RK3399_PD_EDP] = DOMAIN_RK3399_PROTECT("edp", BIT(28), BIT(28), BIT(22), false),
	1642	+ [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true),
	1643	+ [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true),
	1644	+ [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
1376	1645	};
1377	1646
1378	1647	static const struct rockchip_domain_info rk3528_pm_domains[] = {
..	..	@@ -1387,16 +1656,60 @@
1387	1656	[RK3528_PD_VPU] = DOMAIN_RK3528(0, BIT(8), true, false),
1388	1657	};
1389	1658
	1659	+static const struct rockchip_domain_info rk3562_pm_domains[] = {
	1660	+ [RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), 0, false),
	1661	+ [RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), 0, false),
	1662	+ [RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), 0, false),
	1663	+ [RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), 0, false),
	1664	+ [RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), 0, false),
	1665	+ [RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), 0, false),
	1666	+ [RK3562_PD_VO] = DOMAIN_RK3562_PROTECT("vo", BIT(6), BIT(4), 16, false),
	1667	+ [RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), 0, false),
	1668	+};
	1669	+
1390	1670	static const struct rockchip_domain_info rk3568_pm_domains[] = {
1391		- [RK3568_PD_NPU] = DOMAIN_RK3568(BIT(1), BIT(2), false),
1392		- [RK3568_PD_GPU] = DOMAIN_RK3568(BIT(0), BIT(1), false),
1393		- [RK3568_PD_VI] = DOMAIN_RK3568(BIT(6), BIT(3), false),
1394		- [RK3568_PD_VO] = DOMAIN_RK3568_PROTECT(BIT(7), BIT(4), false),
1395		- [RK3568_PD_RGA] = DOMAIN_RK3568(BIT(5), BIT(5), false),
1396		- [RK3568_PD_VPU] = DOMAIN_RK3568(BIT(2), BIT(6), false),
1397		- [RK3568_PD_RKVDEC] = DOMAIN_RK3568(BIT(4), BIT(8), false),
1398		- [RK3568_PD_RKVENC] = DOMAIN_RK3568(BIT(3), BIT(7), false),
1399		- [RK3568_PD_PIPE] = DOMAIN_RK3568(BIT(8), BIT(11), false),
	1671	+ [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
	1672	+ [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
	1673	+ [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false),
	1674	+ [RK3568_PD_VO] = DOMAIN_RK3568_PROTECT("vo", BIT(7), BIT(4), false),
	1675	+ [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
	1676	+ [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
	1677	+ [RK3568_PD_RKVDEC] = DOMAIN_RK3568("rkvdec", BIT(4), BIT(8), false),
	1678	+ [RK3568_PD_RKVENC] = DOMAIN_RK3568("rkvenc", BIT(3), BIT(7), false),
	1679	+ [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
	1680	+};
	1681	+
	1682	+static const struct rockchip_domain_info rk3588_pm_domains[] = {
	1683	+ /* name p_offset pwr status m_offset m_status r_status r_offset req idle wakeup */
	1684	+ [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false),
	1685	+ [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false),
	1686	+ [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false),
	1687	+ [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false),
	1688	+ [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false),
	1689	+ [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false),
	1690	+ [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false),
	1691	+ [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false),
	1692	+ [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false),
	1693	+ [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false),
	1694	+ [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false),
	1695	+ [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false),
	1696	+ [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false),
	1697	+ [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false),
	1698	+ [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false),
	1699	+ [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false),
	1700	+ [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false),
	1701	+ [RK3588_PD_VOP] = DOMAIN_RK3588_P("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) \| BIT(14), BIT(13) \| BIT(14), false),
	1702	+ [RK3588_PD_VO0] = DOMAIN_RK3588_P("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false),
	1703	+ [RK3588_PD_VO1] = DOMAIN_RK3588_P("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false),
	1704	+ [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false),
	1705	+ [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false),
	1706	+ [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false),
	1707	+ [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true),
	1708	+ [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false),
	1709	+ [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false),
	1710	+ [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false),
	1711	+ [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true),
	1712	+ [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false),
1400	1713	};
1401	1714
1402	1715	static const struct rockchip_pmu_info px30_pmu = {
..	..	@@ -1408,17 +1721,6 @@
1408	1721
1409	1722	.num_domains = ARRAY_SIZE(px30_pm_domains),
1410	1723	.domain_info = px30_pm_domains,
1411		-};
1412		-
1413		-static const struct rockchip_pmu_info rv1126_pmu = {
1414		- .pwr_offset = 0x110,
1415		- .status_offset = 0x108,
1416		- .req_offset = 0xc0,
1417		- .idle_offset = 0xd8,
1418		- .ack_offset = 0xd0,
1419		-
1420		- .num_domains = ARRAY_SIZE(rv1126_pm_domains),
1421		- .domain_info = rv1126_pm_domains,
1422	1724	};
1423	1725
1424	1726	static const struct rockchip_pmu_info rk1808_pmu = {
..	..	@@ -1441,6 +1743,17 @@
1441	1743	.domain_info = rk3036_pm_domains,
1442	1744	};
1443	1745
	1746	+static const struct rockchip_pmu_info rk3066_pmu = {
	1747	+ .pwr_offset = 0x08,
	1748	+ .status_offset = 0x0c,
	1749	+ .req_offset = 0x38, /* PMU_MISC_CON1 */
	1750	+ .idle_offset = 0x0c,
	1751	+ .ack_offset = 0x0c,
	1752	+
	1753	+ .num_domains = ARRAY_SIZE(rk3066_pm_domains),
	1754	+ .domain_info = rk3066_pm_domains,
	1755	+};
	1756	+
1444	1757	static const struct rockchip_pmu_info rk3128_pmu = {
1445	1758	.pwr_offset = 0x04,
1446	1759	.status_offset = 0x08,
..	..	@@ -1450,6 +1763,17 @@
1450	1763
1451	1764	.num_domains = ARRAY_SIZE(rk3128_pm_domains),
1452	1765	.domain_info = rk3128_pm_domains,
	1766	+};
	1767	+
	1768	+static const struct rockchip_pmu_info rk3188_pmu = {
	1769	+ .pwr_offset = 0x08,
	1770	+ .status_offset = 0x0c,
	1771	+ .req_offset = 0x38, /* PMU_MISC_CON1 */
	1772	+ .idle_offset = 0x0c,
	1773	+ .ack_offset = 0x0c,
	1774	+
	1775	+ .num_domains = ARRAY_SIZE(rk3188_pm_domains),
	1776	+ .domain_info = rk3188_pm_domains,
1453	1777	};
1454	1778
1455	1779	static const struct rockchip_pmu_info rk3228_pmu = {
..	..	@@ -1528,11 +1852,7 @@
1528	1852	.idle_offset = 0x64,
1529	1853	.ack_offset = 0x68,
1530	1854
1531		- .core_pwrcnt_offset = 0xac,
1532		- .gpu_pwrcnt_offset = 0xac,
1533		-
1534		- .core_power_transition_time = 6, /* 0.25us */
1535		- .gpu_power_transition_time = 6, /* 0.25us */
	1855	+ /* ARM Trusted Firmware manages power transition times */
1536	1856
1537	1857	.num_domains = ARRAY_SIZE(rk3399_pm_domains),
1538	1858	.domain_info = rk3399_pm_domains,
..	..	@@ -1549,6 +1869,19 @@
1549	1869	.domain_info = rk3528_pm_domains,
1550	1870	};
1551	1871
	1872	+static const struct rockchip_pmu_info rk3562_pmu = {
	1873	+ .pwr_offset = 0x210,
	1874	+ .status_offset = 0x230,
	1875	+ .req_offset = 0x110,
	1876	+ .idle_offset = 0x128,
	1877	+ .ack_offset = 0x120,
	1878	+ .clk_ungate_offset = 0x140,
	1879	+ .mem_sd_offset = 0x300,
	1880	+
	1881	+ .num_domains = ARRAY_SIZE(rk3562_pm_domains),
	1882	+ .domain_info = rk3562_pm_domains,
	1883	+};
	1884	+
1552	1885	static const struct rockchip_pmu_info rk3568_pmu = {
1553	1886	.pwr_offset = 0xa0,
1554	1887	.status_offset = 0x98,
..	..	@@ -1560,85 +1893,103 @@
1560	1893	.domain_info = rk3568_pm_domains,
1561	1894	};
1562	1895
	1896	+static const struct rockchip_pmu_info rk3588_pmu = {
	1897	+ .pwr_offset = 0x14c,
	1898	+ .status_offset = 0x180,
	1899	+ .req_offset = 0x10c,
	1900	+ .idle_offset = 0x120,
	1901	+ .ack_offset = 0x118,
	1902	+ .mem_pwr_offset = 0x1a0,
	1903	+ .chain_status_offset = 0x1f0,
	1904	+ .mem_status_offset = 0x1f8,
	1905	+ .repair_status_offset = 0x290,
	1906	+
	1907	+ .num_domains = ARRAY_SIZE(rk3588_pm_domains),
	1908	+ .domain_info = rk3588_pm_domains,
	1909	+};
	1910	+
	1911	+static const struct rockchip_pmu_info rv1126_pmu = {
	1912	+ .pwr_offset = 0x110,
	1913	+ .status_offset = 0x108,
	1914	+ .req_offset = 0xc0,
	1915	+ .idle_offset = 0xd8,
	1916	+ .ack_offset = 0xd0,
	1917	+
	1918	+ .num_domains = ARRAY_SIZE(rv1126_pm_domains),
	1919	+ .domain_info = rv1126_pm_domains,
	1920	+};
	1921	+
1563	1922	static const struct of_device_id rockchip_pm_domain_dt_match[] = {
1564		-#ifdef CONFIG_CPU_PX30
1565	1923	{
1566	1924	.compatible = "rockchip,px30-power-controller",
1567	1925	.data = (void *)&px30_pmu,
1568	1926	},
1569		-#endif
1570		-#ifdef CONFIG_CPU_RV1126
1571		- {
1572		- .compatible = "rockchip,rv1126-power-controller",
1573		- .data = (void *)&rv1126_pmu,
1574		- },
1575		-#endif
1576		-#ifdef CONFIG_CPU_RK1808
1577	1927	{
1578	1928	.compatible = "rockchip,rk1808-power-controller",
1579	1929	.data = (void *)&rk1808_pmu,
1580	1930	},
1581		-#endif
1582		-#ifdef CONFIG_CPU_RK3036
1583	1931	{
1584	1932	.compatible = "rockchip,rk3036-power-controller",
1585	1933	.data = (void *)&rk3036_pmu,
1586	1934	},
1587		-#endif
1588		-#ifdef CONFIG_CPU_RK312X
	1935	+ {
	1936	+ .compatible = "rockchip,rk3066-power-controller",
	1937	+ .data = (void *)&rk3066_pmu,
	1938	+ },
1589	1939	{
1590	1940	.compatible = "rockchip,rk3128-power-controller",
1591	1941	.data = (void *)&rk3128_pmu,
1592	1942	},
1593		-#endif
1594		-#ifdef CONFIG_CPU_RK322X
	1943	+ {
	1944	+ .compatible = "rockchip,rk3188-power-controller",
	1945	+ .data = (void *)&rk3188_pmu,
	1946	+ },
1595	1947	{
1596	1948	.compatible = "rockchip,rk3228-power-controller",
1597	1949	.data = (void *)&rk3228_pmu,
1598	1950	},
1599		-#endif
1600		-#ifdef CONFIG_CPU_RK3288
1601	1951	{
1602	1952	.compatible = "rockchip,rk3288-power-controller",
1603	1953	.data = (void *)&rk3288_pmu,
1604	1954	},
1605		-#endif
1606		-#ifdef CONFIG_CPU_RK3328
1607	1955	{
1608	1956	.compatible = "rockchip,rk3328-power-controller",
1609	1957	.data = (void *)&rk3328_pmu,
1610	1958	},
1611		-#endif
1612		-#ifdef CONFIG_CPU_RK3366
1613	1959	{
1614	1960	.compatible = "rockchip,rk3366-power-controller",
1615	1961	.data = (void *)&rk3366_pmu,
1616	1962	},
1617		-#endif
1618		-#ifdef CONFIG_CPU_RK3368
1619	1963	{
1620	1964	.compatible = "rockchip,rk3368-power-controller",
1621	1965	.data = (void *)&rk3368_pmu,
1622	1966	},
1623		-#endif
1624		-#ifdef CONFIG_CPU_RK3399
1625	1967	{
1626	1968	.compatible = "rockchip,rk3399-power-controller",
1627	1969	.data = (void *)&rk3399_pmu,
1628	1970	},
1629		-#endif
1630	1971	#ifdef CONFIG_CPU_RK3528
1631	1972	{
1632	1973	.compatible = "rockchip,rk3528-power-controller",
1633	1974	.data = (void *)&rk3528_pmu,
1634	1975	},
1635	1976	#endif
1636		-#ifdef CONFIG_CPU_RK3568
	1977	+ {
	1978	+ .compatible = "rockchip,rk3562-power-controller",
	1979	+ .data = (void *)&rk3562_pmu,
	1980	+ },
1637	1981	{
1638	1982	.compatible = "rockchip,rk3568-power-controller",
1639	1983	.data = (void *)&rk3568_pmu,
1640	1984	},
1641		-#endif
	1985	+ {
	1986	+ .compatible = "rockchip,rk3588-power-controller",
	1987	+ .data = (void *)&rk3588_pmu,
	1988	+ },
	1989	+ {
	1990	+ .compatible = "rockchip,rv1126-power-controller",
	1991	+ .data = (void *)&rv1126_pmu,
	1992	+ },
1642	1993	{ /* sentinel */ },
1643	1994	};
1644	1995	MODULE_DEVICE_TABLE(of, rockchip_pm_domain_dt_match);
..	..	@@ -1671,4 +2022,3 @@
1671	2022
1672	2023	MODULE_DESCRIPTION("ROCKCHIP PM Domain Driver");
1673	2024	MODULE_LICENSE("GPL");
1674		-MODULE_ALIAS("platform:rockchip-pm-domain");