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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/soc/imx/gpc.c
....@@ -1,13 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0+
12 /*
23  * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
34  * Copyright 2011-2013 Freescale Semiconductor, Inc.
4
- *
5
- * The code contained herein is licensed under the GNU General Public
6
- * License. You may obtain a copy of the GNU General Public License
7
- * Version 2 or later at the following locations:
8
- *
9
- * http://www.opensource.org/licenses/gpl-license.html
10
- * http://www.gnu.org/copyleft/gpl.html
115  */
126 
137 #include <linux/clk.h>
....@@ -41,7 +35,7 @@
4135 #define GPU_VPU_PUP_REQ		BIT(1)
4236 #define GPU_VPU_PDN_REQ		BIT(0)
4337 
44
-#define GPC_CLK_MAX		6
38
+#define GPC_CLK_MAX		7
4539 
4640 #define PGC_DOMAIN_FLAG_NO_PD		BIT(0)
4741 
....@@ -248,6 +242,7 @@
248242 #define GPC_PGC_DOMAIN_ARM	0
249243 #define GPC_PGC_DOMAIN_PU	1
250244 #define GPC_PGC_DOMAIN_DISPLAY	2
245
+#define GPC_PGC_DOMAIN_PCI	3
251246 
252247 static struct genpd_power_state imx6_pm_domain_pu_state = {
253248 	.power_off_latency_ns = 25000,
....@@ -255,12 +250,13 @@
255250 };
256251 
257252 static struct imx_pm_domain imx_gpc_domains[] = {
258
-	{
253
+	[GPC_PGC_DOMAIN_ARM] = {
259254 		.base = {
260255 			.name = "ARM",
261256 			.flags = GENPD_FLAG_ALWAYS_ON,
262257 		},
263
-	}, {
258
+	},
259
+	[GPC_PGC_DOMAIN_PU] = {
264260 		.base = {
265261 			.name = "PU",
266262 			.power_off = imx6_pm_domain_power_off,
....@@ -270,7 +266,8 @@
270266 		},
271267 		.reg_offs = 0x260,
272268 		.cntr_pdn_bit = 0,
273
-	}, {
269
+	},
270
+	[GPC_PGC_DOMAIN_DISPLAY] = {
274271 		.base = {
275272 			.name = "DISPLAY",
276273 			.power_off = imx6_pm_domain_power_off,
....@@ -278,7 +275,8 @@
278275 		},
279276 		.reg_offs = 0x240,
280277 		.cntr_pdn_bit = 4,
281
-	}, {
278
+	},
279
+	[GPC_PGC_DOMAIN_PCI] = {
282280 		.base = {
283281 			.name = "PCI",
284282 			.power_off = imx6_pm_domain_power_off,
....@@ -350,8 +348,8 @@
350348 };
351349 
352350 static struct generic_pm_domain *imx_gpc_onecell_domains[] = {
353
-	&imx_gpc_domains[0].base,
354
-	&imx_gpc_domains[1].base,
351
+	&imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base,
352
+	&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base,
355353 };
356354 
357355 static struct genpd_onecell_data imx_gpc_onecell_data = {
....@@ -410,7 +408,6 @@
410408 	const struct imx_gpc_dt_data *of_id_data = of_id->data;
411409 	struct device_node *pgc_node;
412410 	struct regmap *regmap;
413
-	struct resource *res;
414411 	void __iomem *base;
415412 	int ret;
416413 
....@@ -421,8 +418,7 @@
421418 	    !pgc_node)
422419 		return 0;
423420 
424
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
425
-	base = devm_ioremap_resource(&pdev->dev, res);
421
+	base = devm_platform_ioremap_resource(pdev, 0);
426422 	if (IS_ERR(base))
427423 		return PTR_ERR(base);
428424 
....@@ -435,10 +431,19 @@
435431 		return ret;
436432 	}
437433 
438
-	/* Disable PU power down in normal operation if ERR009619 is present */
434
+	/*
435
+	 * Disable PU power down by runtime PM if ERR009619 is present.
436
+	 *
437
+	 * The PRE clock will be paused for several cycles when turning on the
438
+	 * PU domain LDO from power down state. If PRE is in use at that time,
439
+	 * the IPU/PRG cannot get the correct display data from the PRE.
440
+	 *
441
+	 * This is not a concern when the whole system enters suspend state, so
442
+	 * it's safe to power down PU in this case.
443
+	 */
439444 	if (of_id_data->err009619_present)
440445 		imx_gpc_domains[GPC_PGC_DOMAIN_PU].base.flags |=
441
-				GENPD_FLAG_ALWAYS_ON;
446
+				GENPD_FLAG_RPM_ALWAYS_ON;
442447 
443448 	/* Keep DISP always on if ERR006287 is present */
444449 	if (of_id_data->err006287_present)