enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/scsi/ufs/ufs-qcom.h
..
..
@@ -1,18 +1,12 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
1
2
 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
2
- *
3
- * This program is free software; you can redistribute it and/or modify
4
- * it under the terms of the GNU General Public License version 2 and
5
- * only version 2 as published by the Free Software Foundation.
6
- *
7
- * This program is distributed in the hope that it will be useful,
8
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
- * GNU General Public License for more details.
11
- *
12
3
  */
13
4
 
14
5
 #ifndef UFS_QCOM_H_
15
6
 #define UFS_QCOM_H_
7
+
8
+#include <linux/reset-controller.h>
9
+#include <linux/reset.h>
16
10
 
17
11
 #define MAX_UFS_QCOM_HOSTS	1
18
12
 #define MAX_U32                 (~(u32)0)
..
..
@@ -129,11 +123,6 @@
129
123
 	MASK_CLK_NS_REG                     = 0xFFFC00,
130
124
 };
131
125
 
132
-enum ufs_qcom_phy_init_type {
133
-	UFS_PHY_INIT_FULL,
134
-	UFS_PHY_INIT_CFG_RESTORE,
135
-};
136
-
137
126
 /* QCOM UFS debug print bit mask */
138
127
 #define UFS_QCOM_DBG_PRINT_REGS_EN	BIT(0)
139
128
 #define UFS_QCOM_DBG_PRINT_ICE_REGS_EN	BIT(1)
..
..
@@ -185,16 +174,6 @@
185
174
 	mb();
186
175
 }
187
176
 
188
-struct ufs_qcom_bus_vote {
189
-	uint32_t client_handle;
190
-	uint32_t curr_vote;
191
-	int min_bw_vote;
192
-	int max_bw_vote;
193
-	int saved_vote;
194
-	bool is_max_bw_needed;
195
-	struct device_attribute max_bus_bw;
196
-};
197
-
198
177
 /* Host controller hardware version: major.minor.step */
199
178
 struct ufs_hw_version {
200
179
 	u16 step;
..
..
@@ -206,6 +185,8 @@
206
185
 	u8 select_major;
207
186
 	u8 select_minor;
208
187
 };
188
+
189
+struct gpio_desc;
209
190
 
210
191
 struct ufs_qcom_host {
211
192
 	/*
..
..
@@ -225,7 +206,6 @@
225
206
 
226
207
 	struct phy *generic_phy;
227
208
 	struct ufs_hba *hba;
228
-	struct ufs_qcom_bus_vote bus_vote;
229
209
 	struct ufs_pa_layer_attr dev_req_params;
230
210
 	struct clk *rx_l0_sync_clk;
231
211
 	struct clk *tx_l0_sync_clk;
..
..
@@ -236,12 +216,21 @@
236
216
 	void __iomem *dev_ref_clk_ctrl_mmio;
237
217
 	bool is_dev_ref_clk_enabled;
238
218
 	struct ufs_hw_version hw_ver;
219
+#ifdef CONFIG_SCSI_UFS_CRYPTO
220
+	void __iomem *ice_mmio;
221
+#endif
239
222
 
240
223
 	u32 dev_ref_clk_en_mask;
241
224
 
242
225
 	/* Bitmask for enabling debug prints */
243
226
 	u32 dbg_print_en;
244
227
 	struct ufs_qcom_testbus testbus;
228
+
229
+	/* Reset control of HCI */
230
+	struct reset_control *core_reset;
231
+	struct reset_controller_dev rcdev;
232
+
233
+	struct gpio_desc *device_reset;
245
234
 };
246
235
 
247
236
 static inline u32
..
..
@@ -267,4 +256,28 @@
267
256
 		return false;
268
257
 }
269
258
 
259
+/* ufs-qcom-ice.c */
260
+
261
+#ifdef CONFIG_SCSI_UFS_CRYPTO
262
+int ufs_qcom_ice_init(struct ufs_qcom_host *host);
263
+int ufs_qcom_ice_enable(struct ufs_qcom_host *host);
264
+int ufs_qcom_ice_resume(struct ufs_qcom_host *host);
265
+int ufs_qcom_ice_program_key(struct ufs_hba *hba,
266
+			     const union ufs_crypto_cfg_entry *cfg, int slot);
267
+#else
268
+static inline int ufs_qcom_ice_init(struct ufs_qcom_host *host)
269
+{
270
+	return 0;
271
+}
272
+static inline int ufs_qcom_ice_enable(struct ufs_qcom_host *host)
273
+{
274
+	return 0;
275
+}
276
+static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
277
+{
278
+	return 0;
279
+}
280
+#define ufs_qcom_ice_program_key NULL
281
+#endif /* !CONFIG_SCSI_UFS_CRYPTO */
282
+
270
283
 #endif /* UFS_QCOM_H_ */