enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/scsi/qla2xxx/qla_mr.h
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@@ -1,11 +1,12 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * QLogic Fibre Channel HBA Driver
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  * Copyright (c)  2003-2014 QLogic Corporation
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- *
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- * See LICENSE.qla2xxx for copyright and licensing details.
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  */
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 #ifndef __QLA_MR_H
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 #define __QLA_MR_H
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+
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+#include "qla_dsd.h"
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 /*
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  * The PCI VendorID and DeviceID for our board.
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@@ -46,8 +47,7 @@
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 	uint8_t fcp_cdb[MAX_CMDSZ];	/* SCSI command words. */
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 	__le32 byte_count;		/* Total byte count. */
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-	uint32_t dseg_0_address[2];	/* Data segment 0 address. */
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-	uint32_t dseg_0_len;		/* Data segment 0 length. */
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+	struct dsd64 dsd;
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 };
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 #define	STATUS_TYPE_FX00	0x01		/* Status entry. */
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@@ -95,7 +95,7 @@
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 	uint8_t sys_define;
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 	uint8_t entry_status;		/* Entry Status. */
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-	__le32 handle;		/* System handle. */
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+	uint32_t handle;		/* System handle. */
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 	uint32_t reserved_0;
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@@ -120,13 +120,13 @@
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 	uint8_t sys_define;		/* System defined. */
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 	uint8_t entry_status;		/* Entry Status. */
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-	__le32 handle;		/* System handle. */
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+	uint32_t handle;		/* System handle. */
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 	__le32 reserved_0;
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 	__le16 tgt_id_sts;		/* Completion status. */
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 	__le16 options;
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-	__le32 abort_handle;		/* System handle. */
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+	uint32_t abort_handle;		/* System handle. */
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 	__le32 reserved_2;
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 	__le16 req_que_no;
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@@ -165,7 +165,7 @@
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 	uint8_t sys_define;		/* System Defined. */
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 	uint8_t entry_status;		/* Entry Status. */
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-	__le32 handle;		/* System handle. */
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+	uint32_t handle;		/* System handle. */
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 	__le32 reserved_0;		/* System handle. */
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 	__le16 func_num;
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@@ -176,10 +176,8 @@
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 	uint8_t flags;
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 	uint8_t reserved_1;
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-	__le32 dseg_rq_address[2];	/* Data segment 0 address. */
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-	__le32 dseg_rq_len;		/* Data segment 0 length. */
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-	__le32 dseg_rsp_address[2];	/* Data segment 1 address. */
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-	__le32 dseg_rsp_len;		/* Data segment 1 length. */
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+	struct dsd64 dseg_rq;
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+	struct dsd64 dseg_rsp;
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 	__le32 dataword;
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 	__le32 adapid;
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@@ -360,47 +358,47 @@
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 #define CONTINUE_A64_TYPE_FX00	0x03	/* Continuation entry. */
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 #define QLAFX00_SET_HST_INTR(ha, value) \
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-	WRT_REG_DWORD((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \
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+	wrt_reg_dword((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \
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 	value)
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 #define QLAFX00_CLR_HST_INTR(ha, value) \
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-	WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
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+	wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
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 	~value)
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 #define QLAFX00_RD_INTR_REG(ha) \
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-	RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)
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+	rd_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)
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 #define QLAFX00_CLR_INTR_REG(ha, value) \
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-	WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
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+	wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
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 	~value)
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 #define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\
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-	WRT_REG_DWORD((ha)->cregbase + off, val)
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+	wrt_reg_dword((ha)->cregbase + off, val)
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 #define QLAFX00_GET_HBA_SOC_REG(ha, off)\
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-	RD_REG_DWORD((ha)->cregbase + off)
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+	rd_reg_dword((ha)->cregbase + off)
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 #define QLAFX00_HBA_RST_REG(ha, val)\
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-	WRT_REG_DWORD((ha)->cregbase + QLAFX00_HST_RST_REG, val)
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+	wrt_reg_dword((ha)->cregbase + QLAFX00_HST_RST_REG, val)
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 #define QLAFX00_RD_ICNTRL_REG(ha) \
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-	RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)
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+	rd_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)
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 #define QLAFX00_ENABLE_ICNTRL_REG(ha) \
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-	WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
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+	wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
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 	(QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) | \
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 	 QLAFX00_ICR_ENB_MASK))
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 #define QLAFX00_DISABLE_ICNTRL_REG(ha) \
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-	WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
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+	wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
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 	(QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) & \
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 	 QLAFX00_ICR_DIS_MASK))
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 #define QLAFX00_RD_REG(ha, off) \
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-	RD_REG_DWORD((ha)->cregbase + off)
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+	rd_reg_dword((ha)->cregbase + off)
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 #define QLAFX00_WR_REG(ha, off, val) \
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-	WRT_REG_DWORD((ha)->cregbase + off, val)
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+	wrt_reg_dword((ha)->cregbase + off, val)
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 struct qla_mt_iocb_rqst_fx00 {
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 	__le32 reserved_0;