~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,14 +1,19 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* QLogic Fibre Channel HBA Driver
3	4	* Copyright (c) 2003-2014 QLogic Corporation
4		- *
5		- * See LICENSE.qla2xxx for copyright and licensing details.
6	5	*/
7	6	#include "qla_def.h"
8	7	#include "qla_target.h"
9	8
10	9	#include <linux/delay.h>
11	10	#include <linux/gfp.h>
	11	+
	12	+#ifdef CONFIG_PPC
	13	+#define IS_PPCARCH true
	14	+#else
	15	+#define IS_PPCARCH false
	16	+#endif
12	17
13	18	static struct mb_cmd_name {
14	19	uint16_t cmd;
..	..	@@ -59,7 +64,9 @@
59	64	{ MBC_IOCB_COMMAND_A64 },
60	65	{ MBC_GET_ADAPTER_LOOP_ID },
61	66	{ MBC_READ_SFP },
	67	+ { MBC_SET_RNID_PARAMS },
62	68	{ MBC_GET_RNID_PARAMS },
	69	+ { MBC_GET_SET_ZIO_THRESHOLD },
63	70	};
64	71
65	72	static int is_rom_cmd(uint16_t cmd)
..	..	@@ -105,7 +112,7 @@
105	112	uint8_t io_lock_on;
106	113	uint16_t command = 0;
107	114	uint16_t *iptr;
108		- uint16_t __iomem *optr;
	115	+ __le16 __iomem *optr;
109	116	uint32_t cnt;
110	117	uint32_t mboxes;
111	118	unsigned long wait_time;
..	..	@@ -116,10 +123,9 @@
116	123
117	124	ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
118	125
119		- if (ha->pdev->error_state > pci_channel_io_frozen) {
	126	+ if (ha->pdev->error_state == pci_channel_io_perm_failure) {
120	127	ql_log(ql_log_warn, vha, 0x1001,
121		- "error_state is greater than pci_channel_io_frozen, "
122		- "exiting.\n");
	128	+ "PCI channel failed permanently, exiting.\n");
123	129	return QLA_FUNCTION_TIMEOUT;
124	130	}
125	131
..	..	@@ -189,7 +195,7 @@
189	195	goto premature_exit;
190	196	}
191	197
192		- ha->flags.mbox_busy = 1;
	198	+
193	199	/* Save mailbox command for debug */
194	200	ha->mcp = mcp;
195	201
..	..	@@ -198,20 +204,21 @@
198	204
199	205	spin_lock_irqsave(&ha->hardware_lock, flags);
200	206
201		- if (ha->flags.purge_mbox \|\| chip_reset != ha->chip_reset) {
	207	+ if (ha->flags.purge_mbox \|\| chip_reset != ha->chip_reset \|\|
	208	+ ha->flags.mbox_busy) {
202	209	rval = QLA_ABORTED;
203		- ha->flags.mbox_busy = 0;
204	210	spin_unlock_irqrestore(&ha->hardware_lock, flags);
205	211	goto premature_exit;
206	212	}
	213	+ ha->flags.mbox_busy = 1;
207	214
208	215	/* Load mailbox registers. */
209	216	if (IS_P3P_TYPE(ha))
210		- optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
	217	+ optr = &reg->isp82.mailbox_in[0];
211	218	else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
212		- optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
	219	+ optr = &reg->isp24.mailbox0;
213	220	else
214		- optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
	221	+ optr = MAILBOX_REG(ha, &reg->isp, 0);
215	222
216	223	iptr = mcp->mb;
217	224	command = mcp->mb[0];
..	..	@@ -221,12 +228,13 @@
221	228	"Mailbox registers (OUT):\n");
222	229	for (cnt = 0; cnt < ha->mbx_count; cnt++) {
223	230	if (IS_QLA2200(ha) && cnt == 8)
224		- optr =
225		- (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
	231	+ optr = MAILBOX_REG(ha, &reg->isp, 8);
226	232	if (mboxes & BIT_0) {
227	233	ql_dbg(ql_dbg_mbx, vha, 0x1112,
228	234	"mbox[%d]<-0x%04x\n", cnt, *iptr);
229		- WRT_REG_WORD(optr, *iptr);
	235	+ wrt_reg_word(optr, *iptr);
	236	+ } else {
	237	+ wrt_reg_word(optr, 0);
230	238	}
231	239
232	240	mboxes >>= 1;
..	..	@@ -251,23 +259,12 @@
251	259	if ((!abort_active && io_lock_on) \|\| IS_NOPOLLING_TYPE(ha)) {
252	260	set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
253	261
254		- if (IS_P3P_TYPE(ha)) {
255		- if (RD_REG_DWORD(&reg->isp82.hint) &
256		- HINT_MBX_INT_PENDING) {
257		- spin_unlock_irqrestore(&ha->hardware_lock,
258		- flags);
259		- ha->flags.mbox_busy = 0;
260		- atomic_dec(&ha->num_pend_mbx_stage2);
261		- ql_dbg(ql_dbg_mbx, vha, 0x1010,
262		- "Pending mailbox timeout, exiting.\n");
263		- rval = QLA_FUNCTION_TIMEOUT;
264		- goto premature_exit;
265		- }
266		- WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
267		- } else if (IS_FWI2_CAPABLE(ha))
268		- WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
	262	+ if (IS_P3P_TYPE(ha))
	263	+ wrt_reg_dword(&reg->isp82.hint, HINT_MBX_INT_PENDING);
	264	+ else if (IS_FWI2_CAPABLE(ha))
	265	+ wrt_reg_dword(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
269	266	else
270		- WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
	267	+ wrt_reg_word(&reg->isp.hccr, HCCR_SET_HOST_INT);
271	268	spin_unlock_irqrestore(&ha->hardware_lock, flags);
272	269
273	270	wait_time = jiffies;
..	..	@@ -280,9 +277,21 @@
280	277	clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
281	278	spin_unlock_irqrestore(&ha->hardware_lock, flags);
282	279
	280	+ if (chip_reset != ha->chip_reset) {
	281	+ spin_lock_irqsave(&ha->hardware_lock, flags);
	282	+ ha->flags.mbox_busy = 0;
	283	+ spin_unlock_irqrestore(&ha->hardware_lock,
	284	+ flags);
	285	+ atomic_dec(&ha->num_pend_mbx_stage2);
	286	+ atomic_dec(&ha->num_pend_mbx_stage3);
	287	+ rval = QLA_ABORTED;
	288	+ goto premature_exit;
	289	+ }
283	290	} else if (ha->flags.purge_mbox \|\|
284	291	chip_reset != ha->chip_reset) {
	292	+ spin_lock_irqsave(&ha->hardware_lock, flags);
285	293	ha->flags.mbox_busy = 0;
	294	+ spin_unlock_irqrestore(&ha->hardware_lock, flags);
286	295	atomic_dec(&ha->num_pend_mbx_stage2);
287	296	atomic_dec(&ha->num_pend_mbx_stage3);
288	297	rval = QLA_ABORTED;
..	..	@@ -298,29 +307,32 @@
298	307	"Cmd=%x Polling Mode.\n", command);
299	308
300	309	if (IS_P3P_TYPE(ha)) {
301		- if (RD_REG_DWORD(&reg->isp82.hint) &
	310	+ if (rd_reg_dword(&reg->isp82.hint) &
302	311	HINT_MBX_INT_PENDING) {
	312	+ ha->flags.mbox_busy = 0;
303	313	spin_unlock_irqrestore(&ha->hardware_lock,
304	314	flags);
305		- ha->flags.mbox_busy = 0;
306	315	atomic_dec(&ha->num_pend_mbx_stage2);
307	316	ql_dbg(ql_dbg_mbx, vha, 0x1012,
308	317	"Pending mailbox timeout, exiting.\n");
309	318	rval = QLA_FUNCTION_TIMEOUT;
310	319	goto premature_exit;
311	320	}
312		- WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
	321	+ wrt_reg_dword(&reg->isp82.hint, HINT_MBX_INT_PENDING);
313	322	} else if (IS_FWI2_CAPABLE(ha))
314		- WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
	323	+ wrt_reg_dword(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
315	324	else
316		- WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
	325	+ wrt_reg_word(&reg->isp.hccr, HCCR_SET_HOST_INT);
317	326	spin_unlock_irqrestore(&ha->hardware_lock, flags);
318	327
319	328	wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
320	329	while (!ha->flags.mbox_int) {
321	330	if (ha->flags.purge_mbox \|\|
322	331	chip_reset != ha->chip_reset) {
	332	+ spin_lock_irqsave(&ha->hardware_lock, flags);
323	333	ha->flags.mbox_busy = 0;
	334	+ spin_unlock_irqrestore(&ha->hardware_lock,
	335	+ flags);
324	336	atomic_dec(&ha->num_pend_mbx_stage2);
325	337	rval = QLA_ABORTED;
326	338	goto premature_exit;
..	..	@@ -355,7 +367,10 @@
355	367	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
356	368
357	369	if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
	370	+ spin_lock_irqsave(&ha->hardware_lock, flags);
358	371	ha->flags.mbox_busy = 0;
	372	+ spin_unlock_irqrestore(&ha->hardware_lock, flags);
	373	+
359	374	/* Setting Link-Down error */
360	375	mcp->mb[0] = MBS_LINK_DOWN_ERROR;
361	376	ha->mcp = NULL;
..	..	@@ -365,8 +380,12 @@
365	380	goto premature_exit;
366	381	}
367	382
368		- if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
	383	+ if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) {
	384	+ ql_dbg(ql_dbg_mbx, vha, 0x11ff,
	385	+ "mb_out[0] = %#x <> %#x\n", ha->mailbox_out[0],
	386	+ MBS_COMMAND_COMPLETE);
369	387	rval = QLA_FUNCTION_FAILED;
	388	+ }
370	389
371	390	/* Load return mailbox registers. */
372	391	iptr2 = mcp->mb;
..	..	@@ -393,14 +412,14 @@
393	412	uint16_t w;
394	413
395	414	if (IS_FWI2_CAPABLE(ha)) {
396		- mb[0] = RD_REG_WORD(&reg->isp24.mailbox0);
397		- mb[1] = RD_REG_WORD(&reg->isp24.mailbox1);
398		- mb[2] = RD_REG_WORD(&reg->isp24.mailbox2);
399		- mb[3] = RD_REG_WORD(&reg->isp24.mailbox3);
400		- mb[7] = RD_REG_WORD(&reg->isp24.mailbox7);
401		- ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
402		- host_status = RD_REG_DWORD(&reg->isp24.host_status);
403		- hccr = RD_REG_DWORD(&reg->isp24.hccr);
	415	+ mb[0] = rd_reg_word(&reg->isp24.mailbox0);
	416	+ mb[1] = rd_reg_word(&reg->isp24.mailbox1);
	417	+ mb[2] = rd_reg_word(&reg->isp24.mailbox2);
	418	+ mb[3] = rd_reg_word(&reg->isp24.mailbox3);
	419	+ mb[7] = rd_reg_word(&reg->isp24.mailbox7);
	420	+ ictrl = rd_reg_dword(&reg->isp24.ictrl);
	421	+ host_status = rd_reg_dword(&reg->isp24.host_status);
	422	+ hccr = rd_reg_dword(&reg->isp24.hccr);
404	423
405	424	ql_log(ql_log_warn, vha, 0xd04c,
406	425	"MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
..	..	@@ -410,7 +429,7 @@
410	429
411	430	} else {
412	431	mb[0] = RD_MAILBOX_REG(ha, &reg->isp, 0);
413		- ictrl = RD_REG_WORD(&reg->isp.ictrl);
	432	+ ictrl = rd_reg_word(&reg->isp.ictrl);
414	433	ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
415	434	"MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
416	435	"mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
..	..	@@ -428,7 +447,10 @@
428	447	* then only PCI ERR flag would be set.
429	448	* we will do premature exit for above case.
430	449	*/
	450	+ spin_lock_irqsave(&ha->hardware_lock, flags);
431	451	ha->flags.mbox_busy = 0;
	452	+ spin_unlock_irqrestore(&ha->hardware_lock,
	453	+ flags);
432	454	rval = QLA_FUNCTION_TIMEOUT;
433	455	goto premature_exit;
434	456	}
..	..	@@ -439,12 +461,13 @@
439	461	* a dump
440	462	*/
441	463	if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
442		- ha->isp_ops->fw_dump(vha, 0);
	464	+ qla2xxx_dump_fw(vha);
443	465	rval = QLA_FUNCTION_TIMEOUT;
444	466	}
445	467	}
446		-
	468	+ spin_lock_irqsave(&ha->hardware_lock, flags);
447	469	ha->flags.mbox_busy = 0;
	470	+ spin_unlock_irqrestore(&ha->hardware_lock, flags);
448	471
449	472	/* Clean up */
450	473	ha->mcp = NULL;
..	..	@@ -534,9 +557,9 @@
534	557	mcp->mb[0]);
535	558	} else if (rval) {
536	559	if (ql2xextended_error_logging & (ql_dbg_disc\|ql_dbg_mbx)) {
537		- pr_warn("%s [%s]-%04x:%ld: **** Failed", QL_MSGHDR,
	560	+ pr_warn("%s [%s]-%04x:%ld: **** Failed=%x", QL_MSGHDR,
538	561	dev_name(&ha->pdev->dev), 0x1020+0x800,
539		- vha->host_no);
	562	+ vha->host_no, rval);
540	563	mboxes = mcp->in_mb;
541	564	cnt = 4;
542	565	for (i = 0; i < ha->mbx_count && cnt; i++, mboxes >>= 1)
..	..	@@ -549,15 +572,15 @@
549	572	if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) {
550	573	ql_dbg(ql_dbg_mbx, vha, 0x1198,
551	574	"host_status=%#x intr_ctrl=%#x intr_status=%#x\n",
552		- RD_REG_DWORD(&reg->isp24.host_status),
553		- RD_REG_DWORD(&reg->isp24.ictrl),
554		- RD_REG_DWORD(&reg->isp24.istatus));
	575	+ rd_reg_dword(&reg->isp24.host_status),
	576	+ rd_reg_dword(&reg->isp24.ictrl),
	577	+ rd_reg_dword(&reg->isp24.istatus));
555	578	} else {
556	579	ql_dbg(ql_dbg_mbx, vha, 0x1206,
557	580	"ctrl_status=%#x ictrl=%#x istatus=%#x\n",
558		- RD_REG_WORD(&reg->isp.ctrl_status),
559		- RD_REG_WORD(&reg->isp.ictrl),
560		- RD_REG_WORD(&reg->isp.istatus));
	581	+ rd_reg_word(&reg->isp.ctrl_status),
	582	+ rd_reg_word(&reg->isp.ictrl),
	583	+ rd_reg_word(&reg->isp.istatus));
561	584	}
562	585	} else {
563	586	ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
..	..	@@ -601,14 +624,15 @@
601	624	mcp->out_mb \|= MBX_4;
602	625	}
603	626
604		- mcp->in_mb = MBX_0;
	627	+ mcp->in_mb = MBX_1\|MBX_0;
605	628	mcp->tov = MBX_TOV_SECONDS;
606	629	mcp->flags = 0;
607	630	rval = qla2x00_mailbox_command(vha, mcp);
608	631
609	632	if (rval != QLA_SUCCESS) {
610	633	ql_dbg(ql_dbg_mbx, vha, 0x1023,
611		- "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
	634	+ "Failed=%x mb[0]=%x mb[1]=%x.\n",
	635	+ rval, mcp->mb[0], mcp->mb[1]);
612	636	} else {
613	637	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
614	638	"Done %s.\n", __func__);
..	..	@@ -617,30 +641,7 @@
617	641	return rval;
618	642	}
619	643
620		-#define EXTENDED_BB_CREDITS BIT_0
621	644	#define NVME_ENABLE_FLAG BIT_3
622		-static inline uint16_t qla25xx_set_sfp_lr_dist(struct qla_hw_data *ha)
623		-{
624		- uint16_t mb4 = BIT_0;
625		-
626		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
627		- mb4 \|= ha->long_range_distance << LR_DIST_FW_POS;
628		-
629		- return mb4;
630		-}
631		-
632		-static inline uint16_t qla25xx_set_nvr_lr_dist(struct qla_hw_data *ha)
633		-{
634		- uint16_t mb4 = BIT_0;
635		-
636		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha)) {
637		- struct nvram_81xx *nv = ha->nvram;
638		-
639		- mb4 \|= LR_DIST_FW_FIELD(nv->enhanced_features);
640		- }
641		-
642		- return mb4;
643		-}
644	645
645	646	/*
646	647	* qla2x00_execute_fw
..	..	@@ -664,10 +665,14 @@
664	665	struct qla_hw_data *ha = vha->hw;
665	666	mbx_cmd_t mc;
666	667	mbx_cmd_t *mcp = &mc;
	668	+ u8 semaphore = 0;
	669	+#define EXE_FW_FORCE_SEMAPHORE BIT_7
	670	+ u8 retry = 3;
667	671
668	672	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
669	673	"Entered %s.\n", __func__);
670	674
	675	+again:
671	676	mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
672	677	mcp->out_mb = MBX_0;
673	678	mcp->in_mb = MBX_0;
..	..	@@ -677,41 +682,33 @@
677	682	mcp->mb[3] = 0;
678	683	mcp->mb[4] = 0;
679	684	mcp->mb[11] = 0;
680		- ha->flags.using_lr_setting = 0;
681		- if (IS_QLA25XX(ha) \|\| IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\|
682		- IS_QLA27XX(ha)) {
683		- if (ql2xautodetectsfp) {
684		- if (ha->flags.detected_lr_sfp) {
685		- mcp->mb[4] \|=
686		- qla25xx_set_sfp_lr_dist(ha);
687		- ha->flags.using_lr_setting = 1;
688		- }
689		- } else {
690		- struct nvram_81xx *nv = ha->nvram;
691		- /* set LR distance if specified in nvram */
692		- if (nv->enhanced_features &
693		- NEF_LR_DIST_ENABLE) {
694		- mcp->mb[4] \|=
695		- qla25xx_set_nvr_lr_dist(ha);
696		- ha->flags.using_lr_setting = 1;
697		- }
698		- }
	685	+
	686	+ /* Enable BPM? */
	687	+ if (ha->flags.lr_detected) {
	688	+ mcp->mb[4] = BIT_0;
	689	+ if (IS_BPM_RANGE_CAPABLE(ha))
	690	+ mcp->mb[4] \|=
	691	+ ha->lr_distance << LR_DIST_FW_POS;
699	692	}
700	693
701		- if (ql2xnvmeenable && IS_QLA27XX(ha))
	694	+ if (ql2xnvmeenable && (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)))
702	695	mcp->mb[4] \|= NVME_ENABLE_FLAG;
703	696
704		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha)) {
	697	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
705	698	struct nvram_81xx *nv = ha->nvram;
706	699	/* set minimum speed if specified in nvram */
707		- if (nv->min_link_speed >= 2 &&
708		- nv->min_link_speed <= 5) {
	700	+ if (nv->min_supported_speed >= 2 &&
	701	+ nv->min_supported_speed <= 5) {
709	702	mcp->mb[4] \|= BIT_4;
710		- mcp->mb[11] = nv->min_link_speed;
	703	+ mcp->mb[11] \|= nv->min_supported_speed & 0xF;
711	704	mcp->out_mb \|= MBX_11;
712	705	mcp->in_mb \|= BIT_5;
713		- vha->min_link_speed_feat = nv->min_link_speed;
	706	+ vha->min_supported_speed =
	707	+ nv->min_supported_speed;
714	708	}
	709	+
	710	+ if (IS_PPCARCH)
	711	+ mcp->mb[11] \|= BIT_4;
715	712	}
716	713
717	714	if (ha->flags.exlogins_enabled)
..	..	@@ -719,6 +716,9 @@
719	716
720	717	if (ha->flags.exchoffld_enabled)
721	718	mcp->mb[4] \|= ENABLE_EXCHANGE_OFFLD;
	719	+
	720	+ if (semaphore)
	721	+ mcp->mb[11] \|= EXE_FW_FORCE_SEMAPHORE;
722	722
723	723	mcp->out_mb \|= MBX_4 \| MBX_3 \| MBX_2 \| MBX_1 \| MBX_11;
724	724	mcp->in_mb \|= MBX_3 \| MBX_2 \| MBX_1;
..	..	@@ -736,35 +736,49 @@
736	736	rval = qla2x00_mailbox_command(vha, mcp);
737	737
738	738	if (rval != QLA_SUCCESS) {
	739	+ if (IS_QLA28XX(ha) && rval == QLA_COMMAND_ERROR &&
	740	+ mcp->mb[1] == 0x27 && retry) {
	741	+ semaphore = 1;
	742	+ retry--;
	743	+ ql_dbg(ql_dbg_async, vha, 0x1026,
	744	+ "Exe FW: force semaphore.\n");
	745	+ goto again;
	746	+ }
	747	+
739	748	ql_dbg(ql_dbg_mbx, vha, 0x1026,
740	749	"Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
741		- } else {
742		- if (IS_FWI2_CAPABLE(ha)) {
743		- ha->fw_ability_mask = mcp->mb[3] << 16 \| mcp->mb[2];
744		- ql_dbg(ql_dbg_mbx, vha, 0x119a,
745		- "fw_ability_mask=%x.\n", ha->fw_ability_mask);
746		- ql_dbg(ql_dbg_mbx, vha, 0x1027,
747		- "exchanges=%x.\n", mcp->mb[1]);
748		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha)) {
749		- ha->max_speed_sup = mcp->mb[2] & BIT_0;
750		- ql_dbg(ql_dbg_mbx, vha, 0x119b,
751		- "Maximum speed supported=%s.\n",
752		- ha->max_speed_sup ? "32Gps" : "16Gps");
753		- if (vha->min_link_speed_feat) {
754		- ha->min_link_speed = mcp->mb[5];
755		- ql_dbg(ql_dbg_mbx, vha, 0x119c,
756		- "Minimum speed set=%s.\n",
757		- mcp->mb[5] == 5 ? "32Gps" :
758		- mcp->mb[5] == 4 ? "16Gps" :
759		- mcp->mb[5] == 3 ? "8Gps" :
760		- mcp->mb[5] == 2 ? "4Gps" :
761		- "unknown");
762		- }
763		- }
764		- }
765		- ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
766		- "Done.\n");
	750	+ return rval;
767	751	}
	752	+
	753	+ if (!IS_FWI2_CAPABLE(ha))
	754	+ goto done;
	755	+
	756	+ ha->fw_ability_mask = mcp->mb[3] << 16 \| mcp->mb[2];
	757	+ ql_dbg(ql_dbg_mbx, vha, 0x119a,
	758	+ "fw_ability_mask=%x.\n", ha->fw_ability_mask);
	759	+ ql_dbg(ql_dbg_mbx, vha, 0x1027, "exchanges=%x.\n", mcp->mb[1]);
	760	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
	761	+ ha->max_supported_speed = mcp->mb[2] & (BIT_0\|BIT_1);
	762	+ ql_dbg(ql_dbg_mbx, vha, 0x119b, "max_supported_speed=%s.\n",
	763	+ ha->max_supported_speed == 0 ? "16Gps" :
	764	+ ha->max_supported_speed == 1 ? "32Gps" :
	765	+ ha->max_supported_speed == 2 ? "64Gps" : "unknown");
	766	+ if (vha->min_supported_speed) {
	767	+ ha->min_supported_speed = mcp->mb[5] &
	768	+ (BIT_0 \| BIT_1 \| BIT_2);
	769	+ ql_dbg(ql_dbg_mbx, vha, 0x119c,
	770	+ "min_supported_speed=%s.\n",
	771	+ ha->min_supported_speed == 6 ? "64Gps" :
	772	+ ha->min_supported_speed == 5 ? "32Gps" :
	773	+ ha->min_supported_speed == 4 ? "16Gps" :
	774	+ ha->min_supported_speed == 3 ? "8Gps" :
	775	+ ha->min_supported_speed == 2 ? "4Gps" : "unknown");
	776	+ }
	777	+ }
	778	+
	779	+done:
	780	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
	781	+ "Done %s.\n", __func__);
768	782
769	783	return rval;
770	784	}
..	..	@@ -841,7 +855,7 @@
841	855	* Context:
842	856	* Kernel context.
843	857	*/
844		-#define CONFIG_XLOGINS_MEM 0x3
	858	+#define CONFIG_XLOGINS_MEM 0x9
845	859	int
846	860	qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
847	861	{
..	..	@@ -868,8 +882,9 @@
868	882	mcp->flags = 0;
869	883	rval = qla2x00_mailbox_command(vha, mcp);
870	884	if (rval != QLA_SUCCESS) {
871		- /EMPTY/
872		- ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval);
	885	+ ql_dbg(ql_dbg_mbx, vha, 0x111b,
	886	+ "EXlogin Failed=%x. MB0=%x MB11=%x\n",
	887	+ rval, mcp->mb[0], mcp->mb[11]);
873	888	} else {
874	889	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
875	890	"Done %s.\n", __func__);
..	..	@@ -1021,10 +1036,10 @@
1021	1036	mcp->in_mb \|= MBX_13\|MBX_12\|MBX_11\|MBX_10\|MBX_9\|MBX_8;
1022	1037	if (IS_FWI2_CAPABLE(ha))
1023	1038	mcp->in_mb \|= MBX_17\|MBX_16\|MBX_15;
1024		- if (IS_QLA27XX(ha))
	1039	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
1025	1040	mcp->in_mb \|=
1026	1041	MBX_25\|MBX_24\|MBX_23\|MBX_22\|MBX_21\|MBX_20\|MBX_19\|MBX_18\|
1027		- MBX_14\|MBX_13\|MBX_11\|MBX_10\|MBX_9\|MBX_8;
	1042	+ MBX_14\|MBX_13\|MBX_11\|MBX_10\|MBX_9\|MBX_8\|MBX_7;
1028	1043
1029	1044	mcp->flags = 0;
1030	1045	mcp->tov = MBX_TOV_SECONDS;
..	..	@@ -1077,15 +1092,31 @@
1077	1092	* FW supports nvme and driver load parameter requested nvme.
1078	1093	* BIT 26 of fw_attributes indicates NVMe support.
1079	1094	*/
1080		- if ((ha->fw_attributes_h & 0x400) && ql2xnvmeenable) {
	1095	+ if ((ha->fw_attributes_h &
	1096	+ (FW_ATTR_H_NVME \| FW_ATTR_H_NVME_UPDATED)) &&
	1097	+ ql2xnvmeenable) {
	1098	+ if (ha->fw_attributes_h & FW_ATTR_H_NVME_FBURST)
	1099	+ vha->flags.nvme_first_burst = 1;
	1100	+
1081	1101	vha->flags.nvme_enabled = 1;
1082	1102	ql_log(ql_log_info, vha, 0xd302,
1083	1103	"%s: FC-NVMe is Enabled (0x%x)\n",
1084	1104	__func__, ha->fw_attributes_h);
1085	1105	}
	1106	+
	1107	+ /* BIT_13 of Extended FW Attributes informs about NVMe2 support */
	1108	+ if (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_NVME2) {
	1109	+ ql_log(ql_log_info, vha, 0xd302,
	1110	+ "Firmware supports NVMe2 0x%x\n",
	1111	+ ha->fw_attributes_ext[0]);
	1112	+ vha->flags.nvme2_enabled = 1;
	1113	+ }
1086	1114	}
1087	1115
1088		- if (IS_QLA27XX(ha)) {
	1116	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
	1117	+ ha->serdes_version[0] = mcp->mb[7] & 0xff;
	1118	+ ha->serdes_version[1] = mcp->mb[8] >> 8;
	1119	+ ha->serdes_version[2] = mcp->mb[8] & 0xff;
1089	1120	ha->mpi_version[0] = mcp->mb[10] & 0xff;
1090	1121	ha->mpi_version[1] = mcp->mb[11] >> 8;
1091	1122	ha->mpi_version[2] = mcp->mb[11] & 0xff;
..	..	@@ -1096,6 +1127,31 @@
1096	1127	ha->fw_shared_ram_end = (mcp->mb[21] << 16) \| mcp->mb[20];
1097	1128	ha->fw_ddr_ram_start = (mcp->mb[23] << 16) \| mcp->mb[22];
1098	1129	ha->fw_ddr_ram_end = (mcp->mb[25] << 16) \| mcp->mb[24];
	1130	+ if (IS_QLA28XX(ha)) {
	1131	+ if (mcp->mb[16] & BIT_10)
	1132	+ ha->flags.secure_fw = 1;
	1133	+
	1134	+ ql_log(ql_log_info, vha, 0xffff,
	1135	+ "Secure Flash Update in FW: %s\n",
	1136	+ (ha->flags.secure_fw) ? "Supported" :
	1137	+ "Not Supported");
	1138	+ }
	1139	+
	1140	+ if (ha->flags.scm_supported_a &&
	1141	+ (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_SCM_SUPPORTED)) {
	1142	+ ha->flags.scm_supported_f = 1;
	1143	+ ha->sf_init_cb->flags \|= cpu_to_le16(BIT_13);
	1144	+ }
	1145	+ ql_log(ql_log_info, vha, 0x11a3, "SCM in FW: %s\n",
	1146	+ (ha->flags.scm_supported_f) ? "Supported" :
	1147	+ "Not Supported");
	1148	+
	1149	+ if (vha->flags.nvme2_enabled) {
	1150	+ /* set BIT_15 of special feature control block for SLER */
	1151	+ ha->sf_init_cb->flags \|= cpu_to_le16(BIT_15);
	1152	+ /* set BIT_14 of special feature control block for PI CTRL*/
	1153	+ ha->sf_init_cb->flags \|= cpu_to_le16(BIT_14);
	1154	+ }
1099	1155	}
1100	1156
1101	1157	failed:
..	..	@@ -1358,17 +1414,20 @@
1358	1414	mbx_cmd_t mc;
1359	1415	mbx_cmd_t *mcp = &mc;
1360	1416
	1417	+ if (!vha->hw->flags.fw_started)
	1418	+ return QLA_INVALID_COMMAND;
	1419	+
1361	1420	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
1362	1421	"Entered %s.\n", __func__);
1363	1422
1364	1423	mcp->mb[0] = MBC_IOCB_COMMAND_A64;
1365	1424	mcp->mb[1] = 0;
1366		- mcp->mb[2] = MSW(phys_addr);
1367		- mcp->mb[3] = LSW(phys_addr);
	1425	+ mcp->mb[2] = MSW(LSD(phys_addr));
	1426	+ mcp->mb[3] = LSW(LSD(phys_addr));
1368	1427	mcp->mb[6] = MSW(MSD(phys_addr));
1369	1428	mcp->mb[7] = LSW(MSD(phys_addr));
1370	1429	mcp->out_mb = MBX_7\|MBX_6\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
1371		- mcp->in_mb = MBX_2\|MBX_0;
	1430	+ mcp->in_mb = MBX_1\|MBX_0;
1372	1431	mcp->tov = tov;
1373	1432	mcp->flags = 0;
1374	1433	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -1377,13 +1436,14 @@
1377	1436	/EMPTY/
1378	1437	ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1379	1438	} else {
1380		- sts_entry_t sts_entry = (sts_entry_t ) buffer;
	1439	+ sts_entry_t *sts_entry = buffer;
1381	1440
1382	1441	/* Mask reserved bits. */
1383	1442	sts_entry->entry_status &=
1384	1443	IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
1385	1444	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
1386		- "Done %s.\n", __func__);
	1445	+ "Done %s (status=%x).\n", __func__,
	1446	+ sts_entry->entry_status);
1387	1447	}
1388	1448
1389	1449	return rval;
..	..	@@ -1428,7 +1488,7 @@
1428	1488	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
1429	1489	"Entered %s.\n", __func__);
1430	1490
1431		- if (vha->flags.qpairs_available && sp->qpair)
	1491	+ if (sp->qpair)
1432	1492	req = sp->qpair->req;
1433	1493	else
1434	1494	req = vha->req;
..	..	@@ -1476,17 +1536,12 @@
1476	1536	mbx_cmd_t mc;
1477	1537	mbx_cmd_t *mcp = &mc;
1478	1538	scsi_qla_host_t *vha;
1479		- struct req_que *req;
1480		- struct rsp_que *rsp;
1481	1539
1482		- l = l;
1483	1540	vha = fcport->vha;
1484	1541
1485	1542	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
1486	1543	"Entered %s.\n", __func__);
1487	1544
1488		- req = vha->hw->req_q_map[0];
1489		- rsp = req->rsp;
1490	1545	mcp->mb[0] = MBC_ABORT_TARGET;
1491	1546	mcp->out_mb = MBX_9\|MBX_2\|MBX_1\|MBX_0;
1492	1547	if (HAS_EXTENDED_IDS(vha->hw)) {
..	..	@@ -1509,7 +1564,7 @@
1509	1564	}
1510	1565
1511	1566	/* Issue marker IOCB. */
1512		- rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
	1567	+ rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, 0,
1513	1568	MK_SYNC_ID);
1514	1569	if (rval2 != QLA_SUCCESS) {
1515	1570	ql_dbg(ql_dbg_mbx, vha, 0x1040,
..	..	@@ -1529,16 +1584,12 @@
1529	1584	mbx_cmd_t mc;
1530	1585	mbx_cmd_t *mcp = &mc;
1531	1586	scsi_qla_host_t *vha;
1532		- struct req_que *req;
1533		- struct rsp_que *rsp;
1534	1587
1535	1588	vha = fcport->vha;
1536	1589
1537	1590	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1538	1591	"Entered %s.\n", __func__);
1539	1592
1540		- req = vha->hw->req_q_map[0];
1541		- rsp = req->rsp;
1542	1593	mcp->mb[0] = MBC_LUN_RESET;
1543	1594	mcp->out_mb = MBX_9\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
1544	1595	if (HAS_EXTENDED_IDS(vha->hw))
..	..	@@ -1558,7 +1609,7 @@
1558	1609	}
1559	1610
1560	1611	/* Issue marker IOCB. */
1561		- rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
	1612	+ rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, l,
1562	1613	MK_SYNC_ID_LUN);
1563	1614	if (rval2 != QLA_SUCCESS) {
1564	1615	ql_dbg(ql_dbg_mbx, vha, 0x1044,
..	..	@@ -1610,8 +1661,9 @@
1610	1661	mcp->in_mb \|= MBX_13\|MBX_12\|MBX_11\|MBX_10;
1611	1662	if (IS_FWI2_CAPABLE(vha->hw))
1612	1663	mcp->in_mb \|= MBX_19\|MBX_18\|MBX_17\|MBX_16;
1613		- if (IS_QLA27XX(vha->hw))
1614		- mcp->in_mb \|= MBX_15;
	1664	+ if (IS_QLA27XX(vha->hw) \|\| IS_QLA28XX(vha->hw))
	1665	+ mcp->in_mb \|= MBX_15\|MBX_21\|MBX_22\|MBX_23;
	1666	+
1615	1667	mcp->tov = MBX_TOV_SECONDS;
1616	1668	mcp->flags = 0;
1617	1669	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -1664,8 +1716,22 @@
1664	1716	}
1665	1717	}
1666	1718
1667		- if (IS_QLA27XX(vha->hw))
	1719	+ if (IS_QLA27XX(vha->hw) \|\| IS_QLA28XX(vha->hw)) {
1668	1720	vha->bbcr = mcp->mb[15];
	1721	+ if (mcp->mb[7] & SCM_EDC_ACC_RECEIVED) {
	1722	+ ql_log(ql_log_info, vha, 0x11a4,
	1723	+ "SCM: EDC ELS completed, flags 0x%x\n",
	1724	+ mcp->mb[21]);
	1725	+ }
	1726	+ if (mcp->mb[7] & SCM_RDF_ACC_RECEIVED) {
	1727	+ vha->hw->flags.scm_enabled = 1;
	1728	+ vha->scm_fabric_connection_flags \|=
	1729	+ SCM_FLAG_RDF_COMPLETED;
	1730	+ ql_log(ql_log_info, vha, 0x11a5,
	1731	+ "SCM: RDF ELS completed, flags 0x%x\n",
	1732	+ mcp->mb[23]);
	1733	+ }
	1734	+ }
1669	1735	}
1670	1736
1671	1737	return rval;
..	..	@@ -1778,9 +1844,20 @@
1778	1844	mcp->mb[14] = sizeof(*ha->ex_init_cb);
1779	1845	mcp->out_mb \|= MBX_14\|MBX_13\|MBX_12\|MBX_11\|MBX_10;
1780	1846	}
	1847	+
	1848	+ if (ha->flags.scm_supported_f \|\| vha->flags.nvme2_enabled) {
	1849	+ mcp->mb[1] \|= BIT_1;
	1850	+ mcp->mb[16] = MSW(ha->sf_init_cb_dma);
	1851	+ mcp->mb[17] = LSW(ha->sf_init_cb_dma);
	1852	+ mcp->mb[18] = MSW(MSD(ha->sf_init_cb_dma));
	1853	+ mcp->mb[19] = LSW(MSD(ha->sf_init_cb_dma));
	1854	+ mcp->mb[15] = sizeof(*ha->sf_init_cb);
	1855	+ mcp->out_mb \|= MBX_19\|MBX_18\|MBX_17\|MBX_16\|MBX_15;
	1856	+ }
	1857	+
1781	1858	/* 1 and 2 should normally be captured. */
1782	1859	mcp->in_mb = MBX_2\|MBX_1\|MBX_0;
1783		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	1860	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
1784	1861	/* mb3 is additional info about the installed SFP. */
1785	1862	mcp->in_mb \|= MBX_3;
1786	1863	mcp->buf_size = size;
..	..	@@ -1791,10 +1868,20 @@
1791	1868	if (rval != QLA_SUCCESS) {
1792	1869	/EMPTY/
1793	1870	ql_dbg(ql_dbg_mbx, vha, 0x104d,
1794		- "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
	1871	+ "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x.\n",
1795	1872	rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
	1873	+ if (ha->init_cb) {
	1874	+ ql_dbg(ql_dbg_mbx, vha, 0x104d, "init_cb:\n");
	1875	+ ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
	1876	+ 0x0104d, ha->init_cb, sizeof(*ha->init_cb));
	1877	+ }
	1878	+ if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
	1879	+ ql_dbg(ql_dbg_mbx, vha, 0x104d, "ex_init_cb:\n");
	1880	+ ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
	1881	+ 0x0104d, ha->ex_init_cb, sizeof(*ha->ex_init_cb));
	1882	+ }
1796	1883	} else {
1797		- if (IS_QLA27XX(ha)) {
	1884	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
1798	1885	if (mcp->mb[2] == 6 \|\| mcp->mb[3] == 2)
1799	1886	ql_dbg(ql_dbg_mbx, vha, 0x119d,
1800	1887	"Invalid SFP/Validation Failed\n");
..	..	@@ -1884,7 +1971,7 @@
1884	1971	pd24 = (struct port_database_24xx *) pd;
1885	1972
1886	1973	/* Check for logged in state. */
1887		- if (fcport->fc4f_nvme) {
	1974	+ if (NVME_TARGET(ha, fcport)) {
1888	1975	current_login_state = pd24->current_login_state >> 4;
1889	1976	last_login_state = pd24->last_login_state >> 4;
1890	1977	} else {
..	..	@@ -1978,7 +2065,7 @@
1978	2065
1979	2066	/* Passback COS information. */
1980	2067	fcport->supported_classes = (pd->options & BIT_4) ?
1981		- FC_COS_CLASS2: FC_COS_CLASS3;
	2068	+ FC_COS_CLASS2 : FC_COS_CLASS3;
1982	2069	}
1983	2070
1984	2071	gpd_error_out:
..	..	@@ -1993,6 +2080,57 @@
1993	2080	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
1994	2081	"Done %s.\n", __func__);
1995	2082	}
	2083	+
	2084	+ return rval;
	2085	+}
	2086	+
	2087	+int
	2088	+qla24xx_get_port_database(scsi_qla_host_t *vha, u16 nport_handle,
	2089	+ struct port_database_24xx *pdb)
	2090	+{
	2091	+ mbx_cmd_t mc;
	2092	+ mbx_cmd_t *mcp = &mc;
	2093	+ dma_addr_t pdb_dma;
	2094	+ int rval;
	2095	+
	2096	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1115,
	2097	+ "Entered %s.\n", __func__);
	2098	+
	2099	+ memset(pdb, 0, sizeof(*pdb));
	2100	+
	2101	+ pdb_dma = dma_map_single(&vha->hw->pdev->dev, pdb,
	2102	+ sizeof(*pdb), DMA_FROM_DEVICE);
	2103	+ if (!pdb_dma) {
	2104	+ ql_log(ql_log_warn, vha, 0x1116, "Failed to map dma buffer.\n");
	2105	+ return QLA_MEMORY_ALLOC_FAILED;
	2106	+ }
	2107	+
	2108	+ mcp->mb[0] = MBC_GET_PORT_DATABASE;
	2109	+ mcp->mb[1] = nport_handle;
	2110	+ mcp->mb[2] = MSW(LSD(pdb_dma));
	2111	+ mcp->mb[3] = LSW(LSD(pdb_dma));
	2112	+ mcp->mb[6] = MSW(MSD(pdb_dma));
	2113	+ mcp->mb[7] = LSW(MSD(pdb_dma));
	2114	+ mcp->mb[9] = 0;
	2115	+ mcp->mb[10] = 0;
	2116	+ mcp->out_mb = MBX_10\|MBX_9\|MBX_7\|MBX_6\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
	2117	+ mcp->in_mb = MBX_1\|MBX_0;
	2118	+ mcp->buf_size = sizeof(*pdb);
	2119	+ mcp->flags = MBX_DMA_IN;
	2120	+ mcp->tov = vha->hw->login_timeout * 2;
	2121	+ rval = qla2x00_mailbox_command(vha, mcp);
	2122	+
	2123	+ if (rval != QLA_SUCCESS) {
	2124	+ ql_dbg(ql_dbg_mbx, vha, 0x111a,
	2125	+ "Failed=%x mb[0]=%x mb[1]=%x.\n",
	2126	+ rval, mcp->mb[0], mcp->mb[1]);
	2127	+ } else {
	2128	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111b,
	2129	+ "Done %s.\n", __func__);
	2130	+ }
	2131	+
	2132	+ dma_unmap_single(&vha->hw->pdev->dev, pdb_dma,
	2133	+ sizeof(*pdb), DMA_FROM_DEVICE);
1996	2134
1997	2135	return rval;
1998	2136	}
..	..	@@ -2048,7 +2186,7 @@
2048	2186	/EMPTY/
2049	2187	ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
2050	2188	} else {
2051		- if (IS_QLA27XX(ha)) {
	2189	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
2052	2190	if (mcp->mb[2] == 6 \|\| mcp->mb[3] == 2)
2053	2191	ql_dbg(ql_dbg_mbx, vha, 0x119e,
2054	2192	"Invalid SFP/Validation Failed\n");
..	..	@@ -2202,7 +2340,7 @@
2202	2340	mbx_cmd_t mc;
2203	2341	mbx_cmd_t *mcp = &mc;
2204	2342
2205		- ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
	2343	+ ql_dbg(ql_dbg_disc, vha, 0x105a,
2206	2344	"Entered %s.\n", __func__);
2207	2345
2208	2346	if (IS_CNA_CAPABLE(vha->hw)) {
..	..	@@ -2213,10 +2351,7 @@
2213	2351	mcp->out_mb = MBX_2\|MBX_1\|MBX_0;
2214	2352	} else if (IS_FWI2_CAPABLE(vha->hw)) {
2215	2353	mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2216		- if (N2N_TOPO(vha->hw))
2217		- mcp->mb[1] = BIT_4; /* re-init */
2218		- else
2219		- mcp->mb[1] = BIT_6; /* LIP */
	2354	+ mcp->mb[1] = BIT_4;
2220	2355	mcp->mb[2] = 0;
2221	2356	mcp->mb[3] = vha->hw->loop_reset_delay;
2222	2357	mcp->out_mb = MBX_3\|MBX_2\|MBX_1\|MBX_0;
..	..	@@ -2339,7 +2474,7 @@
2339	2474
2340	2475	lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2341	2476	lg->entry_count = 1;
2342		- lg->handle = MAKE_HANDLE(req->id, lg->handle);
	2477	+ lg->handle = make_handle(req->id, lg->handle);
2343	2478	lg->nport_handle = cpu_to_le16(loop_id);
2344	2479	lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
2345	2480	if (opt & BIT_0)
..	..	@@ -2609,7 +2744,7 @@
2609	2744	req = vha->req;
2610	2745	lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2611	2746	lg->entry_count = 1;
2612		- lg->handle = MAKE_HANDLE(req->id, lg->handle);
	2747	+ lg->handle = make_handle(req->id, lg->handle);
2613	2748	lg->nport_handle = cpu_to_le16(loop_id);
2614	2749	lg->control_flags =
2615	2750	cpu_to_le16(LCF_COMMAND_LOGO\|LCF_IMPL_LOGO\|
..	..	@@ -2726,7 +2861,7 @@
2726	2861	"Entered %s.\n", __func__);
2727	2862
2728	2863	mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2729		- mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
	2864	+ mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_4 : 0;
2730	2865	mcp->mb[2] = 0;
2731	2866	mcp->mb[3] = 0;
2732	2867	mcp->out_mb = MBX_3\|MBX_2\|MBX_1\|MBX_0;
..	..	@@ -2834,7 +2969,8 @@
2834	2969	mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2835	2970	mcp->out_mb = MBX_0;
2836	2971	mcp->in_mb = MBX_11\|MBX_10\|MBX_7\|MBX_6\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
2837		- if (IS_QLA81XX(vha->hw) \|\| IS_QLA83XX(vha->hw) \|\| IS_QLA27XX(vha->hw))
	2972	+ if (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\|
	2973	+ IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
2838	2974	mcp->in_mb \|= MBX_12;
2839	2975	mcp->tov = MBX_TOV_SECONDS;
2840	2976	mcp->flags = 0;
..	..	@@ -2859,7 +2995,7 @@
2859	2995	ha->orig_fw_iocb_count = mcp->mb[10];
2860	2996	if (ha->flags.npiv_supported)
2861	2997	ha->max_npiv_vports = mcp->mb[11];
2862		- if (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	2998	+ if (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha))
2863	2999	ha->fw_max_fcf_count = mcp->mb[12];
2864	3000	}
2865	3001
..	..	@@ -2881,7 +3017,8 @@
2881	3017	* Kernel context.
2882	3018	*/
2883	3019	int
2884		-qla2x00_get_fcal_position_map(scsi_qla_host_t vha, char pos_map)
	3020	+qla2x00_get_fcal_position_map(scsi_qla_host_t vha, char pos_map,
	3021	+ u8 *num_entries)
2885	3022	{
2886	3023	int rval;
2887	3024	mbx_cmd_t mc;
..	..	@@ -2921,6 +3058,8 @@
2921	3058
2922	3059	if (pos_map)
2923	3060	memcpy(pos_map, pmap, FCAL_MAP_SIZE);
	3061	+ if (num_entries)
	3062	+ *num_entries = pmap[0];
2924	3063	}
2925	3064	dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2926	3065
..	..	@@ -2954,7 +3093,7 @@
2954	3093	int rval;
2955	3094	mbx_cmd_t mc;
2956	3095	mbx_cmd_t *mcp = &mc;
2957		- uint32_t iter = (void )stats;
	3096	+ uint32_t iter = (uint32_t )stats;
2958	3097	ushort dwords = offsetof(typeof(stats), link_up_cnt)/sizeof(iter);
2959	3098	struct qla_hw_data *ha = vha->hw;
2960	3099
..	..	@@ -3013,20 +3152,21 @@
3013	3152	int rval;
3014	3153	mbx_cmd_t mc;
3015	3154	mbx_cmd_t *mcp = &mc;
3016		- uint32_t *iter, dwords;
	3155	+ uint32_t iter = (uint32_t )stats;
	3156	+ ushort dwords = sizeof(stats)/sizeof(iter);
3017	3157
3018	3158	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
3019	3159	"Entered %s.\n", __func__);
3020	3160
3021	3161	memset(&mc, 0, sizeof(mc));
3022	3162	mc.mb[0] = MBC_GET_LINK_PRIV_STATS;
3023		- mc.mb[2] = MSW(stats_dma);
3024		- mc.mb[3] = LSW(stats_dma);
	3163	+ mc.mb[2] = MSW(LSD(stats_dma));
	3164	+ mc.mb[3] = LSW(LSD(stats_dma));
3025	3165	mc.mb[6] = MSW(MSD(stats_dma));
3026	3166	mc.mb[7] = LSW(MSD(stats_dma));
3027		- mc.mb[8] = sizeof(struct link_statistics) / 4;
3028		- mc.mb[9] = cpu_to_le16(vha->vp_idx);
3029		- mc.mb[10] = cpu_to_le16(options);
	3167	+ mc.mb[8] = dwords;
	3168	+ mc.mb[9] = vha->vp_idx;
	3169	+ mc.mb[10] = options;
3030	3170
3031	3171	rval = qla24xx_send_mb_cmd(vha, &mc);
3032	3172
..	..	@@ -3039,8 +3179,6 @@
3039	3179	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
3040	3180	"Done %s.\n", __func__);
3041	3181	/* Re-endianize - firmware data is le32. */
3042		- dwords = sizeof(struct link_statistics) / 4;
3043		- iter = &stats->link_fail_cnt;
3044	3182	for ( ; dwords--; iter++)
3045	3183	le32_to_cpus(iter);
3046	3184	}
..	..	@@ -3065,22 +3203,25 @@
3065	3203	struct scsi_qla_host *vha = fcport->vha;
3066	3204	struct qla_hw_data *ha = vha->hw;
3067	3205	struct req_que *req = vha->req;
	3206	+ struct qla_qpair *qpair = sp->qpair;
3068	3207
3069	3208	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
3070	3209	"Entered %s.\n", __func__);
3071	3210
3072	3211	if (sp->qpair)
3073	3212	req = sp->qpair->req;
	3213	+ else
	3214	+ return QLA_FUNCTION_FAILED;
3074	3215
3075	3216	if (ql2xasynctmfenable)
3076	3217	return qla24xx_async_abort_command(sp);
3077	3218
3078		- spin_lock_irqsave(&ha->hardware_lock, flags);
	3219	+ spin_lock_irqsave(qpair->qp_lock_ptr, flags);
3079	3220	for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
3080	3221	if (req->outstanding_cmds[handle] == sp)
3081	3222	break;
3082	3223	}
3083		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
	3224	+ spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
3084	3225	if (handle == req->num_outstanding_cmds) {
3085	3226	/* Command not found. */
3086	3227	return QLA_FUNCTION_FAILED;
..	..	@@ -3095,9 +3236,9 @@
3095	3236
3096	3237	abt->entry_type = ABORT_IOCB_TYPE;
3097	3238	abt->entry_count = 1;
3098		- abt->handle = MAKE_HANDLE(req->id, abt->handle);
	3239	+ abt->handle = make_handle(req->id, abt->handle);
3099	3240	abt->nport_handle = cpu_to_le16(fcport->loop_id);
3100		- abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
	3241	+ abt->handle_to_abort = make_handle(req->id, handle);
3101	3242	abt->port_id[0] = fcport->d_id.b.al_pa;
3102	3243	abt->port_id[1] = fcport->d_id.b.area;
3103	3244	abt->port_id[2] = fcport->d_id.b.domain;
..	..	@@ -3118,7 +3259,7 @@
3118	3259	ql_dbg(ql_dbg_mbx, vha, 0x1090,
3119	3260	"Failed to complete IOCB -- completion status (%x).\n",
3120	3261	le16_to_cpu(abt->nport_handle));
3121		- if (abt->nport_handle == CS_IOCB_ERROR)
	3262	+ if (abt->nport_handle == cpu_to_le16(CS_IOCB_ERROR))
3122	3263	rval = QLA_FUNCTION_PARAMETER_ERROR;
3123	3264	else
3124	3265	rval = QLA_FUNCTION_FAILED;
..	..	@@ -3150,7 +3291,6 @@
3150	3291	scsi_qla_host_t *vha;
3151	3292	struct qla_hw_data *ha;
3152	3293	struct req_que *req;
3153		- struct rsp_que *rsp;
3154	3294	struct qla_qpair *qpair;
3155	3295
3156	3296	vha = fcport->vha;
..	..	@@ -3163,10 +3303,7 @@
3163	3303	if (vha->vp_idx && vha->qpair) {
3164	3304	/* NPIV port */
3165	3305	qpair = vha->qpair;
3166		- rsp = qpair->rsp;
3167	3306	req = qpair->req;
3168		- } else {
3169		- rsp = req->rsp;
3170	3307	}
3171	3308
3172	3309	tsk = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
..	..	@@ -3178,7 +3315,7 @@
3178	3315
3179	3316	tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
3180	3317	tsk->p.tsk.entry_count = 1;
3181		- tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
	3318	+ tsk->p.tsk.handle = make_handle(req->id, tsk->p.tsk.handle);
3182	3319	tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
3183	3320	tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
3184	3321	tsk->p.tsk.control_flags = cpu_to_le32(type);
..	..	@@ -3223,8 +3360,8 @@
3223	3360	}
3224	3361
3225	3362	/* Issue marker IOCB. */
3226		- rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
3227		- type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
	3363	+ rval2 = qla2x00_marker(vha, ha->base_qpair, fcport->loop_id, l,
	3364	+ type == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
3228	3365	if (rval2 != QLA_SUCCESS) {
3229	3366	ql_dbg(ql_dbg_mbx, vha, 0x1099,
3230	3367	"Failed to issue marker IOCB (%x).\n", rval2);
..	..	@@ -3299,7 +3436,7 @@
3299	3436	mbx_cmd_t *mcp = &mc;
3300	3437
3301	3438	if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3302		- !IS_QLA27XX(vha->hw))
	3439	+ !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
3303	3440	return QLA_FUNCTION_FAILED;
3304	3441
3305	3442	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
..	..	@@ -3338,7 +3475,7 @@
3338	3475	mbx_cmd_t *mcp = &mc;
3339	3476
3340	3477	if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3341		- !IS_QLA27XX(vha->hw))
	3478	+ !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
3342	3479	return QLA_FUNCTION_FAILED;
3343	3480
3344	3481	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
..	..	@@ -3444,9 +3581,9 @@
3444	3581	/**
3445	3582	* qla2x00_set_serdes_params() -
3446	3583	* @vha: HA context
3447		- * @sw_em_1g:
3448		- * @sw_em_2g:
3449		- * @sw_em_4g:
	3584	+ * @sw_em_1g: serial link options
	3585	+ * @sw_em_2g: serial link options
	3586	+ * @sw_em_4g: serial link options
3450	3587	*
3451	3588	* Returns
3452	3589	*/
..	..	@@ -3607,7 +3744,8 @@
3607	3744	"Entered %s.\n", __func__);
3608	3745
3609	3746	if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
3610		- !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
	3747	+ !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
	3748	+ !IS_QLA28XX(vha->hw))
3611	3749	return QLA_FUNCTION_FAILED;
3612	3750
3613	3751	if (unlikely(pci_channel_offline(vha->hw->pdev)))
..	..	@@ -3720,7 +3858,7 @@
3720	3858	rval = qla2x00_mailbox_command(vha, mcp);
3721	3859
3722	3860	/* Return mailbox statuses. */
3723		- if (mb != NULL) {
	3861	+ if (mb) {
3724	3862	mb[0] = mcp->mb[0];
3725	3863	mb[1] = mcp->mb[1];
3726	3864	mb[3] = mcp->mb[3];
..	..	@@ -3755,7 +3893,7 @@
3755	3893	mcp->mb[0] = MBC_PORT_PARAMS;
3756	3894	mcp->mb[1] = loop_id;
3757	3895	mcp->mb[2] = BIT_0;
3758		- mcp->mb[3] = port_speed & (BIT_5\|BIT_4\|BIT_3\|BIT_2\|BIT_1\|BIT_0);
	3896	+ mcp->mb[3] = port_speed & 0x3F;
3759	3897	mcp->mb[9] = vha->vp_idx;
3760	3898	mcp->out_mb = MBX_9\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
3761	3899	mcp->in_mb = MBX_3\|MBX_1\|MBX_0;
..	..	@@ -3764,7 +3902,7 @@
3764	3902	rval = qla2x00_mailbox_command(vha, mcp);
3765	3903
3766	3904	/* Return mailbox statuses. */
3767		- if (mb != NULL) {
	3905	+ if (mb) {
3768	3906	mb[0] = mcp->mb[0];
3769	3907	mb[1] = mcp->mb[1];
3770	3908	mb[3] = mcp->mb[3];
..	..	@@ -3837,14 +3975,46 @@
3837	3975	case TOPO_N2N:
3838	3976	ha->current_topology = ISP_CFG_N;
3839	3977	spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
	3978	+ list_for_each_entry(fcport, &vha->vp_fcports, list) {
	3979	+ fcport->scan_state = QLA_FCPORT_SCAN;
	3980	+ fcport->n2n_flag = 0;
	3981	+ }
	3982	+ id.b24 = 0;
	3983	+ if (wwn_to_u64(vha->port_name) >
	3984	+ wwn_to_u64(rptid_entry->u.f1.port_name)) {
	3985	+ vha->d_id.b24 = 0;
	3986	+ vha->d_id.b.al_pa = 1;
	3987	+ ha->flags.n2n_bigger = 1;
	3988	+
	3989	+ id.b.al_pa = 2;
	3990	+ ql_dbg(ql_dbg_async, vha, 0x5075,
	3991	+ "Format 1: assign local id %x remote id %x\n",
	3992	+ vha->d_id.b24, id.b24);
	3993	+ } else {
	3994	+ ql_dbg(ql_dbg_async, vha, 0x5075,
	3995	+ "Format 1: Remote login - Waiting for WWPN %8phC.\n",
	3996	+ rptid_entry->u.f1.port_name);
	3997	+ ha->flags.n2n_bigger = 0;
	3998	+ }
	3999	+
3840	4000	fcport = qla2x00_find_fcport_by_wwpn(vha,
3841	4001	rptid_entry->u.f1.port_name, 1);
3842	4002	spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
3843	4003
	4004	+
3844	4005	if (fcport) {
3845	4006	fcport->plogi_nack_done_deadline = jiffies + HZ;
3846		- fcport->dm_login_expire = jiffies + 3*HZ;
	4007	+ fcport->dm_login_expire = jiffies +
	4008	+ QLA_N2N_WAIT_TIME * HZ;
3847	4009	fcport->scan_state = QLA_FCPORT_FOUND;
	4010	+ fcport->n2n_flag = 1;
	4011	+ fcport->keep_nport_handle = 1;
	4012	+
	4013	+ if (wwn_to_u64(vha->port_name) >
	4014	+ wwn_to_u64(fcport->port_name)) {
	4015	+ fcport->d_id = id;
	4016	+ }
	4017	+
3848	4018	switch (fcport->disc_state) {
3849	4019	case DSC_DELETED:
3850	4020	set_bit(RELOGIN_NEEDED,
..	..	@@ -3857,30 +4027,11 @@
3857	4027	break;
3858	4028	}
3859	4029	} else {
3860		- id.b24 = 0;
3861		- if (wwn_to_u64(vha->port_name) >
3862		- wwn_to_u64(rptid_entry->u.f1.port_name)) {
3863		- vha->d_id.b24 = 0;
3864		- vha->d_id.b.al_pa = 1;
3865		- ha->flags.n2n_bigger = 1;
3866		- ha->flags.n2n_ae = 0;
3867		-
3868		- id.b.al_pa = 2;
3869		- ql_dbg(ql_dbg_async, vha, 0x5075,
3870		- "Format 1: assign local id %x remote id %x\n",
3871		- vha->d_id.b24, id.b24);
3872		- } else {
3873		- ql_dbg(ql_dbg_async, vha, 0x5075,
3874		- "Format 1: Remote login - Waiting for WWPN %8phC.\n",
3875		- rptid_entry->u.f1.port_name);
3876		- ha->flags.n2n_bigger = 0;
3877		- ha->flags.n2n_ae = 1;
3878		- }
3879	4030	qla24xx_post_newsess_work(vha, &id,
3880	4031	rptid_entry->u.f1.port_name,
3881	4032	rptid_entry->u.f1.node_name,
3882	4033	NULL,
3883		- FC4_TYPE_UNKNOWN);
	4034	+ FS_FCP_IS_N2N);
3884	4035	}
3885	4036
3886	4037	/* if our portname is higher then initiate N2N login */
..	..	@@ -3978,6 +4129,7 @@
3978	4129
3979	4130	list_for_each_entry(fcport, &vha->vp_fcports, list) {
3980	4131	fcport->scan_state = QLA_FCPORT_SCAN;
	4132	+ fcport->n2n_flag = 0;
3981	4133	}
3982	4134
3983	4135	fcport = qla2x00_find_fcport_by_wwpn(vha,
..	..	@@ -3987,6 +4139,14 @@
3987	4139	fcport->login_retry = vha->hw->login_retry_count;
3988	4140	fcport->plogi_nack_done_deadline = jiffies + HZ;
3989	4141	fcport->scan_state = QLA_FCPORT_FOUND;
	4142	+ fcport->keep_nport_handle = 1;
	4143	+ fcport->n2n_flag = 1;
	4144	+ fcport->d_id.b.domain =
	4145	+ rptid_entry->u.f2.remote_nport_id[2];
	4146	+ fcport->d_id.b.area =
	4147	+ rptid_entry->u.f2.remote_nport_id[1];
	4148	+ fcport->d_id.b.al_pa =
	4149	+ rptid_entry->u.f2.remote_nport_id[0];
3990	4150	}
3991	4151	}
3992	4152	}
..	..	@@ -4128,7 +4288,8 @@
4128	4288	if (MSW(addr) \|\| IS_FWI2_CAPABLE(vha->hw)) {
4129	4289	mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
4130	4290	mcp->mb[8] = MSW(addr);
4131		- mcp->out_mb = MBX_8\|MBX_0;
	4291	+ mcp->mb[10] = 0;
	4292	+ mcp->out_mb = MBX_10\|MBX_8\|MBX_0;
4132	4293	} else {
4133	4294	mcp->mb[0] = MBC_DUMP_RISC_RAM;
4134	4295	mcp->out_mb = MBX_0;
..	..	@@ -4207,7 +4368,7 @@
4207	4368	ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
4208	4369	"Dump of Verify Request.\n");
4209	4370	ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
4210		- (uint8_t )mn, sizeof(mn));
	4371	+ mn, sizeof(*mn));
4211	4372
4212	4373	rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4213	4374	if (rval != QLA_SUCCESS) {
..	..	@@ -4219,7 +4380,7 @@
4219	4380	ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
4220	4381	"Dump of Verify Response.\n");
4221	4382	ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
4222		- (uint8_t )mn, sizeof(mn));
	4383	+ mn, sizeof(*mn));
4223	4384
4224	4385	status[0] = le16_to_cpu(mn->p.rsp.comp_status);
4225	4386	status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
..	..	@@ -4295,7 +4456,7 @@
4295	4456	mcp->mb[12] = req->qos;
4296	4457	mcp->mb[11] = req->vp_idx;
4297	4458	mcp->mb[13] = req->rid;
4298		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	4459	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
4299	4460	mcp->mb[15] = 0;
4300	4461
4301	4462	mcp->mb[4] = req->id;
..	..	@@ -4309,9 +4470,10 @@
4309	4470	mcp->flags = MBX_DMA_OUT;
4310	4471	mcp->tov = MBX_TOV_SECONDS * 2;
4311	4472
4312		- if (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	4473	+ if (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\|
	4474	+ IS_QLA28XX(ha))
4313	4475	mcp->in_mb \|= MBX_1;
4314		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha)) {
	4476	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
4315	4477	mcp->out_mb \|= MBX_15;
4316	4478	/* debug q create issue in SR-IOV */
4317	4479	mcp->in_mb \|= MBX_9 \| MBX_8 \| MBX_7;
..	..	@@ -4319,9 +4481,9 @@
4319	4481
4320	4482	spin_lock_irqsave(&ha->hardware_lock, flags);
4321	4483	if (!(req->options & BIT_0)) {
4322		- WRT_REG_DWORD(req->req_q_in, 0);
4323		- if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
4324		- WRT_REG_DWORD(req->req_q_out, 0);
	4484	+ wrt_reg_dword(req->req_q_in, 0);
	4485	+ if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
	4486	+ wrt_reg_dword(req->req_q_out, 0);
4325	4487	}
4326	4488	spin_unlock_irqrestore(&ha->hardware_lock, flags);
4327	4489
..	..	@@ -4364,7 +4526,7 @@
4364	4526	mcp->mb[5] = rsp->length;
4365	4527	mcp->mb[14] = rsp->msix->entry;
4366	4528	mcp->mb[13] = rsp->rid;
4367		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	4529	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
4368	4530	mcp->mb[15] = 0;
4369	4531
4370	4532	mcp->mb[4] = rsp->id;
..	..	@@ -4381,7 +4543,7 @@
4381	4543	if (IS_QLA81XX(ha)) {
4382	4544	mcp->out_mb \|= MBX_12\|MBX_11\|MBX_10;
4383	4545	mcp->in_mb \|= MBX_1;
4384		- } else if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha)) {
	4546	+ } else if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
4385	4547	mcp->out_mb \|= MBX_15\|MBX_12\|MBX_11\|MBX_10;
4386	4548	mcp->in_mb \|= MBX_1;
4387	4549	/* debug q create issue in SR-IOV */
..	..	@@ -4390,9 +4552,9 @@
4390	4552
4391	4553	spin_lock_irqsave(&ha->hardware_lock, flags);
4392	4554	if (!(rsp->options & BIT_0)) {
4393		- WRT_REG_DWORD(rsp->rsp_q_out, 0);
4394		- if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
4395		- WRT_REG_DWORD(rsp->rsp_q_in, 0);
	4555	+ wrt_reg_dword(rsp->rsp_q_out, 0);
	4556	+ if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
	4557	+ wrt_reg_dword(rsp->rsp_q_in, 0);
4396	4558	}
4397	4559
4398	4560	spin_unlock_irqrestore(&ha->hardware_lock, flags);
..	..	@@ -4449,7 +4611,7 @@
4449	4611	"Entered %s.\n", __func__);
4450	4612
4451	4613	if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4452		- !IS_QLA27XX(vha->hw))
	4614	+ !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
4453	4615	return QLA_FUNCTION_FAILED;
4454	4616
4455	4617	mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
..	..	@@ -4481,7 +4643,7 @@
4481	4643	mbx_cmd_t *mcp = &mc;
4482	4644
4483	4645	if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4484		- !IS_QLA27XX(vha->hw))
	4646	+ !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
4485	4647	return QLA_FUNCTION_FAILED;
4486	4648
4487	4649	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
..	..	@@ -4516,7 +4678,7 @@
4516	4678	mbx_cmd_t *mcp = &mc;
4517	4679
4518	4680	if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4519		- !IS_QLA27XX(vha->hw))
	4681	+ !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
4520	4682	return QLA_FUNCTION_FAILED;
4521	4683
4522	4684	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
..	..	@@ -4530,6 +4692,42 @@
4530	4692	mcp->mb[5] = MSW(finish);
4531	4693	mcp->out_mb = MBX_5\|MBX_4\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
4532	4694	mcp->in_mb = MBX_2\|MBX_1\|MBX_0;
	4695	+ mcp->tov = MBX_TOV_SECONDS;
	4696	+ mcp->flags = 0;
	4697	+ rval = qla2x00_mailbox_command(vha, mcp);
	4698	+
	4699	+ if (rval != QLA_SUCCESS) {
	4700	+ ql_dbg(ql_dbg_mbx, vha, 0x10e3,
	4701	+ "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
	4702	+ rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
	4703	+ } else {
	4704	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
	4705	+ "Done %s.\n", __func__);
	4706	+ }
	4707	+
	4708	+ return rval;
	4709	+}
	4710	+
	4711	+int
	4712	+qla81xx_fac_semaphore_access(scsi_qla_host_t *vha, int lock)
	4713	+{
	4714	+ int rval = QLA_SUCCESS;
	4715	+ mbx_cmd_t mc;
	4716	+ mbx_cmd_t *mcp = &mc;
	4717	+ struct qla_hw_data *ha = vha->hw;
	4718	+
	4719	+ if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
	4720	+ !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
	4721	+ return rval;
	4722	+
	4723	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
	4724	+ "Entered %s.\n", __func__);
	4725	+
	4726	+ mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
	4727	+ mcp->mb[1] = (lock ? FAC_OPT_CMD_LOCK_SEMAPHORE :
	4728	+ FAC_OPT_CMD_UNLOCK_SEMAPHORE);
	4729	+ mcp->out_mb = MBX_1\|MBX_0;
	4730	+ mcp->in_mb = MBX_1\|MBX_0;
4533	4731	mcp->tov = MBX_TOV_SECONDS;
4534	4732	mcp->flags = 0;
4535	4733	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -4583,7 +4781,7 @@
4583	4781	mbx_cmd_t *mcp = &mc;
4584	4782	int i;
4585	4783	int len;
4586		- uint16_t *str;
	4784	+ __le16 *str;
4587	4785	struct qla_hw_data *ha = vha->hw;
4588	4786
4589	4787	if (!IS_P3P_TYPE(ha))
..	..	@@ -4592,14 +4790,14 @@
4592	4790	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4593	4791	"Entered %s.\n", __func__);
4594	4792
4595		- str = (void *)version;
	4793	+ str = (__force __le16 *)version;
4596	4794	len = strlen(version);
4597	4795
4598	4796	mcp->mb[0] = MBC_SET_RNID_PARAMS;
4599	4797	mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4600	4798	mcp->out_mb = MBX_1\|MBX_0;
4601	4799	for (i = 4; i < 16 && len; i++, str++, len -= 2) {
4602		- mcp->mb[i] = cpu_to_le16p(str);
	4800	+ mcp->mb[i] = le16_to_cpup(str);
4603	4801	mcp->out_mb \|= 1<<i;
4604	4802	}
4605	4803	for (; i < 16; i++) {
..	..	@@ -4717,8 +4915,73 @@
4717	4915	"Done %s.\n", __func__);
4718	4916	bp = (uint32_t *) buf;
4719	4917	for (i = 0; i < (bufsiz-4)/4; i++, bp++)
4720		- bp = le32_to_cpu(bp);
	4918	+ bp = le32_to_cpu((__force __le32)bp);
4721	4919	}
	4920	+
	4921	+ return rval;
	4922	+}
	4923	+
	4924	+#define PUREX_CMD_COUNT 2
	4925	+int
	4926	+qla25xx_set_els_cmds_supported(scsi_qla_host_t *vha)
	4927	+{
	4928	+ int rval;
	4929	+ mbx_cmd_t mc;
	4930	+ mbx_cmd_t *mcp = &mc;
	4931	+ uint8_t *els_cmd_map;
	4932	+ dma_addr_t els_cmd_map_dma;
	4933	+ uint8_t cmd_opcode[PUREX_CMD_COUNT];
	4934	+ uint8_t i, index, purex_bit;
	4935	+ struct qla_hw_data *ha = vha->hw;
	4936	+
	4937	+ if (!IS_QLA25XX(ha) && !IS_QLA2031(ha) &&
	4938	+ !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
	4939	+ return QLA_SUCCESS;
	4940	+
	4941	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1197,
	4942	+ "Entered %s.\n", __func__);
	4943	+
	4944	+ els_cmd_map = dma_alloc_coherent(&ha->pdev->dev, ELS_CMD_MAP_SIZE,
	4945	+ &els_cmd_map_dma, GFP_KERNEL);
	4946	+ if (!els_cmd_map) {
	4947	+ ql_log(ql_log_warn, vha, 0x7101,
	4948	+ "Failed to allocate RDP els command param.\n");
	4949	+ return QLA_MEMORY_ALLOC_FAILED;
	4950	+ }
	4951	+
	4952	+ /* List of Purex ELS */
	4953	+ cmd_opcode[0] = ELS_FPIN;
	4954	+ cmd_opcode[1] = ELS_RDP;
	4955	+
	4956	+ for (i = 0; i < PUREX_CMD_COUNT; i++) {
	4957	+ index = cmd_opcode[i] / 8;
	4958	+ purex_bit = cmd_opcode[i] % 8;
	4959	+ els_cmd_map[index] \|= 1 << purex_bit;
	4960	+ }
	4961	+
	4962	+ mcp->mb[0] = MBC_SET_RNID_PARAMS;
	4963	+ mcp->mb[1] = RNID_TYPE_ELS_CMD << 8;
	4964	+ mcp->mb[2] = MSW(LSD(els_cmd_map_dma));
	4965	+ mcp->mb[3] = LSW(LSD(els_cmd_map_dma));
	4966	+ mcp->mb[6] = MSW(MSD(els_cmd_map_dma));
	4967	+ mcp->mb[7] = LSW(MSD(els_cmd_map_dma));
	4968	+ mcp->out_mb = MBX_7\|MBX_6\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
	4969	+ mcp->in_mb = MBX_1\|MBX_0;
	4970	+ mcp->tov = MBX_TOV_SECONDS;
	4971	+ mcp->flags = MBX_DMA_OUT;
	4972	+ mcp->buf_size = ELS_CMD_MAP_SIZE;
	4973	+ rval = qla2x00_mailbox_command(vha, mcp);
	4974	+
	4975	+ if (rval != QLA_SUCCESS) {
	4976	+ ql_dbg(ql_dbg_mbx, vha, 0x118d,
	4977	+ "Failed=%x (%x,%x).\n", rval, mcp->mb[0], mcp->mb[1]);
	4978	+ } else {
	4979	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
	4980	+ "Done %s.\n", __func__);
	4981	+ }
	4982	+
	4983	+ dma_free_coherent(&ha->pdev->dev, ELS_CMD_MAP_SIZE,
	4984	+ els_cmd_map, els_cmd_map_dma);
4722	4985
4723	4986	return rval;
4724	4987	}
..	..	@@ -4776,8 +5039,8 @@
4776	5039
4777	5040	mcp->mb[0] = MBC_READ_SFP;
4778	5041	mcp->mb[1] = dev;
4779		- mcp->mb[2] = MSW(sfp_dma);
4780		- mcp->mb[3] = LSW(sfp_dma);
	5042	+ mcp->mb[2] = MSW(LSD(sfp_dma));
	5043	+ mcp->mb[3] = LSW(LSD(sfp_dma));
4781	5044	mcp->mb[6] = MSW(MSD(sfp_dma));
4782	5045	mcp->mb[7] = LSW(MSD(sfp_dma));
4783	5046	mcp->mb[8] = len;
..	..	@@ -4795,10 +5058,10 @@
4795	5058	if (rval != QLA_SUCCESS) {
4796	5059	ql_dbg(ql_dbg_mbx, vha, 0x10e9,
4797	5060	"Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4798		- if (mcp->mb[0] == MBS_COMMAND_ERROR &&
4799		- mcp->mb[1] == 0x22)
	5061	+ if (mcp->mb[0] == MBS_COMMAND_ERROR && mcp->mb[1] == 0x22) {
4800	5062	/* sfp is not there */
4801	5063	rval = QLA_INTERFACE_ERROR;
	5064	+ }
4802	5065	} else {
4803	5066	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
4804	5067	"Done %s.\n", __func__);
..	..	@@ -4830,8 +5093,8 @@
4830	5093
4831	5094	mcp->mb[0] = MBC_WRITE_SFP;
4832	5095	mcp->mb[1] = dev;
4833		- mcp->mb[2] = MSW(sfp_dma);
4834		- mcp->mb[3] = LSW(sfp_dma);
	5096	+ mcp->mb[2] = MSW(LSD(sfp_dma));
	5097	+ mcp->mb[3] = LSW(LSD(sfp_dma));
4835	5098	mcp->mb[6] = MSW(MSD(sfp_dma));
4836	5099	mcp->mb[7] = LSW(MSD(sfp_dma));
4837	5100	mcp->mb[8] = len;
..	..	@@ -4952,7 +5215,7 @@
4952	5215	mcp->mb[8] = MSW(risc_addr);
4953	5216	mcp->out_mb = MBX_8\|MBX_1\|MBX_0;
4954	5217	mcp->in_mb = MBX_3\|MBX_2\|MBX_0;
4955		- mcp->tov = 30;
	5218	+ mcp->tov = MBX_TOV_SECONDS;
4956	5219	mcp->flags = 0;
4957	5220	rval = qla2x00_mailbox_command(vha, mcp);
4958	5221	if (rval != QLA_SUCCESS) {
..	..	@@ -5066,10 +5329,11 @@
5066	5329	mcp->out_mb \|= MBX_2;
5067	5330
5068	5331	mcp->in_mb = MBX_0;
5069		- if (IS_QLA24XX_TYPE(ha) \|\| IS_QLA25XX(ha) \|\|
5070		- IS_CNA_CAPABLE(ha) \|\| IS_QLA2031(ha))
	5332	+ if (IS_CNA_CAPABLE(ha) \|\| IS_QLA24XX_TYPE(ha) \|\| IS_QLA25XX(ha) \|\|
	5333	+ IS_QLA2031(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
5071	5334	mcp->in_mb \|= MBX_1;
5072		- if (IS_CNA_CAPABLE(ha) \|\| IS_QLA2031(ha))
	5335	+ if (IS_CNA_CAPABLE(ha) \|\| IS_QLA2031(ha) \|\| IS_QLA27XX(ha) \|\|
	5336	+ IS_QLA28XX(ha))
5073	5337	mcp->in_mb \|= MBX_3;
5074	5338
5075	5339	mcp->tov = MBX_TOV_SECONDS;
..	..	@@ -5138,13 +5402,14 @@
5138	5402	mcp->mb[3] = MSW(data);
5139	5403	mcp->mb[8] = MSW(risc_addr);
5140	5404	mcp->out_mb = MBX_8\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
5141		- mcp->in_mb = MBX_0;
5142		- mcp->tov = 30;
	5405	+ mcp->in_mb = MBX_1\|MBX_0;
	5406	+ mcp->tov = MBX_TOV_SECONDS;
5143	5407	mcp->flags = 0;
5144	5408	rval = qla2x00_mailbox_command(vha, mcp);
5145	5409	if (rval != QLA_SUCCESS) {
5146	5410	ql_dbg(ql_dbg_mbx, vha, 0x1101,
5147		- "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
	5411	+ "Failed=%x mb[0]=%x mb[1]=%x.\n",
	5412	+ rval, mcp->mb[0], mcp->mb[1]);
5148	5413	} else {
5149	5414	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
5150	5415	"Done %s.\n", __func__);
..	..	@@ -5170,18 +5435,18 @@
5170	5435	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
5171	5436
5172	5437	/* Write the MBC data to the registers */
5173		- WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
5174		- WRT_REG_WORD(&reg->mailbox1, mb[0]);
5175		- WRT_REG_WORD(&reg->mailbox2, mb[1]);
5176		- WRT_REG_WORD(&reg->mailbox3, mb[2]);
5177		- WRT_REG_WORD(&reg->mailbox4, mb[3]);
	5438	+ wrt_reg_word(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
	5439	+ wrt_reg_word(&reg->mailbox1, mb[0]);
	5440	+ wrt_reg_word(&reg->mailbox2, mb[1]);
	5441	+ wrt_reg_word(&reg->mailbox3, mb[2]);
	5442	+ wrt_reg_word(&reg->mailbox4, mb[3]);
5178	5443
5179		- WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
	5444	+ wrt_reg_dword(&reg->hccr, HCCRX_SET_HOST_INT);
5180	5445
5181	5446	/* Poll for MBC interrupt */
5182	5447	for (timer = 6000000; timer; timer--) {
5183	5448	/* Check for pending interrupts. */
5184		- stat = RD_REG_DWORD(&reg->host_status);
	5449	+ stat = rd_reg_dword(&reg->host_status);
5185	5450	if (stat & HSRX_RISC_INT) {
5186	5451	stat &= 0xff;
5187	5452
..	..	@@ -5189,10 +5454,10 @@
5189	5454	stat == 0x10 \|\| stat == 0x11) {
5190	5455	set_bit(MBX_INTERRUPT,
5191	5456	&ha->mbx_cmd_flags);
5192		- mb0 = RD_REG_WORD(&reg->mailbox0);
5193		- WRT_REG_DWORD(&reg->hccr,
	5457	+ mb0 = rd_reg_word(&reg->mailbox0);
	5458	+ wrt_reg_dword(&reg->hccr,
5194	5459	HCCRX_CLR_RISC_INT);
5195		- RD_REG_DWORD(&reg->hccr);
	5460	+ rd_reg_dword(&reg->hccr);
5196	5461	break;
5197	5462	}
5198	5463	}
..	..	@@ -5215,6 +5480,66 @@
5215	5480	return rval;
5216	5481	}
5217	5482
	5483	+/* Set the specified data rate */
	5484	+int
	5485	+qla2x00_set_data_rate(scsi_qla_host_t *vha, uint16_t mode)
	5486	+{
	5487	+ int rval;
	5488	+ mbx_cmd_t mc;
	5489	+ mbx_cmd_t *mcp = &mc;
	5490	+ struct qla_hw_data *ha = vha->hw;
	5491	+ uint16_t val;
	5492	+
	5493	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
	5494	+ "Entered %s speed:0x%x mode:0x%x.\n", __func__, ha->set_data_rate,
	5495	+ mode);
	5496	+
	5497	+ if (!IS_FWI2_CAPABLE(ha))
	5498	+ return QLA_FUNCTION_FAILED;
	5499	+
	5500	+ memset(mcp, 0, sizeof(*mcp));
	5501	+ switch (ha->set_data_rate) {
	5502	+ case PORT_SPEED_AUTO:
	5503	+ case PORT_SPEED_4GB:
	5504	+ case PORT_SPEED_8GB:
	5505	+ case PORT_SPEED_16GB:
	5506	+ case PORT_SPEED_32GB:
	5507	+ val = ha->set_data_rate;
	5508	+ break;
	5509	+ default:
	5510	+ ql_log(ql_log_warn, vha, 0x1199,
	5511	+ "Unrecognized speed setting:%d. Setting Autoneg\n",
	5512	+ ha->set_data_rate);
	5513	+ val = ha->set_data_rate = PORT_SPEED_AUTO;
	5514	+ break;
	5515	+ }
	5516	+
	5517	+ mcp->mb[0] = MBC_DATA_RATE;
	5518	+ mcp->mb[1] = mode;
	5519	+ mcp->mb[2] = val;
	5520	+
	5521	+ mcp->out_mb = MBX_2\|MBX_1\|MBX_0;
	5522	+ mcp->in_mb = MBX_2\|MBX_1\|MBX_0;
	5523	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	5524	+ mcp->in_mb \|= MBX_4\|MBX_3;
	5525	+ mcp->tov = MBX_TOV_SECONDS;
	5526	+ mcp->flags = 0;
	5527	+ rval = qla2x00_mailbox_command(vha, mcp);
	5528	+ if (rval != QLA_SUCCESS) {
	5529	+ ql_dbg(ql_dbg_mbx, vha, 0x1107,
	5530	+ "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
	5531	+ } else {
	5532	+ if (mcp->mb[1] != 0x7)
	5533	+ ql_dbg(ql_dbg_mbx, vha, 0x1179,
	5534	+ "Speed set:0x%x\n", mcp->mb[1]);
	5535	+
	5536	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
	5537	+ "Done %s.\n", __func__);
	5538	+ }
	5539	+
	5540	+ return rval;
	5541	+}
	5542	+
5218	5543	int
5219	5544	qla2x00_get_data_rate(scsi_qla_host_t *vha)
5220	5545	{
..	..	@@ -5230,11 +5555,11 @@
5230	5555	return QLA_FUNCTION_FAILED;
5231	5556
5232	5557	mcp->mb[0] = MBC_DATA_RATE;
5233		- mcp->mb[1] = 0;
	5558	+ mcp->mb[1] = QLA_GET_DATA_RATE;
5234	5559	mcp->out_mb = MBX_1\|MBX_0;
5235	5560	mcp->in_mb = MBX_2\|MBX_1\|MBX_0;
5236		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
5237		- mcp->in_mb \|= MBX_3;
	5561	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	5562	+ mcp->in_mb \|= MBX_4\|MBX_3;
5238	5563	mcp->tov = MBX_TOV_SECONDS;
5239	5564	mcp->flags = 0;
5240	5565	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -5242,6 +5567,15 @@
5242	5567	ql_dbg(ql_dbg_mbx, vha, 0x1107,
5243	5568	"Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5244	5569	} else {
	5570	+ if (mcp->mb[1] != 0x7)
	5571	+ ha->link_data_rate = mcp->mb[1];
	5572	+
	5573	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
	5574	+ if (mcp->mb[4] & BIT_0)
	5575	+ ql_log(ql_log_info, vha, 0x11a2,
	5576	+ "FEC=enabled (data rate).\n");
	5577	+ }
	5578	+
5245	5579	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5246	5580	"Done %s.\n", __func__);
5247	5581	if (mcp->mb[1] != 0x7)
..	..	@@ -5263,7 +5597,7 @@
5263	5597	"Entered %s.\n", __func__);
5264	5598
5265	5599	if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
5266		- !IS_QLA27XX(ha))
	5600	+ !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
5267	5601	return QLA_FUNCTION_FAILED;
5268	5602	mcp->mb[0] = MBC_GET_PORT_CONFIG;
5269	5603	mcp->out_mb = MBX_0;
..	..	@@ -5341,7 +5675,7 @@
5341	5675	mcp->mb[9] = vha->vp_idx;
5342	5676	mcp->out_mb = MBX_9\|MBX_4\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
5343	5677	mcp->in_mb = MBX_4\|MBX_3\|MBX_1\|MBX_0;
5344		- mcp->tov = 30;
	5678	+ mcp->tov = MBX_TOV_SECONDS;
5345	5679	mcp->flags = 0;
5346	5680	rval = qla2x00_mailbox_command(vha, mcp);
5347	5681	if (mb != NULL) {
..	..	@@ -5428,7 +5762,7 @@
5428	5762
5429	5763	mcp->out_mb = MBX_1\|MBX_0;
5430	5764	mcp->in_mb = MBX_0;
5431		- mcp->tov = 30;
	5765	+ mcp->tov = MBX_TOV_SECONDS;
5432	5766	mcp->flags = 0;
5433	5767
5434	5768	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -5463,7 +5797,7 @@
5463	5797
5464	5798	mcp->out_mb = MBX_1\|MBX_0;
5465	5799	mcp->in_mb = MBX_0;
5466		- mcp->tov = 30;
	5800	+ mcp->tov = MBX_TOV_SECONDS;
5467	5801	mcp->flags = 0;
5468	5802
5469	5803	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -5579,6 +5913,7 @@
5579	5913	mbx_cmd_t *mcp = &mc;
5580	5914	int rval = QLA_FUNCTION_FAILED;
5581	5915	int offset = 0, size = MINIDUMP_SIZE_36K;
	5916	+
5582	5917	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
5583	5918	"Entered %s.\n", __func__);
5584	5919
..	..	@@ -5654,7 +5989,7 @@
5654	5989	if (IS_QLA8031(ha))
5655	5990	mcp->out_mb \|= MBX_6\|MBX_5\|MBX_4\|MBX_3;
5656	5991	mcp->in_mb = MBX_0;
5657		- mcp->tov = 30;
	5992	+ mcp->tov = MBX_TOV_SECONDS;
5658	5993	mcp->flags = 0;
5659	5994
5660	5995	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -5690,7 +6025,7 @@
5690	6025	mcp->in_mb = MBX_2\|MBX_1\|MBX_0;
5691	6026	if (IS_QLA8031(ha))
5692	6027	mcp->in_mb \|= MBX_6\|MBX_5\|MBX_4\|MBX_3;
5693		- mcp->tov = 30;
	6028	+ mcp->tov = MBX_TOV_SECONDS;
5694	6029	mcp->flags = 0;
5695	6030
5696	6031	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -5759,7 +6094,7 @@
5759	6094	mbx_cmd_t mc;
5760	6095	mbx_cmd_t *mcp = &mc;
5761	6096
5762		- if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
	6097	+ if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
5763	6098	return QLA_FUNCTION_FAILED;
5764	6099
5765	6100	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
..	..	@@ -5834,7 +6169,7 @@
5834	6169	struct qla_hw_data *ha = vha->hw;
5835	6170	unsigned long retry_max_time = jiffies + (2 * HZ);
5836	6171
5837		- if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
	6172	+ if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
5838	6173	return QLA_FUNCTION_FAILED;
5839	6174
5840	6175	ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
..	..	@@ -5884,7 +6219,7 @@
5884	6219	mbx_cmd_t *mcp = &mc;
5885	6220	struct qla_hw_data *ha = vha->hw;
5886	6221
5887		- if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
	6222	+ if (!IS_QLA83XX(ha))
5888	6223	return QLA_FUNCTION_FAILED;
5889	6224
5890	6225	ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
..	..	@@ -5900,7 +6235,7 @@
5900	6235	ql_dbg(ql_dbg_mbx, vha, 0x1144,
5901	6236	"Failed=%x mb[0]=%x mb[1]=%x.\n",
5902	6237	rval, mcp->mb[0], mcp->mb[1]);
5903		- ha->isp_ops->fw_dump(vha, 0);
	6238	+ qla2xxx_dump_fw(vha);
5904	6239	} else {
5905	6240	ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
5906	6241	}
..	..	@@ -5945,7 +6280,7 @@
5945	6280	"Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
5946	6281	rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
5947	6282	mcp->mb[4]);
5948		- ha->isp_ops->fw_dump(vha, 0);
	6283	+ qla2xxx_dump_fw(vha);
5949	6284	} else {
5950	6285	if (subcode & BIT_5)
5951	6286	*sector_size = mcp->mb[1];
..	..	@@ -6017,7 +6352,8 @@
6017	6352	mbx_cmd_t *mcp = &mc;
6018	6353	dma_addr_t dd_dma;
6019	6354
6020		- if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
	6355	+ if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
	6356	+ !IS_QLA28XX(vha->hw))
6021	6357	return QLA_FUNCTION_FAILED;
6022	6358
6023	6359	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f,
..	..	@@ -6059,10 +6395,8 @@
6059	6395	return rval;
6060	6396	}
6061	6397
6062		-static void qla2x00_async_mb_sp_done(void *s, int res)
	6398	+static void qla2x00_async_mb_sp_done(srb_t *sp, int res)
6063	6399	{
6064		- struct srb *sp = s;
6065		-
6066	6400	sp->u.iocb_cmd.u.mbx.rc = res;
6067	6401
6068	6402	complete(&sp->u.iocb_cmd.u.mbx.comp);
..	..	@@ -6160,13 +6494,13 @@
6160	6494
6161	6495	memset(&mc, 0, sizeof(mc));
6162	6496	mc.mb[0] = MBC_GET_PORT_DATABASE;
6163		- mc.mb[1] = cpu_to_le16(fcport->loop_id);
	6497	+ mc.mb[1] = fcport->loop_id;
6164	6498	mc.mb[2] = MSW(pd_dma);
6165	6499	mc.mb[3] = LSW(pd_dma);
6166	6500	mc.mb[6] = MSW(MSD(pd_dma));
6167	6501	mc.mb[7] = LSW(MSD(pd_dma));
6168		- mc.mb[9] = cpu_to_le16(vha->vp_idx);
6169		- mc.mb[10] = cpu_to_le16((uint16_t)opt);
	6502	+ mc.mb[9] = vha->vp_idx;
	6503	+ mc.mb[10] = opt;
6170	6504
6171	6505	rval = qla24xx_send_mb_cmd(vha, &mc);
6172	6506	if (rval != QLA_SUCCESS) {
..	..	@@ -6194,7 +6528,7 @@
6194	6528	uint64_t zero = 0;
6195	6529	u8 current_login_state, last_login_state;
6196	6530
6197		- if (fcport->fc4f_nvme) {
	6531	+ if (NVME_TARGET(vha->hw, fcport)) {
6198	6532	current_login_state = pd->current_login_state >> 4;
6199	6533	last_login_state = pd->last_login_state >> 4;
6200	6534	} else {
..	..	@@ -6229,10 +6563,14 @@
6229	6563	fcport->d_id.b.al_pa = pd->port_id[2];
6230	6564	fcport->d_id.b.rsvd_1 = 0;
6231	6565
6232		- if (fcport->fc4f_nvme) {
6233		- fcport->nvme_prli_service_param =
6234		- pd->prli_nvme_svc_param_word_3;
	6566	+ if (NVME_TARGET(vha->hw, fcport)) {
6235	6567	fcport->port_type = FCT_NVME;
	6568	+ if ((pd->prli_svc_param_word_3[0] & BIT_5) == 0)
	6569	+ fcport->port_type \|= FCT_NVME_INITIATOR;
	6570	+ if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
	6571	+ fcport->port_type \|= FCT_NVME_TARGET;
	6572	+ if ((pd->prli_svc_param_word_3[0] & BIT_3) == 0)
	6573	+ fcport->port_type \|= FCT_NVME_DISCOVERY;
6236	6574	} else {
6237	6575	/* If not target must be initiator or unknown type. */
6238	6576	if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
..	..	@@ -6273,7 +6611,7 @@
6273	6611	mc.mb[6] = MSW(MSD(id_list_dma));
6274	6612	mc.mb[7] = LSW(MSD(id_list_dma));
6275	6613	mc.mb[8] = 0;
6276		- mc.mb[9] = cpu_to_le16(vha->vp_idx);
	6614	+ mc.mb[9] = vha->vp_idx;
6277	6615
6278	6616	rval = qla24xx_send_mb_cmd(vha, &mc);
6279	6617	if (rval != QLA_SUCCESS) {
..	..	@@ -6299,8 +6637,8 @@
6299	6637
6300	6638	memset(mcp->mb, 0 , sizeof(mcp->mb));
6301	6639	mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6302		- mcp->mb[1] = cpu_to_le16(1);
6303		- mcp->mb[2] = cpu_to_le16(value);
	6640	+ mcp->mb[1] = 1;
	6641	+ mcp->mb[2] = value;
6304	6642	mcp->out_mb = MBX_2 \| MBX_1 \| MBX_0;
6305	6643	mcp->in_mb = MBX_2 \| MBX_0;
6306	6644	mcp->tov = MBX_TOV_SECONDS;
..	..	@@ -6325,7 +6663,7 @@
6325	6663
6326	6664	memset(mcp->mb, 0, sizeof(mcp->mb));
6327	6665	mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6328		- mcp->mb[1] = cpu_to_le16(0);
	6666	+ mcp->mb[1] = 0;
6329	6667	mcp->out_mb = MBX_1 \| MBX_0;
6330	6668	mcp->in_mb = MBX_2 \| MBX_0;
6331	6669	mcp->tov = MBX_TOV_SECONDS;
..	..	@@ -6421,3 +6759,158 @@
6421	6759	done:
6422	6760	return rval;
6423	6761	}
	6762	+
	6763	+int qla28xx_secure_flash_update(scsi_qla_host_t *vha, uint16_t opts,
	6764	+ uint16_t region, uint32_t len, dma_addr_t sfub_dma_addr,
	6765	+ uint32_t sfub_len)
	6766	+{
	6767	+ int rval;
	6768	+ mbx_cmd_t mc;
	6769	+ mbx_cmd_t *mcp = &mc;
	6770	+
	6771	+ mcp->mb[0] = MBC_SECURE_FLASH_UPDATE;
	6772	+ mcp->mb[1] = opts;
	6773	+ mcp->mb[2] = region;
	6774	+ mcp->mb[3] = MSW(len);
	6775	+ mcp->mb[4] = LSW(len);
	6776	+ mcp->mb[5] = MSW(sfub_dma_addr);
	6777	+ mcp->mb[6] = LSW(sfub_dma_addr);
	6778	+ mcp->mb[7] = MSW(MSD(sfub_dma_addr));
	6779	+ mcp->mb[8] = LSW(MSD(sfub_dma_addr));
	6780	+ mcp->mb[9] = sfub_len;
	6781	+ mcp->out_mb =
	6782	+ MBX_9\|MBX_8\|MBX_7\|MBX_6\|MBX_5\|MBX_4\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
	6783	+ mcp->in_mb = MBX_2\|MBX_1\|MBX_0;
	6784	+ mcp->tov = MBX_TOV_SECONDS;
	6785	+ mcp->flags = 0;
	6786	+ rval = qla2x00_mailbox_command(vha, mcp);
	6787	+
	6788	+ if (rval != QLA_SUCCESS) {
	6789	+ ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s(%ld): failed rval 0x%x, %x %x %x",
	6790	+ __func__, vha->host_no, rval, mcp->mb[0], mcp->mb[1],
	6791	+ mcp->mb[2]);
	6792	+ }
	6793	+
	6794	+ return rval;
	6795	+}
	6796	+
	6797	+int qla2xxx_write_remote_register(scsi_qla_host_t *vha, uint32_t addr,
	6798	+ uint32_t data)
	6799	+{
	6800	+ int rval;
	6801	+ mbx_cmd_t mc;
	6802	+ mbx_cmd_t *mcp = &mc;
	6803	+
	6804	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
	6805	+ "Entered %s.\n", __func__);
	6806	+
	6807	+ mcp->mb[0] = MBC_WRITE_REMOTE_REG;
	6808	+ mcp->mb[1] = LSW(addr);
	6809	+ mcp->mb[2] = MSW(addr);
	6810	+ mcp->mb[3] = LSW(data);
	6811	+ mcp->mb[4] = MSW(data);
	6812	+ mcp->out_mb = MBX_4\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
	6813	+ mcp->in_mb = MBX_1\|MBX_0;
	6814	+ mcp->tov = MBX_TOV_SECONDS;
	6815	+ mcp->flags = 0;
	6816	+ rval = qla2x00_mailbox_command(vha, mcp);
	6817	+
	6818	+ if (rval != QLA_SUCCESS) {
	6819	+ ql_dbg(ql_dbg_mbx, vha, 0x10e9,
	6820	+ "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
	6821	+ } else {
	6822	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
	6823	+ "Done %s.\n", __func__);
	6824	+ }
	6825	+
	6826	+ return rval;
	6827	+}
	6828	+
	6829	+int qla2xxx_read_remote_register(scsi_qla_host_t *vha, uint32_t addr,
	6830	+ uint32_t *data)
	6831	+{
	6832	+ int rval;
	6833	+ mbx_cmd_t mc;
	6834	+ mbx_cmd_t *mcp = &mc;
	6835	+
	6836	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
	6837	+ "Entered %s.\n", __func__);
	6838	+
	6839	+ mcp->mb[0] = MBC_READ_REMOTE_REG;
	6840	+ mcp->mb[1] = LSW(addr);
	6841	+ mcp->mb[2] = MSW(addr);
	6842	+ mcp->out_mb = MBX_2\|MBX_1\|MBX_0;
	6843	+ mcp->in_mb = MBX_4\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
	6844	+ mcp->tov = MBX_TOV_SECONDS;
	6845	+ mcp->flags = 0;
	6846	+ rval = qla2x00_mailbox_command(vha, mcp);
	6847	+
	6848	+ *data = (uint32_t)((((uint32_t)mcp->mb[4]) << 16) \| mcp->mb[3]);
	6849	+
	6850	+ if (rval != QLA_SUCCESS) {
	6851	+ ql_dbg(ql_dbg_mbx, vha, 0x10e9,
	6852	+ "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
	6853	+ } else {
	6854	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
	6855	+ "Done %s.\n", __func__);
	6856	+ }
	6857	+
	6858	+ return rval;
	6859	+}
	6860	+
	6861	+int
	6862	+ql26xx_led_config(scsi_qla_host_t vha, uint16_t options, uint16_t led)
	6863	+{
	6864	+ struct qla_hw_data *ha = vha->hw;
	6865	+ mbx_cmd_t mc;
	6866	+ mbx_cmd_t *mcp = &mc;
	6867	+ int rval;
	6868	+
	6869	+ if (!IS_QLA2031(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
	6870	+ return QLA_FUNCTION_FAILED;
	6871	+
	6872	+ ql_dbg(ql_dbg_mbx, vha, 0x7070, "Entered %s (options=%x).\n",
	6873	+ __func__, options);
	6874	+
	6875	+ mcp->mb[0] = MBC_SET_GET_FC_LED_CONFIG;
	6876	+ mcp->mb[1] = options;
	6877	+ mcp->out_mb = MBX_1\|MBX_0;
	6878	+ mcp->in_mb = MBX_1\|MBX_0;
	6879	+ if (options & BIT_0) {
	6880	+ if (options & BIT_1) {
	6881	+ mcp->mb[2] = led[2];
	6882	+ mcp->out_mb \|= MBX_2;
	6883	+ }
	6884	+ if (options & BIT_2) {
	6885	+ mcp->mb[3] = led[0];
	6886	+ mcp->out_mb \|= MBX_3;
	6887	+ }
	6888	+ if (options & BIT_3) {
	6889	+ mcp->mb[4] = led[1];
	6890	+ mcp->out_mb \|= MBX_4;
	6891	+ }
	6892	+ } else {
	6893	+ mcp->in_mb \|= MBX_4\|MBX_3\|MBX_2;
	6894	+ }
	6895	+ mcp->tov = MBX_TOV_SECONDS;
	6896	+ mcp->flags = 0;
	6897	+ rval = qla2x00_mailbox_command(vha, mcp);
	6898	+ if (rval) {
	6899	+ ql_dbg(ql_dbg_mbx, vha, 0x7071, "Failed %s %x (mb=%x,%x)\n",
	6900	+ __func__, rval, mcp->mb[0], mcp->mb[1]);
	6901	+ return rval;
	6902	+ }
	6903	+
	6904	+ if (options & BIT_0) {
	6905	+ ha->beacon_blink_led = 0;
	6906	+ ql_dbg(ql_dbg_mbx, vha, 0x7072, "Done %s\n", __func__);
	6907	+ } else {
	6908	+ led[2] = mcp->mb[2];
	6909	+ led[0] = mcp->mb[3];
	6910	+ led[1] = mcp->mb[4];
	6911	+ ql_dbg(ql_dbg_mbx, vha, 0x7073, "Done %s (led=%x,%x,%x)\n",
	6912	+ __func__, led[0], led[1], led[2]);
	6913	+ }
	6914	+
	6915	+ return rval;
	6916	+}