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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/scsi/qla2xxx/qla_dbg.h
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@@ -1,8 +1,7 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * QLogic Fibre Channel HBA Driver
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  * Copyright (c)  2003-2014 QLogic Corporation
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- *
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- * See LICENSE.qla2xxx for copyright and licensing details.
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  */
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6
 
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 #include "qla_def.h"
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@@ -12,205 +11,206 @@
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  */
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12
 
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 struct qla2300_fw_dump {
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-	uint16_t hccr;
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-	uint16_t pbiu_reg[8];
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-	uint16_t risc_host_reg[8];
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-	uint16_t mailbox_reg[32];
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-	uint16_t resp_dma_reg[32];
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-	uint16_t dma_reg[48];
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-	uint16_t risc_hdw_reg[16];
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-	uint16_t risc_gp0_reg[16];
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-	uint16_t risc_gp1_reg[16];
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-	uint16_t risc_gp2_reg[16];
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-	uint16_t risc_gp3_reg[16];
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-	uint16_t risc_gp4_reg[16];
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-	uint16_t risc_gp5_reg[16];
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-	uint16_t risc_gp6_reg[16];
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-	uint16_t risc_gp7_reg[16];
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-	uint16_t frame_buf_hdw_reg[64];
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-	uint16_t fpm_b0_reg[64];
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-	uint16_t fpm_b1_reg[64];
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-	uint16_t risc_ram[0xf800];
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-	uint16_t stack_ram[0x1000];
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-	uint16_t data_ram[1];
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+	__be16 hccr;
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+	__be16 pbiu_reg[8];
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+	__be16 risc_host_reg[8];
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+	__be16 mailbox_reg[32];
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+	__be16 resp_dma_reg[32];
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+	__be16 dma_reg[48];
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+	__be16 risc_hdw_reg[16];
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+	__be16 risc_gp0_reg[16];
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+	__be16 risc_gp1_reg[16];
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+	__be16 risc_gp2_reg[16];
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+	__be16 risc_gp3_reg[16];
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+	__be16 risc_gp4_reg[16];
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+	__be16 risc_gp5_reg[16];
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+	__be16 risc_gp6_reg[16];
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+	__be16 risc_gp7_reg[16];
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+	__be16 frame_buf_hdw_reg[64];
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+	__be16 fpm_b0_reg[64];
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+	__be16 fpm_b1_reg[64];
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+	__be16 risc_ram[0xf800];
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+	__be16 stack_ram[0x1000];
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+	__be16 data_ram[1];
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 };
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36
 
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 struct qla2100_fw_dump {
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-	uint16_t hccr;
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-	uint16_t pbiu_reg[8];
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-	uint16_t mailbox_reg[32];
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-	uint16_t dma_reg[48];
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-	uint16_t risc_hdw_reg[16];
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-	uint16_t risc_gp0_reg[16];
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-	uint16_t risc_gp1_reg[16];
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-	uint16_t risc_gp2_reg[16];
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-	uint16_t risc_gp3_reg[16];
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-	uint16_t risc_gp4_reg[16];
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-	uint16_t risc_gp5_reg[16];
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-	uint16_t risc_gp6_reg[16];
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-	uint16_t risc_gp7_reg[16];
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-	uint16_t frame_buf_hdw_reg[16];
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-	uint16_t fpm_b0_reg[64];
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-	uint16_t fpm_b1_reg[64];
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-	uint16_t risc_ram[0xf000];
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+	__be16 hccr;
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+	__be16 pbiu_reg[8];
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+	__be16 mailbox_reg[32];
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+	__be16 dma_reg[48];
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+	__be16 risc_hdw_reg[16];
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+	__be16 risc_gp0_reg[16];
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+	__be16 risc_gp1_reg[16];
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+	__be16 risc_gp2_reg[16];
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+	__be16 risc_gp3_reg[16];
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+	__be16 risc_gp4_reg[16];
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+	__be16 risc_gp5_reg[16];
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+	__be16 risc_gp6_reg[16];
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+	__be16 risc_gp7_reg[16];
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+	__be16 frame_buf_hdw_reg[16];
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+	__be16 fpm_b0_reg[64];
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+	__be16 fpm_b1_reg[64];
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+	__be16 risc_ram[0xf000];
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+	u8	queue_dump[];
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 };
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 struct qla24xx_fw_dump {
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-	uint32_t host_status;
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-	uint32_t host_reg[32];
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-	uint32_t shadow_reg[7];
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-	uint16_t mailbox_reg[32];
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-	uint32_t xseq_gp_reg[128];
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-	uint32_t xseq_0_reg[16];
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-	uint32_t xseq_1_reg[16];
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-	uint32_t rseq_gp_reg[128];
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-	uint32_t rseq_0_reg[16];
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-	uint32_t rseq_1_reg[16];
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-	uint32_t rseq_2_reg[16];
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-	uint32_t cmd_dma_reg[16];
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-	uint32_t req0_dma_reg[15];
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-	uint32_t resp0_dma_reg[15];
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-	uint32_t req1_dma_reg[15];
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-	uint32_t xmt0_dma_reg[32];
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-	uint32_t xmt1_dma_reg[32];
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-	uint32_t xmt2_dma_reg[32];
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-	uint32_t xmt3_dma_reg[32];
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-	uint32_t xmt4_dma_reg[32];
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-	uint32_t xmt_data_dma_reg[16];
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-	uint32_t rcvt0_data_dma_reg[32];
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-	uint32_t rcvt1_data_dma_reg[32];
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-	uint32_t risc_gp_reg[128];
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-	uint32_t lmc_reg[112];
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-	uint32_t fpm_hdw_reg[192];
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-	uint32_t fb_hdw_reg[176];
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-	uint32_t code_ram[0x2000];
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-	uint32_t ext_mem[1];
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+	__be32	host_status;
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+	__be32	host_reg[32];
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+	__be32	shadow_reg[7];
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+	__be16	mailbox_reg[32];
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+	__be32	xseq_gp_reg[128];
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+	__be32	xseq_0_reg[16];
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+	__be32	xseq_1_reg[16];
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+	__be32	rseq_gp_reg[128];
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+	__be32	rseq_0_reg[16];
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+	__be32	rseq_1_reg[16];
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+	__be32	rseq_2_reg[16];
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+	__be32	cmd_dma_reg[16];
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+	__be32	req0_dma_reg[15];
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+	__be32	resp0_dma_reg[15];
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+	__be32	req1_dma_reg[15];
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+	__be32	xmt0_dma_reg[32];
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+	__be32	xmt1_dma_reg[32];
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+	__be32	xmt2_dma_reg[32];
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+	__be32	xmt3_dma_reg[32];
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+	__be32	xmt4_dma_reg[32];
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+	__be32	xmt_data_dma_reg[16];
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+	__be32	rcvt0_data_dma_reg[32];
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+	__be32	rcvt1_data_dma_reg[32];
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+	__be32	risc_gp_reg[128];
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+	__be32	lmc_reg[112];
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+	__be32	fpm_hdw_reg[192];
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+	__be32	fb_hdw_reg[176];
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+	__be32	code_ram[0x2000];
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+	__be32	ext_mem[1];
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 };
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 struct qla25xx_fw_dump {
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-	uint32_t host_status;
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-	uint32_t host_risc_reg[32];
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-	uint32_t pcie_regs[4];
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-	uint32_t host_reg[32];
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-	uint32_t shadow_reg[11];
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-	uint32_t risc_io_reg;
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-	uint16_t mailbox_reg[32];
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-	uint32_t xseq_gp_reg[128];
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-	uint32_t xseq_0_reg[48];
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-	uint32_t xseq_1_reg[16];
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-	uint32_t rseq_gp_reg[128];
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-	uint32_t rseq_0_reg[32];
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-	uint32_t rseq_1_reg[16];
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-	uint32_t rseq_2_reg[16];
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-	uint32_t aseq_gp_reg[128];
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-	uint32_t aseq_0_reg[32];
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-	uint32_t aseq_1_reg[16];
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-	uint32_t aseq_2_reg[16];
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-	uint32_t cmd_dma_reg[16];
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-	uint32_t req0_dma_reg[15];
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-	uint32_t resp0_dma_reg[15];
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-	uint32_t req1_dma_reg[15];
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-	uint32_t xmt0_dma_reg[32];
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-	uint32_t xmt1_dma_reg[32];
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-	uint32_t xmt2_dma_reg[32];
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-	uint32_t xmt3_dma_reg[32];
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-	uint32_t xmt4_dma_reg[32];
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-	uint32_t xmt_data_dma_reg[16];
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-	uint32_t rcvt0_data_dma_reg[32];
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-	uint32_t rcvt1_data_dma_reg[32];
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-	uint32_t risc_gp_reg[128];
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-	uint32_t lmc_reg[128];
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-	uint32_t fpm_hdw_reg[192];
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-	uint32_t fb_hdw_reg[192];
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-	uint32_t code_ram[0x2000];
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-	uint32_t ext_mem[1];
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+	__be32	host_status;
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+	__be32	host_risc_reg[32];
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+	__be32	pcie_regs[4];
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+	__be32	host_reg[32];
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+	__be32	shadow_reg[11];
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+	__be32	risc_io_reg;
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+	__be16	mailbox_reg[32];
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+	__be32	xseq_gp_reg[128];
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+	__be32	xseq_0_reg[48];
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+	__be32	xseq_1_reg[16];
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+	__be32	rseq_gp_reg[128];
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+	__be32	rseq_0_reg[32];
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+	__be32	rseq_1_reg[16];
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+	__be32	rseq_2_reg[16];
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+	__be32	aseq_gp_reg[128];
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+	__be32	aseq_0_reg[32];
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+	__be32	aseq_1_reg[16];
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+	__be32	aseq_2_reg[16];
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+	__be32	cmd_dma_reg[16];
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+	__be32	req0_dma_reg[15];
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+	__be32	resp0_dma_reg[15];
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+	__be32	req1_dma_reg[15];
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+	__be32	xmt0_dma_reg[32];
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+	__be32	xmt1_dma_reg[32];
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+	__be32	xmt2_dma_reg[32];
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+	__be32	xmt3_dma_reg[32];
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+	__be32	xmt4_dma_reg[32];
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+	__be32	xmt_data_dma_reg[16];
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+	__be32	rcvt0_data_dma_reg[32];
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+	__be32	rcvt1_data_dma_reg[32];
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+	__be32	risc_gp_reg[128];
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+	__be32	lmc_reg[128];
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+	__be32	fpm_hdw_reg[192];
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+	__be32	fb_hdw_reg[192];
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+	__be32	code_ram[0x2000];
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+	__be32	ext_mem[1];
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 };
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128
 
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 struct qla81xx_fw_dump {
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-	uint32_t host_status;
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-	uint32_t host_risc_reg[32];
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-	uint32_t pcie_regs[4];
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-	uint32_t host_reg[32];
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-	uint32_t shadow_reg[11];
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-	uint32_t risc_io_reg;
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-	uint16_t mailbox_reg[32];
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-	uint32_t xseq_gp_reg[128];
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-	uint32_t xseq_0_reg[48];
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-	uint32_t xseq_1_reg[16];
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-	uint32_t rseq_gp_reg[128];
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-	uint32_t rseq_0_reg[32];
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-	uint32_t rseq_1_reg[16];
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-	uint32_t rseq_2_reg[16];
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-	uint32_t aseq_gp_reg[128];
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-	uint32_t aseq_0_reg[32];
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-	uint32_t aseq_1_reg[16];
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-	uint32_t aseq_2_reg[16];
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-	uint32_t cmd_dma_reg[16];
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-	uint32_t req0_dma_reg[15];
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-	uint32_t resp0_dma_reg[15];
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-	uint32_t req1_dma_reg[15];
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-	uint32_t xmt0_dma_reg[32];
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-	uint32_t xmt1_dma_reg[32];
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-	uint32_t xmt2_dma_reg[32];
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-	uint32_t xmt3_dma_reg[32];
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-	uint32_t xmt4_dma_reg[32];
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-	uint32_t xmt_data_dma_reg[16];
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-	uint32_t rcvt0_data_dma_reg[32];
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-	uint32_t rcvt1_data_dma_reg[32];
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-	uint32_t risc_gp_reg[128];
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-	uint32_t lmc_reg[128];
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-	uint32_t fpm_hdw_reg[224];
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-	uint32_t fb_hdw_reg[208];
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-	uint32_t code_ram[0x2000];
165
-	uint32_t ext_mem[1];
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+	__be32	host_status;
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+	__be32	host_risc_reg[32];
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+	__be32	pcie_regs[4];
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+	__be32	host_reg[32];
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+	__be32	shadow_reg[11];
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+	__be32	risc_io_reg;
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+	__be16	mailbox_reg[32];
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+	__be32	xseq_gp_reg[128];
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+	__be32	xseq_0_reg[48];
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+	__be32	xseq_1_reg[16];
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+	__be32	rseq_gp_reg[128];
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+	__be32	rseq_0_reg[32];
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+	__be32	rseq_1_reg[16];
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+	__be32	rseq_2_reg[16];
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+	__be32	aseq_gp_reg[128];
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+	__be32	aseq_0_reg[32];
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+	__be32	aseq_1_reg[16];
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+	__be32	aseq_2_reg[16];
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+	__be32	cmd_dma_reg[16];
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+	__be32	req0_dma_reg[15];
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+	__be32	resp0_dma_reg[15];
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+	__be32	req1_dma_reg[15];
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+	__be32	xmt0_dma_reg[32];
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+	__be32	xmt1_dma_reg[32];
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+	__be32	xmt2_dma_reg[32];
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+	__be32	xmt3_dma_reg[32];
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+	__be32	xmt4_dma_reg[32];
157
+	__be32	xmt_data_dma_reg[16];
158
+	__be32	rcvt0_data_dma_reg[32];
159
+	__be32	rcvt1_data_dma_reg[32];
160
+	__be32	risc_gp_reg[128];
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+	__be32	lmc_reg[128];
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+	__be32	fpm_hdw_reg[224];
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+	__be32	fb_hdw_reg[208];
164
+	__be32	code_ram[0x2000];
165
+	__be32	ext_mem[1];
166
166
 };
167
167
 
168
168
 struct qla83xx_fw_dump {
169
-	uint32_t host_status;
170
-	uint32_t host_risc_reg[48];
171
-	uint32_t pcie_regs[4];
172
-	uint32_t host_reg[32];
173
-	uint32_t shadow_reg[11];
174
-	uint32_t risc_io_reg;
175
-	uint16_t mailbox_reg[32];
176
-	uint32_t xseq_gp_reg[256];
177
-	uint32_t xseq_0_reg[48];
178
-	uint32_t xseq_1_reg[16];
179
-	uint32_t xseq_2_reg[16];
180
-	uint32_t rseq_gp_reg[256];
181
-	uint32_t rseq_0_reg[32];
182
-	uint32_t rseq_1_reg[16];
183
-	uint32_t rseq_2_reg[16];
184
-	uint32_t rseq_3_reg[16];
185
-	uint32_t aseq_gp_reg[256];
186
-	uint32_t aseq_0_reg[32];
187
-	uint32_t aseq_1_reg[16];
188
-	uint32_t aseq_2_reg[16];
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-	uint32_t aseq_3_reg[16];
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-	uint32_t cmd_dma_reg[64];
191
-	uint32_t req0_dma_reg[15];
192
-	uint32_t resp0_dma_reg[15];
193
-	uint32_t req1_dma_reg[15];
194
-	uint32_t xmt0_dma_reg[32];
195
-	uint32_t xmt1_dma_reg[32];
196
-	uint32_t xmt2_dma_reg[32];
197
-	uint32_t xmt3_dma_reg[32];
198
-	uint32_t xmt4_dma_reg[32];
199
-	uint32_t xmt_data_dma_reg[16];
200
-	uint32_t rcvt0_data_dma_reg[32];
201
-	uint32_t rcvt1_data_dma_reg[32];
202
-	uint32_t risc_gp_reg[128];
203
-	uint32_t lmc_reg[128];
204
-	uint32_t fpm_hdw_reg[256];
205
-	uint32_t rq0_array_reg[256];
206
-	uint32_t rq1_array_reg[256];
207
-	uint32_t rp0_array_reg[256];
208
-	uint32_t rp1_array_reg[256];
209
-	uint32_t queue_control_reg[16];
210
-	uint32_t fb_hdw_reg[432];
211
-	uint32_t at0_array_reg[128];
212
-	uint32_t code_ram[0x2400];
213
-	uint32_t ext_mem[1];
169
+	__be32	host_status;
170
+	__be32	host_risc_reg[48];
171
+	__be32	pcie_regs[4];
172
+	__be32	host_reg[32];
173
+	__be32	shadow_reg[11];
174
+	__be32	risc_io_reg;
175
+	__be16	mailbox_reg[32];
176
+	__be32	xseq_gp_reg[256];
177
+	__be32	xseq_0_reg[48];
178
+	__be32	xseq_1_reg[16];
179
+	__be32	xseq_2_reg[16];
180
+	__be32	rseq_gp_reg[256];
181
+	__be32	rseq_0_reg[32];
182
+	__be32	rseq_1_reg[16];
183
+	__be32	rseq_2_reg[16];
184
+	__be32	rseq_3_reg[16];
185
+	__be32	aseq_gp_reg[256];
186
+	__be32	aseq_0_reg[32];
187
+	__be32	aseq_1_reg[16];
188
+	__be32	aseq_2_reg[16];
189
+	__be32	aseq_3_reg[16];
190
+	__be32	cmd_dma_reg[64];
191
+	__be32	req0_dma_reg[15];
192
+	__be32	resp0_dma_reg[15];
193
+	__be32	req1_dma_reg[15];
194
+	__be32	xmt0_dma_reg[32];
195
+	__be32	xmt1_dma_reg[32];
196
+	__be32	xmt2_dma_reg[32];
197
+	__be32	xmt3_dma_reg[32];
198
+	__be32	xmt4_dma_reg[32];
199
+	__be32	xmt_data_dma_reg[16];
200
+	__be32	rcvt0_data_dma_reg[32];
201
+	__be32	rcvt1_data_dma_reg[32];
202
+	__be32	risc_gp_reg[128];
203
+	__be32	lmc_reg[128];
204
+	__be32	fpm_hdw_reg[256];
205
+	__be32	rq0_array_reg[256];
206
+	__be32	rq1_array_reg[256];
207
+	__be32	rp0_array_reg[256];
208
+	__be32	rp1_array_reg[256];
209
+	__be32	queue_control_reg[16];
210
+	__be32	fb_hdw_reg[432];
211
+	__be32	at0_array_reg[128];
212
+	__be32	code_ram[0x2400];
213
+	__be32	ext_mem[1];
214
214
 };
215
215
 
216
216
 #define EFT_NUM_BUFFERS		4
..
..
@@ -223,44 +223,45 @@
223
223
 #define fce_calc_size(b)	((FCE_BYTES_PER_BUFFER) * (b))
224
224
 
225
225
 struct qla2xxx_fce_chain {
226
-	uint32_t type;
227
-	uint32_t chain_size;
226
+	__be32	type;
227
+	__be32	chain_size;
228
228
 
229
-	uint32_t size;
230
-	uint32_t addr_l;
231
-	uint32_t addr_h;
232
-	uint32_t eregs[8];
229
+	__be32	size;
230
+	__be32	addr_l;
231
+	__be32	addr_h;
232
+	__be32	eregs[8];
233
233
 };
234
234
 
235
235
 /* used by exchange off load and extended login offload */
236
236
 struct qla2xxx_offld_chain {
237
-	uint32_t type;
238
-	uint32_t chain_size;
237
+	__be32	type;
238
+	__be32	chain_size;
239
239
 
240
-	uint32_t size;
241
-	u64	 addr;
240
+	__be32	size;
241
+	__be32	reserved;
242
+	__be64	addr;
242
243
 };
243
244
 
244
245
 struct qla2xxx_mq_chain {
245
-	uint32_t type;
246
-	uint32_t chain_size;
246
+	__be32	type;
247
+	__be32	chain_size;
247
248
 
248
-	uint32_t count;
249
-	uint32_t qregs[4 * QLA_MQ_SIZE];
249
+	__be32	count;
250
+	__be32	qregs[4 * QLA_MQ_SIZE];
250
251
 };
251
252
 
252
253
 struct qla2xxx_mqueue_header {
253
-	uint32_t queue;
254
+	__be32	queue;
254
255
 #define TYPE_REQUEST_QUEUE	0x1
255
256
 #define TYPE_RESPONSE_QUEUE	0x2
256
257
 #define TYPE_ATIO_QUEUE		0x3
257
-	uint32_t number;
258
-	uint32_t size;
258
+	__be32	number;
259
+	__be32	size;
259
260
 };
260
261
 
261
262
 struct qla2xxx_mqueue_chain {
262
-	uint32_t type;
263
-	uint32_t chain_size;
263
+	__be32	type;
264
+	__be32	chain_size;
264
265
 };
265
266
 
266
267
 #define DUMP_CHAIN_VARIANT	0x80000000
..
..
@@ -273,28 +274,28 @@
273
274
 
274
275
 struct qla2xxx_fw_dump {
275
276
 	uint8_t signature[4];
276
-	uint32_t version;
277
+	__be32	version;
277
278
 
278
-	uint32_t fw_major_version;
279
-	uint32_t fw_minor_version;
280
-	uint32_t fw_subminor_version;
281
-	uint32_t fw_attributes;
279
+	__be32 fw_major_version;
280
+	__be32 fw_minor_version;
281
+	__be32 fw_subminor_version;
282
+	__be32 fw_attributes;
282
283
 
283
-	uint32_t vendor;
284
-	uint32_t device;
285
-	uint32_t subsystem_vendor;
286
-	uint32_t subsystem_device;
284
+	__be32 vendor;
285
+	__be32 device;
286
+	__be32 subsystem_vendor;
287
+	__be32 subsystem_device;
287
288
 
288
-	uint32_t fixed_size;
289
-	uint32_t mem_size;
290
-	uint32_t req_q_size;
291
-	uint32_t rsp_q_size;
289
+	__be32	fixed_size;
290
+	__be32	mem_size;
291
+	__be32	req_q_size;
292
+	__be32	rsp_q_size;
292
293
 
293
-	uint32_t eft_size;
294
-	uint32_t eft_addr_l;
295
-	uint32_t eft_addr_h;
294
+	__be32	eft_size;
295
+	__be32	eft_addr_l;
296
+	__be32	eft_addr_h;
296
297
 
297
-	uint32_t header_size;
298
+	__be32	header_size;
298
299
 
299
300
 	union {
300
301
 		struct qla2100_fw_dump isp21;
..
..
@@ -318,20 +319,20 @@
318
319
 				   * as compared to other log levels.
319
320
 				   */
320
321
 
321
-extern int ql_errlev;
322
+extern uint ql_errlev;
322
323
 
323
324
 void __attribute__((format (printf, 4, 5)))
324
-ql_dbg(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
325
+ql_dbg(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
325
326
 void __attribute__((format (printf, 4, 5)))
326
-ql_dbg_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
327
+ql_dbg_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
327
328
 void __attribute__((format (printf, 4, 5)))
328
329
 ql_dbg_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
329
330
 
330
331
 
331
332
 void __attribute__((format (printf, 4, 5)))
332
-ql_log(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
333
+ql_log(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
333
334
 void __attribute__((format (printf, 4, 5)))
334
-ql_log_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
335
+ql_log_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
335
336
 
336
337
 void __attribute__((format (printf, 4, 5)))
337
338
 ql_log_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
..
..
@@ -369,7 +370,7 @@
369
370
 
370
371
 extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *,
371
372
 	uint32_t, void **);
372
-extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, uint32_t *,
373
+extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, __be32 *,
373
374
 	uint32_t, void **);
374
375
 extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *,
375
376
 	struct qla_hw_data *);
..
..
@@ -378,5 +379,8 @@
378
379
 static inline int
379
380
 ql_mask_match(uint level)
380
381
 {
382
+	if (ql2xextended_error_logging == 1)
383
+		ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
384
+
381
385
 	return (level & ql2xextended_error_logging) == level;
382
386
 }