~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,8 +1,7 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* QLogic Fibre Channel HBA Driver
3	4	* Copyright (c) 2003-2014 QLogic Corporation
4		- *
5		- * See LICENSE.qla2xxx for copyright and licensing details.
6	5	*/
7	6
8	7	/*
..	..	@@ -11,14 +10,11 @@
11	10	* ----------------------------------------------------------------------
12	11	* \| Level \| Last Value Used \| Holes \|
13	12	* ----------------------------------------------------------------------
14		- * \| Module Init and Probe \| 0x0193 \| 0x0146 \|
15		- * \| \| \| 0x015b-0x0160 \|
16		- * \| \| \| 0x016e \|
17		- * \| Mailbox commands \| 0x1206 \| 0x11a2-0x11ff \|
18		- * \| Device Discovery \| 0x2134 \| 0x210e-0x2116 \|
19		- * \| \| \| 0x211a \|
	13	+ * \| Module Init and Probe \| 0x0199 \| \|
	14	+ * \| Mailbox commands \| 0x1206 \| 0x11a5-0x11ff \|
	15	+ * \| Device Discovery \| 0x2134 \| 0x210e-0x2115 \|
20	16	* \| \| \| 0x211c-0x2128 \|
21		- * \| \| \| 0x212a-0x2130 \|
	17	+ * \| \| \| 0x212c-0x2134 \|
22	18	* \| Queue Command and IO tracing \| 0x3074 \| 0x300b \|
23	19	* \| \| \| 0x3027-0x3028 \|
24	20	* \| \| \| 0x303d-0x3041 \|
..	..	@@ -26,11 +22,7 @@
26	22	* \| \| \| 0x3036,0x3038 \|
27	23	* \| \| \| 0x303a \|
28	24	* \| DPC Thread \| 0x4023 \| 0x4002,0x4013 \|
29		- * \| Async Events \| 0x5090 \| 0x502b-0x502f \|
30		- * \| \| \| 0x5047 \|
31		- * \| \| \| 0x5084,0x5075 \|
32		- * \| \| \| 0x503d,0x5044 \|
33		- * \| \| \| 0x505f \|
	25	+ * \| Async Events \| 0x509c \| \|
34	26	* \| Timer Routines \| 0x6012 \| \|
35	27	* \| User Space Interactions \| 0x70e3 \| 0x7018,0x702e \|
36	28	* \| \| \| 0x7020,0x7024 \|
..	..	@@ -73,6 +65,8 @@
73	65	#include "qla_def.h"
74	66
75	67	#include <linux/delay.h>
	68	+#define CREATE_TRACE_POINTS
	69	+#include <trace/events/qla.h>
76	70
77	71	static uint32_t ql_dbg_offset = 0x800;
78	72
..	..	@@ -111,162 +105,161 @@
111	105	qla27xx_dump_mpi_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
112	106	uint32_t ram_dwords, void **nxt)
113	107	{
114		- int rval;
115		- uint32_t cnt, stat, timer, dwords, idx;
116		- uint16_t mb0;
117	108	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
118	109	dma_addr_t dump_dma = ha->gid_list_dma;
119		- uint32_t dump = (uint32_t )ha->gid_list;
	110	+ uint32_t chunk = (uint32_t )ha->gid_list;
	111	+ uint32_t dwords = qla2x00_gid_list_size(ha) / 4;
	112	+ uint32_t stat;
	113	+ ulong i, j, timer = 6000000;
	114	+ int rval = QLA_FUNCTION_FAILED;
120	115
121		- rval = QLA_SUCCESS;
122		- mb0 = 0;
123		-
124		- WRT_REG_WORD(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
125	116	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
	117	+ for (i = 0; i < ram_dwords; i += dwords, addr += dwords) {
	118	+ if (i + dwords > ram_dwords)
	119	+ dwords = ram_dwords - i;
126	120
127		- dwords = qla2x00_gid_list_size(ha) / 4;
128		- for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
129		- cnt += dwords, addr += dwords) {
130		- if (cnt + dwords > ram_dwords)
131		- dwords = ram_dwords - cnt;
	121	+ wrt_reg_word(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
	122	+ wrt_reg_word(&reg->mailbox1, LSW(addr));
	123	+ wrt_reg_word(&reg->mailbox8, MSW(addr));
132	124
133		- WRT_REG_WORD(&reg->mailbox1, LSW(addr));
134		- WRT_REG_WORD(&reg->mailbox8, MSW(addr));
	125	+ wrt_reg_word(&reg->mailbox2, MSW(LSD(dump_dma)));
	126	+ wrt_reg_word(&reg->mailbox3, LSW(LSD(dump_dma)));
	127	+ wrt_reg_word(&reg->mailbox6, MSW(MSD(dump_dma)));
	128	+ wrt_reg_word(&reg->mailbox7, LSW(MSD(dump_dma)));
135	129
136		- WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
137		- WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
138		- WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
139		- WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
	130	+ wrt_reg_word(&reg->mailbox4, MSW(dwords));
	131	+ wrt_reg_word(&reg->mailbox5, LSW(dwords));
140	132
141		- WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
142		- WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
143		-
144		- WRT_REG_WORD(&reg->mailbox9, 0);
145		- WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
	133	+ wrt_reg_word(&reg->mailbox9, 0);
	134	+ wrt_reg_dword(&reg->hccr, HCCRX_SET_HOST_INT);
146	135
147	136	ha->flags.mbox_int = 0;
148		- for (timer = 6000000; timer; timer--) {
	137	+ while (timer--) {
	138	+ udelay(5);
	139	+
	140	+ stat = rd_reg_dword(&reg->host_status);
149	141	/* Check for pending interrupts. */
150		- stat = RD_REG_DWORD(&reg->host_status);
151		- if (stat & HSRX_RISC_INT) {
152		- stat &= 0xff;
	142	+ if (!(stat & HSRX_RISC_INT))
	143	+ continue;
153	144
154		- if (stat == 0x1 \|\| stat == 0x2 \|\|
155		- stat == 0x10 \|\| stat == 0x11) {
156		- set_bit(MBX_INTERRUPT,
157		- &ha->mbx_cmd_flags);
158		-
159		- mb0 = RD_REG_WORD(&reg->mailbox0);
160		- RD_REG_WORD(&reg->mailbox1);
161		-
162		- WRT_REG_DWORD(&reg->hccr,
163		- HCCRX_CLR_RISC_INT);
164		- RD_REG_DWORD(&reg->hccr);
165		- break;
166		- }
	145	+ stat &= 0xff;
	146	+ if (stat != 0x1 && stat != 0x2 &&
	147	+ stat != 0x10 && stat != 0x11) {
167	148
168	149	/* Clear this intr; it wasn't a mailbox intr */
169		- WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
170		- RD_REG_DWORD(&reg->hccr);
	150	+ wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT);
	151	+ rd_reg_dword(&reg->hccr);
	152	+ continue;
171	153	}
172		- udelay(5);
	154	+
	155	+ set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
	156	+ rval = rd_reg_word(&reg->mailbox0) & MBS_MASK;
	157	+ wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT);
	158	+ rd_reg_dword(&reg->hccr);
	159	+ break;
173	160	}
174	161	ha->flags.mbox_int = 1;
	162	+ *nxt = ram + i;
175	163
176		- if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
177		- rval = mb0 & MBS_MASK;
178		- for (idx = 0; idx < dwords; idx++)
179		- ram[cnt + idx] = IS_QLA27XX(ha) ?
180		- le32_to_cpu(dump[idx]) : swab32(dump[idx]);
181		- } else {
182		- rval = QLA_FUNCTION_FAILED;
	164	+ if (!test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
	165	+ /* no interrupt, timed out*/
	166	+ return rval;
	167	+ }
	168	+ if (rval) {
	169	+ /* error completion status */
	170	+ return rval;
	171	+ }
	172	+ for (j = 0; j < dwords; j++) {
	173	+ ram[i + j] =
	174	+ (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) ?
	175	+ chunk[j] : swab32(chunk[j]);
183	176	}
184	177	}
185	178
186		- *nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL;
187		- return rval;
	179	+ *nxt = ram + i;
	180	+ return QLA_SUCCESS;
188	181	}
189	182
190	183	int
191		-qla24xx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
192		- uint32_t ram_dwords, void **nxt)
	184	+qla24xx_dump_ram(struct qla_hw_data ha, uint32_t addr, __be32 ram,
	185	+ uint32_t ram_dwords, void **nxt)
193	186	{
194		- int rval;
195		- uint32_t cnt, stat, timer, dwords, idx;
196		- uint16_t mb0;
	187	+ int rval = QLA_FUNCTION_FAILED;
197	188	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
198	189	dma_addr_t dump_dma = ha->gid_list_dma;
199		- uint32_t dump = (uint32_t )ha->gid_list;
	190	+ uint32_t chunk = (uint32_t )ha->gid_list;
	191	+ uint32_t dwords = qla2x00_gid_list_size(ha) / 4;
	192	+ uint32_t stat;
	193	+ ulong i, j, timer = 6000000;
200	194
201		- rval = QLA_SUCCESS;
202		- mb0 = 0;
203		-
204		- WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
205	195	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
206	196
207		- dwords = qla2x00_gid_list_size(ha) / 4;
208		- for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
209		- cnt += dwords, addr += dwords) {
210		- if (cnt + dwords > ram_dwords)
211		- dwords = ram_dwords - cnt;
	197	+ for (i = 0; i < ram_dwords; i += dwords, addr += dwords) {
	198	+ if (i + dwords > ram_dwords)
	199	+ dwords = ram_dwords - i;
212	200
213		- WRT_REG_WORD(&reg->mailbox1, LSW(addr));
214		- WRT_REG_WORD(&reg->mailbox8, MSW(addr));
	201	+ wrt_reg_word(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
	202	+ wrt_reg_word(&reg->mailbox1, LSW(addr));
	203	+ wrt_reg_word(&reg->mailbox8, MSW(addr));
	204	+ wrt_reg_word(&reg->mailbox10, 0);
215	205
216		- WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
217		- WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
218		- WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
219		- WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
	206	+ wrt_reg_word(&reg->mailbox2, MSW(LSD(dump_dma)));
	207	+ wrt_reg_word(&reg->mailbox3, LSW(LSD(dump_dma)));
	208	+ wrt_reg_word(&reg->mailbox6, MSW(MSD(dump_dma)));
	209	+ wrt_reg_word(&reg->mailbox7, LSW(MSD(dump_dma)));
220	210
221		- WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
222		- WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
223		- WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
	211	+ wrt_reg_word(&reg->mailbox4, MSW(dwords));
	212	+ wrt_reg_word(&reg->mailbox5, LSW(dwords));
	213	+ wrt_reg_dword(&reg->hccr, HCCRX_SET_HOST_INT);
224	214
225	215	ha->flags.mbox_int = 0;
226		- for (timer = 6000000; timer; timer--) {
227		- /* Check for pending interrupts. */
228		- stat = RD_REG_DWORD(&reg->host_status);
229		- if (stat & HSRX_RISC_INT) {
230		- stat &= 0xff;
231		-
232		- if (stat == 0x1 \|\| stat == 0x2 \|\|
233		- stat == 0x10 \|\| stat == 0x11) {
234		- set_bit(MBX_INTERRUPT,
235		- &ha->mbx_cmd_flags);
236		-
237		- mb0 = RD_REG_WORD(&reg->mailbox0);
238		-
239		- WRT_REG_DWORD(&reg->hccr,
240		- HCCRX_CLR_RISC_INT);
241		- RD_REG_DWORD(&reg->hccr);
242		- break;
243		- }
244		-
245		- /* Clear this intr; it wasn't a mailbox intr */
246		- WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
247		- RD_REG_DWORD(&reg->hccr);
248		- }
	216	+ while (timer--) {
249	217	udelay(5);
	218	+ stat = rd_reg_dword(&reg->host_status);
	219	+
	220	+ /* Check for pending interrupts. */
	221	+ if (!(stat & HSRX_RISC_INT))
	222	+ continue;
	223	+
	224	+ stat &= 0xff;
	225	+ if (stat != 0x1 && stat != 0x2 &&
	226	+ stat != 0x10 && stat != 0x11) {
	227	+ wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT);
	228	+ rd_reg_dword(&reg->hccr);
	229	+ continue;
	230	+ }
	231	+
	232	+ set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
	233	+ rval = rd_reg_word(&reg->mailbox0) & MBS_MASK;
	234	+ wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT);
	235	+ rd_reg_dword(&reg->hccr);
	236	+ break;
250	237	}
251	238	ha->flags.mbox_int = 1;
	239	+ *nxt = ram + i;
252	240
253		- if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
254		- rval = mb0 & MBS_MASK;
255		- for (idx = 0; idx < dwords; idx++)
256		- ram[cnt + idx] = IS_QLA27XX(ha) ?
257		- le32_to_cpu(dump[idx]) : swab32(dump[idx]);
258		- } else {
259		- rval = QLA_FUNCTION_FAILED;
	241	+ if (!test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
	242	+ /* no interrupt, timed out*/
	243	+ return rval;
	244	+ }
	245	+ if (rval) {
	246	+ /* error completion status */
	247	+ return rval;
	248	+ }
	249	+ for (j = 0; j < dwords; j++) {
	250	+ ram[i + j] = (__force __be32)
	251	+ ((IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) ?
	252	+ chunk[j] : swab32(chunk[j]));
260	253	}
261	254	}
262	255
263		- *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
264		- return rval;
	256	+ *nxt = ram + i;
	257	+ return QLA_SUCCESS;
265	258	}
266	259
267	260	static int
268		-qla24xx_dump_memory(struct qla_hw_data ha, uint32_t code_ram,
269		- uint32_t cram_size, void **nxt)
	261	+qla24xx_dump_memory(struct qla_hw_data ha, __be32 code_ram,
	262	+ uint32_t cram_size, void **nxt)
270	263	{
271	264	int rval;
272	265
..	..	@@ -286,16 +279,16 @@
286	279	return rval;
287	280	}
288	281
289		-static uint32_t *
	282	+static __be32 *
290	283	qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
291		- uint32_t count, uint32_t *buf)
	284	+ uint32_t count, __be32 *buf)
292	285	{
293		- uint32_t __iomem *dmp_reg;
	286	+ __le32 __iomem *dmp_reg;
294	287
295		- WRT_REG_DWORD(&reg->iobase_addr, iobase);
	288	+ wrt_reg_dword(&reg->iobase_addr, iobase);
296	289	dmp_reg = &reg->iobase_window;
297	290	for ( ; count--; dmp_reg++)
298		- *buf++ = htonl(RD_REG_DWORD(dmp_reg));
	291	+ *buf++ = htonl(rd_reg_dword(dmp_reg));
299	292
300	293	return buf;
301	294	}
..	..	@@ -303,11 +296,11 @@
303	296	void
304	297	qla24xx_pause_risc(struct device_reg_24xx __iomem reg, struct qla_hw_data ha)
305	298	{
306		- WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
	299	+ wrt_reg_dword(&reg->hccr, HCCRX_SET_RISC_PAUSE);
307	300
308	301	/* 100 usec delay is sufficient enough for hardware to pause RISC */
309	302	udelay(100);
310		- if (RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED)
	303	+ if (rd_reg_dword(&reg->host_status) & HSRX_RISC_PAUSED)
311	304	set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags);
312	305	}
313	306
..	..	@@ -324,17 +317,17 @@
324	317	* Driver can proceed with the reset sequence after waiting
325	318	* for a timeout period.
326	319	*/
327		- WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
	320	+ wrt_reg_dword(&reg->ctrl_status, CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
328	321	for (cnt = 0; cnt < 30000; cnt++) {
329		- if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
	322	+ if ((rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
330	323	break;
331	324
332	325	udelay(10);
333	326	}
334		- if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
	327	+ if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
335	328	set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
336	329
337		- WRT_REG_DWORD(&reg->ctrl_status,
	330	+ wrt_reg_dword(&reg->ctrl_status,
338	331	CSRX_ISP_SOFT_RESET\|CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
339	332	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
340	333
..	..	@@ -342,19 +335,19 @@
342	335
343	336	/* Wait for soft-reset to complete. */
344	337	for (cnt = 0; cnt < 30000; cnt++) {
345		- if ((RD_REG_DWORD(&reg->ctrl_status) &
	338	+ if ((rd_reg_dword(&reg->ctrl_status) &
346	339	CSRX_ISP_SOFT_RESET) == 0)
347	340	break;
348	341
349	342	udelay(10);
350	343	}
351		- if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
	344	+ if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
352	345	set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags);
353	346
354		- WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
355		- RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
	347	+ wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_RESET);
	348	+ rd_reg_dword(&reg->hccr); /* PCI Posting. */
356	349
357		- for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
	350	+ for (cnt = 10000; rd_reg_word(&reg->mailbox0) != 0 &&
358	351	rval == QLA_SUCCESS; cnt--) {
359	352	if (cnt)
360	353	udelay(10);
..	..	@@ -368,7 +361,7 @@
368	361	}
369	362
370	363	static int
371		-qla2xxx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint16_t ram,
	364	+qla2xxx_dump_ram(struct qla_hw_data ha, uint32_t addr, __be16 ram,
372	365	uint32_t ram_words, void **nxt)
373	366	{
374	367	int rval;
..	..	@@ -376,7 +369,7 @@
376	369	uint16_t mb0;
377	370	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
378	371	dma_addr_t dump_dma = ha->gid_list_dma;
379		- uint16_t dump = (uint16_t )ha->gid_list;
	372	+ __le16 dump = (__force __le16 )ha->gid_list;
380	373
381	374	rval = QLA_SUCCESS;
382	375	mb0 = 0;
..	..	@@ -399,11 +392,11 @@
399	392	WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
400	393
401	394	WRT_MAILBOX_REG(ha, reg, 4, words);
402		- WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
	395	+ wrt_reg_word(&reg->hccr, HCCR_SET_HOST_INT);
403	396
404	397	for (timer = 6000000; timer; timer--) {
405	398	/* Check for pending interrupts. */
406		- stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
	399	+ stat = rd_reg_dword(&reg->u.isp2300.host_status);
407	400	if (stat & HSR_RISC_INT) {
408	401	stat &= 0xff;
409	402
..	..	@@ -414,10 +407,10 @@
414	407	mb0 = RD_MAILBOX_REG(ha, reg, 0);
415	408
416	409	/* Release mailbox registers. */
417		- WRT_REG_WORD(&reg->semaphore, 0);
418		- WRT_REG_WORD(&reg->hccr,
	410	+ wrt_reg_word(&reg->semaphore, 0);
	411	+ wrt_reg_word(&reg->hccr,
419	412	HCCR_CLR_RISC_INT);
420		- RD_REG_WORD(&reg->hccr);
	413	+ rd_reg_word(&reg->hccr);
421	414	break;
422	415	} else if (stat == 0x10 \|\| stat == 0x11) {
423	416	set_bit(MBX_INTERRUPT,
..	..	@@ -425,15 +418,15 @@
425	418
426	419	mb0 = RD_MAILBOX_REG(ha, reg, 0);
427	420
428		- WRT_REG_WORD(&reg->hccr,
	421	+ wrt_reg_word(&reg->hccr,
429	422	HCCR_CLR_RISC_INT);
430		- RD_REG_WORD(&reg->hccr);
	423	+ rd_reg_word(&reg->hccr);
431	424	break;
432	425	}
433	426
434	427	/* clear this intr; it wasn't a mailbox intr */
435		- WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
436		- RD_REG_WORD(&reg->hccr);
	428	+ wrt_reg_word(&reg->hccr, HCCR_CLR_RISC_INT);
	429	+ rd_reg_word(&reg->hccr);
437	430	}
438	431	udelay(5);
439	432	}
..	..	@@ -441,24 +434,25 @@
441	434	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
442	435	rval = mb0 & MBS_MASK;
443	436	for (idx = 0; idx < words; idx++)
444		- ram[cnt + idx] = swab16(dump[idx]);
	437	+ ram[cnt + idx] =
	438	+ cpu_to_be16(le16_to_cpu(dump[idx]));
445	439	} else {
446	440	rval = QLA_FUNCTION_FAILED;
447	441	}
448	442	}
449	443
450		- *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
	444	+ *nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL;
451	445	return rval;
452	446	}
453	447
454	448	static inline void
455	449	qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
456		- uint16_t *buf)
	450	+ __be16 *buf)
457	451	{
458		- uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
	452	+ __le16 __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
459	453
460	454	for ( ; count--; dmp_reg++)
461		- *buf++ = htons(RD_REG_WORD(dmp_reg));
	455	+ *buf++ = htons(rd_reg_word(dmp_reg));
462	456	}
463	457
464	458	static inline void *
..	..	@@ -472,10 +466,10 @@
472	466	}
473	467
474	468	static inline void *
475		-qla25xx_copy_fce(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
	469	+qla25xx_copy_fce(struct qla_hw_data ha, void ptr, __be32 **last_chain)
476	470	{
477	471	uint32_t cnt;
478		- uint32_t *iter_reg;
	472	+ __be32 *iter_reg;
479	473	struct qla2xxx_fce_chain *fcec = ptr;
480	474
481	475	if (!ha->fce)
..	..	@@ -499,7 +493,7 @@
499	493	}
500	494
501	495	static inline void *
502		-qla25xx_copy_exlogin(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
	496	+qla25xx_copy_exlogin(struct qla_hw_data ha, void ptr, __be32 **last_chain)
503	497	{
504	498	struct qla2xxx_offld_chain *c = ptr;
505	499
..	..	@@ -517,11 +511,11 @@
517	511	ptr += sizeof(struct qla2xxx_offld_chain);
518	512	memcpy(ptr, ha->exlogin_buf, ha->exlogin_size);
519	513
520		- return (char *)ptr + cpu_to_be32(c->size);
	514	+ return (char *)ptr + be32_to_cpu(c->size);
521	515	}
522	516
523	517	static inline void *
524		-qla81xx_copy_exchoffld(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
	518	+qla81xx_copy_exchoffld(struct qla_hw_data ha, void ptr, __be32 **last_chain)
525	519	{
526	520	struct qla2xxx_offld_chain *c = ptr;
527	521
..	..	@@ -539,12 +533,12 @@
539	533	ptr += sizeof(struct qla2xxx_offld_chain);
540	534	memcpy(ptr, ha->exchoffld_buf, ha->exchoffld_size);
541	535
542		- return (char *)ptr + cpu_to_be32(c->size);
	536	+ return (char *)ptr + be32_to_cpu(c->size);
543	537	}
544	538
545	539	static inline void *
546	540	qla2xxx_copy_atioqueues(struct qla_hw_data ha, void ptr,
547		- uint32_t **last_chain)
	541	+ __be32 **last_chain)
548	542	{
549	543	struct qla2xxx_mqueue_chain *q;
550	544	struct qla2xxx_mqueue_header *qh;
..	..	@@ -591,7 +585,7 @@
591	585	}
592	586
593	587	static inline void *
594		-qla25xx_copy_mqueues(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
	588	+qla25xx_copy_mqueues(struct qla_hw_data ha, void ptr, __be32 **last_chain)
595	589	{
596	590	struct qla2xxx_mqueue_chain *q;
597	591	struct qla2xxx_mqueue_header *qh;
..	..	@@ -662,14 +656,15 @@
662	656	}
663	657
664	658	static inline void *
665		-qla25xx_copy_mq(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
	659	+qla25xx_copy_mq(struct qla_hw_data ha, void ptr, __be32 **last_chain)
666	660	{
667	661	uint32_t cnt, que_idx;
668	662	uint8_t que_cnt;
669	663	struct qla2xxx_mq_chain *mq = ptr;
670	664	device_reg_t *reg;
671	665
672		- if (!ha->mqenable \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	666	+ if (!ha->mqenable \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\|
	667	+ IS_QLA28XX(ha))
673	668	return ptr;
674	669
675	670	mq = ptr;
..	..	@@ -684,13 +679,13 @@
684	679	reg = ISP_QUE_REG(ha, cnt);
685	680	que_idx = cnt * 4;
686	681	mq->qregs[que_idx] =
687		- htonl(RD_REG_DWORD(&reg->isp25mq.req_q_in));
	682	+ htonl(rd_reg_dword(&reg->isp25mq.req_q_in));
688	683	mq->qregs[que_idx+1] =
689		- htonl(RD_REG_DWORD(&reg->isp25mq.req_q_out));
	684	+ htonl(rd_reg_dword(&reg->isp25mq.req_q_out));
690	685	mq->qregs[que_idx+2] =
691		- htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_in));
	686	+ htonl(rd_reg_dword(&reg->isp25mq.rsp_q_in));
692	687	mq->qregs[que_idx+3] =
693		- htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_out));
	688	+ htonl(rd_reg_dword(&reg->isp25mq.rsp_q_out));
694	689	}
695	690
696	691	return ptr + sizeof(struct qla2xxx_mq_chain);
..	..	@@ -705,45 +700,47 @@
705	700	ql_log(ql_log_warn, vha, 0xd000,
706	701	"Failed to dump firmware (%x), dump status flags (0x%lx).\n",
707	702	rval, ha->fw_dump_cap_flags);
708		- ha->fw_dumped = 0;
	703	+ ha->fw_dumped = false;
709	704	} else {
710	705	ql_log(ql_log_info, vha, 0xd001,
711	706	"Firmware dump saved to temp buffer (%ld/%p), dump status flags (0x%lx).\n",
712	707	vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags);
713		- ha->fw_dumped = 1;
	708	+ ha->fw_dumped = true;
714	709	qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
715	710	}
	711	+}
	712	+
	713	+void qla2xxx_dump_fw(scsi_qla_host_t *vha)
	714	+{
	715	+ unsigned long flags;
	716	+
	717	+ spin_lock_irqsave(&vha->hw->hardware_lock, flags);
	718	+ vha->hw->isp_ops->fw_dump(vha);
	719	+ spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
716	720	}
717	721
718	722	/**
719	723	* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
720	724	* @vha: HA context
721		- * @hardware_locked: Called with the hardware_lock
722	725	*/
723	726	void
724		-qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
	727	+qla2300_fw_dump(scsi_qla_host_t *vha)
725	728	{
726	729	int rval;
727	730	uint32_t cnt;
728	731	struct qla_hw_data *ha = vha->hw;
729	732	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
730		- uint16_t __iomem *dmp_reg;
731		- unsigned long flags;
	733	+ __le16 __iomem *dmp_reg;
732	734	struct qla2300_fw_dump *fw;
733	735	void *nxt;
734	736	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
735	737
736		- flags = 0;
737		-
738		-#ifndef __CHECKER__
739		- if (!hardware_locked)
740		- spin_lock_irqsave(&ha->hardware_lock, flags);
741		-#endif
	738	+ lockdep_assert_held(&ha->hardware_lock);
742	739
743	740	if (!ha->fw_dump) {
744	741	ql_log(ql_log_warn, vha, 0xd002,
745	742	"No buffer available for dump.\n");
746		- goto qla2300_fw_dump_failed;
	743	+ return;
747	744	}
748	745
749	746	if (ha->fw_dumped) {
..	..	@@ -751,19 +748,19 @@
751	748	"Firmware has been previously dumped (%p) "
752	749	"-- ignoring request.\n",
753	750	ha->fw_dump);
754		- goto qla2300_fw_dump_failed;
	751	+ return;
755	752	}
756	753	fw = &ha->fw_dump->isp.isp23;
757	754	qla2xxx_prep_dump(ha, ha->fw_dump);
758	755
759	756	rval = QLA_SUCCESS;
760		- fw->hccr = htons(RD_REG_WORD(&reg->hccr));
	757	+ fw->hccr = htons(rd_reg_word(&reg->hccr));
761	758
762	759	/* Pause RISC. */
763		- WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
	760	+ wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);
764	761	if (IS_QLA2300(ha)) {
765	762	for (cnt = 30000;
766		- (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
	763	+ (rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
767	764	rval == QLA_SUCCESS; cnt--) {
768	765	if (cnt)
769	766	udelay(100);
..	..	@@ -771,74 +768,74 @@
771	768	rval = QLA_FUNCTION_TIMEOUT;
772	769	}
773	770	} else {
774		- RD_REG_WORD(&reg->hccr); /* PCI Posting. */
	771	+ rd_reg_word(&reg->hccr); /* PCI Posting. */
775	772	udelay(10);
776	773	}
777	774
778	775	if (rval == QLA_SUCCESS) {
779	776	dmp_reg = &reg->flash_address;
780		- for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++, dmp_reg++)
781		- fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	777	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->pbiu_reg); cnt++, dmp_reg++)
	778	+ fw->pbiu_reg[cnt] = htons(rd_reg_word(dmp_reg));
782	779
783	780	dmp_reg = &reg->u.isp2300.req_q_in;
784		- for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2;
	781	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_host_reg);
785	782	cnt++, dmp_reg++)
786		- fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	783	+ fw->risc_host_reg[cnt] = htons(rd_reg_word(dmp_reg));
787	784
788	785	dmp_reg = &reg->u.isp2300.mailbox0;
789		- for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2;
	786	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg);
790	787	cnt++, dmp_reg++)
791		- fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	788	+ fw->mailbox_reg[cnt] = htons(rd_reg_word(dmp_reg));
792	789
793		- WRT_REG_WORD(&reg->ctrl_status, 0x40);
	790	+ wrt_reg_word(&reg->ctrl_status, 0x40);
794	791	qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
795	792
796		- WRT_REG_WORD(&reg->ctrl_status, 0x50);
	793	+ wrt_reg_word(&reg->ctrl_status, 0x50);
797	794	qla2xxx_read_window(reg, 48, fw->dma_reg);
798	795
799		- WRT_REG_WORD(&reg->ctrl_status, 0x00);
	796	+ wrt_reg_word(&reg->ctrl_status, 0x00);
800	797	dmp_reg = &reg->risc_hw;
801		- for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2;
	798	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_hdw_reg);
802	799	cnt++, dmp_reg++)
803		- fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	800	+ fw->risc_hdw_reg[cnt] = htons(rd_reg_word(dmp_reg));
804	801
805		- WRT_REG_WORD(&reg->pcr, 0x2000);
	802	+ wrt_reg_word(&reg->pcr, 0x2000);
806	803	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
807	804
808		- WRT_REG_WORD(&reg->pcr, 0x2200);
	805	+ wrt_reg_word(&reg->pcr, 0x2200);
809	806	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
810	807
811		- WRT_REG_WORD(&reg->pcr, 0x2400);
	808	+ wrt_reg_word(&reg->pcr, 0x2400);
812	809	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
813	810
814		- WRT_REG_WORD(&reg->pcr, 0x2600);
	811	+ wrt_reg_word(&reg->pcr, 0x2600);
815	812	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
816	813
817		- WRT_REG_WORD(&reg->pcr, 0x2800);
	814	+ wrt_reg_word(&reg->pcr, 0x2800);
818	815	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
819	816
820		- WRT_REG_WORD(&reg->pcr, 0x2A00);
	817	+ wrt_reg_word(&reg->pcr, 0x2A00);
821	818	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
822	819
823		- WRT_REG_WORD(&reg->pcr, 0x2C00);
	820	+ wrt_reg_word(&reg->pcr, 0x2C00);
824	821	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
825	822
826		- WRT_REG_WORD(&reg->pcr, 0x2E00);
	823	+ wrt_reg_word(&reg->pcr, 0x2E00);
827	824	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
828	825
829		- WRT_REG_WORD(&reg->ctrl_status, 0x10);
	826	+ wrt_reg_word(&reg->ctrl_status, 0x10);
830	827	qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
831	828
832		- WRT_REG_WORD(&reg->ctrl_status, 0x20);
	829	+ wrt_reg_word(&reg->ctrl_status, 0x20);
833	830	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
834	831
835		- WRT_REG_WORD(&reg->ctrl_status, 0x30);
	832	+ wrt_reg_word(&reg->ctrl_status, 0x30);
836	833	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
837	834
838	835	/* Reset RISC. */
839		- WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
	836	+ wrt_reg_word(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
840	837	for (cnt = 0; cnt < 30000; cnt++) {
841		- if ((RD_REG_WORD(&reg->ctrl_status) &
	838	+ if ((rd_reg_word(&reg->ctrl_status) &
842	839	CSR_ISP_SOFT_RESET) == 0)
843	840	break;
844	841
..	..	@@ -859,12 +856,12 @@
859	856	/* Get RISC SRAM. */
860	857	if (rval == QLA_SUCCESS)
861	858	rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
862		- sizeof(fw->risc_ram) / 2, &nxt);
	859	+ ARRAY_SIZE(fw->risc_ram), &nxt);
863	860
864	861	/* Get stack SRAM. */
865	862	if (rval == QLA_SUCCESS)
866	863	rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
867		- sizeof(fw->stack_ram) / 2, &nxt);
	864	+ ARRAY_SIZE(fw->stack_ram), &nxt);
868	865
869	866	/* Get data SRAM. */
870	867	if (rval == QLA_SUCCESS)
..	..	@@ -875,48 +872,31 @@
875	872	qla2xxx_copy_queues(ha, nxt);
876	873
877	874	qla2xxx_dump_post_process(base_vha, rval);
878		-
879		-qla2300_fw_dump_failed:
880		-#ifndef __CHECKER__
881		- if (!hardware_locked)
882		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
883		-#else
884		- ;
885		-#endif
886	875	}
887	876
888	877	/**
889	878	* qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
890	879	* @vha: HA context
891		- * @hardware_locked: Called with the hardware_lock
892	880	*/
893	881	void
894		-qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
	882	+qla2100_fw_dump(scsi_qla_host_t *vha)
895	883	{
896	884	int rval;
897	885	uint32_t cnt, timer;
898		- uint16_t risc_address;
899		- uint16_t mb0, mb2;
	886	+ uint16_t risc_address = 0;
	887	+ uint16_t mb0 = 0, mb2 = 0;
900	888	struct qla_hw_data *ha = vha->hw;
901	889	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
902		- uint16_t __iomem *dmp_reg;
903		- unsigned long flags;
	890	+ __le16 __iomem *dmp_reg;
904	891	struct qla2100_fw_dump *fw;
905	892	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
906	893
907		- risc_address = 0;
908		- mb0 = mb2 = 0;
909		- flags = 0;
910		-
911		-#ifndef __CHECKER__
912		- if (!hardware_locked)
913		- spin_lock_irqsave(&ha->hardware_lock, flags);
914		-#endif
	894	+ lockdep_assert_held(&ha->hardware_lock);
915	895
916	896	if (!ha->fw_dump) {
917	897	ql_log(ql_log_warn, vha, 0xd004,
918	898	"No buffer available for dump.\n");
919		- goto qla2100_fw_dump_failed;
	899	+ return;
920	900	}
921	901
922	902	if (ha->fw_dumped) {
..	..	@@ -924,17 +904,17 @@
924	904	"Firmware has been previously dumped (%p) "
925	905	"-- ignoring request.\n",
926	906	ha->fw_dump);
927		- goto qla2100_fw_dump_failed;
	907	+ return;
928	908	}
929	909	fw = &ha->fw_dump->isp.isp21;
930	910	qla2xxx_prep_dump(ha, ha->fw_dump);
931	911
932	912	rval = QLA_SUCCESS;
933		- fw->hccr = htons(RD_REG_WORD(&reg->hccr));
	913	+ fw->hccr = htons(rd_reg_word(&reg->hccr));
934	914
935	915	/* Pause RISC. */
936		- WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
937		- for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
	916	+ wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);
	917	+ for (cnt = 30000; (rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
938	918	rval == QLA_SUCCESS; cnt--) {
939	919	if (cnt)
940	920	udelay(100);
..	..	@@ -943,61 +923,61 @@
943	923	}
944	924	if (rval == QLA_SUCCESS) {
945	925	dmp_reg = &reg->flash_address;
946		- for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++, dmp_reg++)
947		- fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	926	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->pbiu_reg); cnt++, dmp_reg++)
	927	+ fw->pbiu_reg[cnt] = htons(rd_reg_word(dmp_reg));
948	928
949	929	dmp_reg = &reg->u.isp2100.mailbox0;
950	930	for (cnt = 0; cnt < ha->mbx_count; cnt++, dmp_reg++) {
951	931	if (cnt == 8)
952	932	dmp_reg = &reg->u_end.isp2200.mailbox8;
953	933
954		- fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	934	+ fw->mailbox_reg[cnt] = htons(rd_reg_word(dmp_reg));
955	935	}
956	936
957	937	dmp_reg = &reg->u.isp2100.unused_2[0];
958		- for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++, dmp_reg++)
959		- fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	938	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->dma_reg); cnt++, dmp_reg++)
	939	+ fw->dma_reg[cnt] = htons(rd_reg_word(dmp_reg));
960	940
961		- WRT_REG_WORD(&reg->ctrl_status, 0x00);
	941	+ wrt_reg_word(&reg->ctrl_status, 0x00);
962	942	dmp_reg = &reg->risc_hw;
963		- for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++, dmp_reg++)
964		- fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
	943	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_hdw_reg); cnt++, dmp_reg++)
	944	+ fw->risc_hdw_reg[cnt] = htons(rd_reg_word(dmp_reg));
965	945
966		- WRT_REG_WORD(&reg->pcr, 0x2000);
	946	+ wrt_reg_word(&reg->pcr, 0x2000);
967	947	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
968	948
969		- WRT_REG_WORD(&reg->pcr, 0x2100);
	949	+ wrt_reg_word(&reg->pcr, 0x2100);
970	950	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
971	951
972		- WRT_REG_WORD(&reg->pcr, 0x2200);
	952	+ wrt_reg_word(&reg->pcr, 0x2200);
973	953	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
974	954
975		- WRT_REG_WORD(&reg->pcr, 0x2300);
	955	+ wrt_reg_word(&reg->pcr, 0x2300);
976	956	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
977	957
978		- WRT_REG_WORD(&reg->pcr, 0x2400);
	958	+ wrt_reg_word(&reg->pcr, 0x2400);
979	959	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
980	960
981		- WRT_REG_WORD(&reg->pcr, 0x2500);
	961	+ wrt_reg_word(&reg->pcr, 0x2500);
982	962	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
983	963
984		- WRT_REG_WORD(&reg->pcr, 0x2600);
	964	+ wrt_reg_word(&reg->pcr, 0x2600);
985	965	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
986	966
987		- WRT_REG_WORD(&reg->pcr, 0x2700);
	967	+ wrt_reg_word(&reg->pcr, 0x2700);
988	968	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
989	969
990		- WRT_REG_WORD(&reg->ctrl_status, 0x10);
	970	+ wrt_reg_word(&reg->ctrl_status, 0x10);
991	971	qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
992	972
993		- WRT_REG_WORD(&reg->ctrl_status, 0x20);
	973	+ wrt_reg_word(&reg->ctrl_status, 0x20);
994	974	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
995	975
996		- WRT_REG_WORD(&reg->ctrl_status, 0x30);
	976	+ wrt_reg_word(&reg->ctrl_status, 0x30);
997	977	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
998	978
999	979	/* Reset the ISP. */
1000		- WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
	980	+ wrt_reg_word(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1001	981	}
1002	982
1003	983	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
..	..	@@ -1010,11 +990,11 @@
1010	990
1011	991	/* Pause RISC. */
1012	992	if (rval == QLA_SUCCESS && (IS_QLA2200(ha) \|\| (IS_QLA2100(ha) &&
1013		- (RD_REG_WORD(&reg->mctr) & (BIT_1 \| BIT_0)) != 0))) {
	993	+ (rd_reg_word(&reg->mctr) & (BIT_1 \| BIT_0)) != 0))) {
1014	994
1015		- WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
	995	+ wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);
1016	996	for (cnt = 30000;
1017		- (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
	997	+ (rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
1018	998	rval == QLA_SUCCESS; cnt--) {
1019	999	if (cnt)
1020	1000	udelay(100);
..	..	@@ -1024,13 +1004,13 @@
1024	1004	if (rval == QLA_SUCCESS) {
1025	1005	/* Set memory configuration and timing. */
1026	1006	if (IS_QLA2100(ha))
1027		- WRT_REG_WORD(&reg->mctr, 0xf1);
	1007	+ wrt_reg_word(&reg->mctr, 0xf1);
1028	1008	else
1029		- WRT_REG_WORD(&reg->mctr, 0xf2);
1030		- RD_REG_WORD(&reg->mctr); /* PCI Posting. */
	1009	+ wrt_reg_word(&reg->mctr, 0xf2);
	1010	+ rd_reg_word(&reg->mctr); /* PCI Posting. */
1031	1011
1032	1012	/* Release RISC. */
1033		- WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
	1013	+ wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC);
1034	1014	}
1035	1015	}
1036	1016
..	..	@@ -1040,29 +1020,29 @@
1040	1020	WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
1041	1021	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
1042	1022	}
1043		- for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
	1023	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_ram) && rval == QLA_SUCCESS;
1044	1024	cnt++, risc_address++) {
1045	1025	WRT_MAILBOX_REG(ha, reg, 1, risc_address);
1046		- WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
	1026	+ wrt_reg_word(&reg->hccr, HCCR_SET_HOST_INT);
1047	1027
1048	1028	for (timer = 6000000; timer != 0; timer--) {
1049	1029	/* Check for pending interrupts. */
1050		- if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
1051		- if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
	1030	+ if (rd_reg_word(&reg->istatus) & ISR_RISC_INT) {
	1031	+ if (rd_reg_word(&reg->semaphore) & BIT_0) {
1052	1032	set_bit(MBX_INTERRUPT,
1053	1033	&ha->mbx_cmd_flags);
1054	1034
1055	1035	mb0 = RD_MAILBOX_REG(ha, reg, 0);
1056	1036	mb2 = RD_MAILBOX_REG(ha, reg, 2);
1057	1037
1058		- WRT_REG_WORD(&reg->semaphore, 0);
1059		- WRT_REG_WORD(&reg->hccr,
	1038	+ wrt_reg_word(&reg->semaphore, 0);
	1039	+ wrt_reg_word(&reg->hccr,
1060	1040	HCCR_CLR_RISC_INT);
1061		- RD_REG_WORD(&reg->hccr);
	1041	+ rd_reg_word(&reg->hccr);
1062	1042	break;
1063	1043	}
1064		- WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1065		- RD_REG_WORD(&reg->hccr);
	1044	+ wrt_reg_word(&reg->hccr, HCCR_CLR_RISC_INT);
	1045	+ rd_reg_word(&reg->hccr);
1066	1046	}
1067	1047	udelay(5);
1068	1048	}
..	..	@@ -1076,51 +1056,38 @@
1076	1056	}
1077	1057
1078	1058	if (rval == QLA_SUCCESS)
1079		- qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
	1059	+ qla2xxx_copy_queues(ha, &fw->queue_dump[0]);
1080	1060
1081	1061	qla2xxx_dump_post_process(base_vha, rval);
1082		-
1083		-qla2100_fw_dump_failed:
1084		-#ifndef __CHECKER__
1085		- if (!hardware_locked)
1086		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
1087		-#else
1088		- ;
1089		-#endif
1090	1062	}
1091	1063
1092	1064	void
1093		-qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
	1065	+qla24xx_fw_dump(scsi_qla_host_t *vha)
1094	1066	{
1095	1067	int rval;
1096	1068	uint32_t cnt;
1097	1069	struct qla_hw_data *ha = vha->hw;
1098	1070	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1099		- uint32_t __iomem *dmp_reg;
1100		- uint32_t *iter_reg;
1101		- uint16_t __iomem *mbx_reg;
1102		- unsigned long flags;
	1071	+ __le32 __iomem *dmp_reg;
	1072	+ __be32 *iter_reg;
	1073	+ __le16 __iomem *mbx_reg;
1103	1074	struct qla24xx_fw_dump *fw;
1104	1075	void *nxt;
1105	1076	void *nxt_chain;
1106		- uint32_t *last_chain = NULL;
	1077	+ __be32 *last_chain = NULL;
1107	1078	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
	1079	+
	1080	+ lockdep_assert_held(&ha->hardware_lock);
1108	1081
1109	1082	if (IS_P3P_TYPE(ha))
1110	1083	return;
1111	1084
1112		- flags = 0;
1113	1085	ha->fw_dump_cap_flags = 0;
1114		-
1115		-#ifndef __CHECKER__
1116		- if (!hardware_locked)
1117		- spin_lock_irqsave(&ha->hardware_lock, flags);
1118		-#endif
1119	1086
1120	1087	if (!ha->fw_dump) {
1121	1088	ql_log(ql_log_warn, vha, 0xd006,
1122	1089	"No buffer available for dump.\n");
1123		- goto qla24xx_fw_dump_failed;
	1090	+ return;
1124	1091	}
1125	1092
1126	1093	if (ha->fw_dumped) {
..	..	@@ -1128,13 +1095,13 @@
1128	1095	"Firmware has been previously dumped (%p) "
1129	1096	"-- ignoring request.\n",
1130	1097	ha->fw_dump);
1131		- goto qla24xx_fw_dump_failed;
	1098	+ return;
1132	1099	}
1133	1100	QLA_FW_STOPPED(ha);
1134	1101	fw = &ha->fw_dump->isp.isp24;
1135	1102	qla2xxx_prep_dump(ha, ha->fw_dump);
1136	1103
1137		- fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
	1104	+ fw->host_status = htonl(rd_reg_dword(&reg->host_status));
1138	1105
1139	1106	/*
1140	1107	* Pause RISC. No need to track timeout, as resetting the chip
..	..	@@ -1144,41 +1111,41 @@
1144	1111
1145	1112	/* Host interface registers. */
1146	1113	dmp_reg = &reg->flash_addr;
1147		- for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
1148		- fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
	1114	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++)
	1115	+ fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
1149	1116
1150	1117	/* Disable interrupts. */
1151		- WRT_REG_DWORD(&reg->ictrl, 0);
1152		- RD_REG_DWORD(&reg->ictrl);
	1118	+ wrt_reg_dword(&reg->ictrl, 0);
	1119	+ rd_reg_dword(&reg->ictrl);
1153	1120
1154	1121	/* Shadow registers. */
1155		- WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1156		- RD_REG_DWORD(&reg->iobase_addr);
1157		- WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1158		- fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1122	+ wrt_reg_dword(&reg->iobase_addr, 0x0F70);
	1123	+ rd_reg_dword(&reg->iobase_addr);
	1124	+ wrt_reg_dword(&reg->iobase_select, 0xB0000000);
	1125	+ fw->shadow_reg[0] = htonl(rd_reg_dword(&reg->iobase_sdata));
1159	1126
1160		- WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1161		- fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1127	+ wrt_reg_dword(&reg->iobase_select, 0xB0100000);
	1128	+ fw->shadow_reg[1] = htonl(rd_reg_dword(&reg->iobase_sdata));
1162	1129
1163		- WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1164		- fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1130	+ wrt_reg_dword(&reg->iobase_select, 0xB0200000);
	1131	+ fw->shadow_reg[2] = htonl(rd_reg_dword(&reg->iobase_sdata));
1165	1132
1166		- WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1167		- fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1133	+ wrt_reg_dword(&reg->iobase_select, 0xB0300000);
	1134	+ fw->shadow_reg[3] = htonl(rd_reg_dword(&reg->iobase_sdata));
1168	1135
1169		- WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1170		- fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1136	+ wrt_reg_dword(&reg->iobase_select, 0xB0400000);
	1137	+ fw->shadow_reg[4] = htonl(rd_reg_dword(&reg->iobase_sdata));
1171	1138
1172		- WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1173		- fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1139	+ wrt_reg_dword(&reg->iobase_select, 0xB0500000);
	1140	+ fw->shadow_reg[5] = htonl(rd_reg_dword(&reg->iobase_sdata));
1174	1141
1175		- WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1176		- fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1142	+ wrt_reg_dword(&reg->iobase_select, 0xB0600000);
	1143	+ fw->shadow_reg[6] = htonl(rd_reg_dword(&reg->iobase_sdata));
1177	1144
1178	1145	/* Mailbox registers. */
1179	1146	mbx_reg = &reg->mailbox0;
1180		- for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++)
1181		- fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
	1147	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++)
	1148	+ fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg));
1182	1149
1183	1150	/* Transfer sequence registers. */
1184	1151	iter_reg = fw->xseq_gp_reg;
..	..	@@ -1217,19 +1184,19 @@
1217	1184	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1218	1185	dmp_reg = &reg->iobase_q;
1219	1186	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1220		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1187	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1221	1188
1222	1189	iter_reg = fw->resp0_dma_reg;
1223	1190	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1224	1191	dmp_reg = &reg->iobase_q;
1225	1192	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1226		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1193	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1227	1194
1228	1195	iter_reg = fw->req1_dma_reg;
1229	1196	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1230	1197	dmp_reg = &reg->iobase_q;
1231	1198	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1232		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1199	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1233	1200
1234	1201	/* Transmit DMA registers. */
1235	1202	iter_reg = fw->xmt0_dma_reg;
..	..	@@ -1338,44 +1305,31 @@
1338	1305
1339	1306	qla24xx_fw_dump_failed_0:
1340	1307	qla2xxx_dump_post_process(base_vha, rval);
1341		-
1342		-qla24xx_fw_dump_failed:
1343		-#ifndef __CHECKER__
1344		- if (!hardware_locked)
1345		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
1346		-#else
1347		- ;
1348		-#endif
1349	1308	}
1350	1309
1351	1310	void
1352		-qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
	1311	+qla25xx_fw_dump(scsi_qla_host_t *vha)
1353	1312	{
1354	1313	int rval;
1355	1314	uint32_t cnt;
1356	1315	struct qla_hw_data *ha = vha->hw;
1357	1316	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1358		- uint32_t __iomem *dmp_reg;
1359		- uint32_t *iter_reg;
1360		- uint16_t __iomem *mbx_reg;
1361		- unsigned long flags;
	1317	+ __le32 __iomem *dmp_reg;
	1318	+ __be32 *iter_reg;
	1319	+ __le16 __iomem *mbx_reg;
1362	1320	struct qla25xx_fw_dump *fw;
1363	1321	void nxt, nxt_chain;
1364		- uint32_t *last_chain = NULL;
	1322	+ __be32 *last_chain = NULL;
1365	1323	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1366	1324
1367		- flags = 0;
1368		- ha->fw_dump_cap_flags = 0;
	1325	+ lockdep_assert_held(&ha->hardware_lock);
1369	1326
1370		-#ifndef __CHECKER__
1371		- if (!hardware_locked)
1372		- spin_lock_irqsave(&ha->hardware_lock, flags);
1373		-#endif
	1327	+ ha->fw_dump_cap_flags = 0;
1374	1328
1375	1329	if (!ha->fw_dump) {
1376	1330	ql_log(ql_log_warn, vha, 0xd008,
1377	1331	"No buffer available for dump.\n");
1378		- goto qla25xx_fw_dump_failed;
	1332	+ return;
1379	1333	}
1380	1334
1381	1335	if (ha->fw_dumped) {
..	..	@@ -1383,14 +1337,14 @@
1383	1337	"Firmware has been previously dumped (%p) "
1384	1338	"-- ignoring request.\n",
1385	1339	ha->fw_dump);
1386		- goto qla25xx_fw_dump_failed;
	1340	+ return;
1387	1341	}
1388	1342	QLA_FW_STOPPED(ha);
1389	1343	fw = &ha->fw_dump->isp.isp25;
1390	1344	qla2xxx_prep_dump(ha, ha->fw_dump);
1391	1345	ha->fw_dump->version = htonl(2);
1392	1346
1393		- fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
	1347	+ fw->host_status = htonl(rd_reg_dword(&reg->host_status));
1394	1348
1395	1349	/*
1396	1350	* Pause RISC. No need to track timeout, as resetting the chip
..	..	@@ -1404,73 +1358,73 @@
1404	1358	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1405	1359
1406	1360	/* PCIe registers. */
1407		- WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1408		- RD_REG_DWORD(&reg->iobase_addr);
1409		- WRT_REG_DWORD(&reg->iobase_window, 0x01);
	1361	+ wrt_reg_dword(&reg->iobase_addr, 0x7C00);
	1362	+ rd_reg_dword(&reg->iobase_addr);
	1363	+ wrt_reg_dword(&reg->iobase_window, 0x01);
1410	1364	dmp_reg = &reg->iobase_c4;
1411		- fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg));
	1365	+ fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg));
1412	1366	dmp_reg++;
1413		- fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg));
	1367	+ fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg));
1414	1368	dmp_reg++;
1415		- fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1416		- fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
	1369	+ fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg));
	1370	+ fw->pcie_regs[3] = htonl(rd_reg_dword(&reg->iobase_window));
1417	1371
1418		- WRT_REG_DWORD(&reg->iobase_window, 0x00);
1419		- RD_REG_DWORD(&reg->iobase_window);
	1372	+ wrt_reg_dword(&reg->iobase_window, 0x00);
	1373	+ rd_reg_dword(&reg->iobase_window);
1420	1374
1421	1375	/* Host interface registers. */
1422	1376	dmp_reg = &reg->flash_addr;
1423		- for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
1424		- fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
	1377	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++)
	1378	+ fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
1425	1379
1426	1380	/* Disable interrupts. */
1427		- WRT_REG_DWORD(&reg->ictrl, 0);
1428		- RD_REG_DWORD(&reg->ictrl);
	1381	+ wrt_reg_dword(&reg->ictrl, 0);
	1382	+ rd_reg_dword(&reg->ictrl);
1429	1383
1430	1384	/* Shadow registers. */
1431		- WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1432		- RD_REG_DWORD(&reg->iobase_addr);
1433		- WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1434		- fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1385	+ wrt_reg_dword(&reg->iobase_addr, 0x0F70);
	1386	+ rd_reg_dword(&reg->iobase_addr);
	1387	+ wrt_reg_dword(&reg->iobase_select, 0xB0000000);
	1388	+ fw->shadow_reg[0] = htonl(rd_reg_dword(&reg->iobase_sdata));
1435	1389
1436		- WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1437		- fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1390	+ wrt_reg_dword(&reg->iobase_select, 0xB0100000);
	1391	+ fw->shadow_reg[1] = htonl(rd_reg_dword(&reg->iobase_sdata));
1438	1392
1439		- WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1440		- fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1393	+ wrt_reg_dword(&reg->iobase_select, 0xB0200000);
	1394	+ fw->shadow_reg[2] = htonl(rd_reg_dword(&reg->iobase_sdata));
1441	1395
1442		- WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1443		- fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1396	+ wrt_reg_dword(&reg->iobase_select, 0xB0300000);
	1397	+ fw->shadow_reg[3] = htonl(rd_reg_dword(&reg->iobase_sdata));
1444	1398
1445		- WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1446		- fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1399	+ wrt_reg_dword(&reg->iobase_select, 0xB0400000);
	1400	+ fw->shadow_reg[4] = htonl(rd_reg_dword(&reg->iobase_sdata));
1447	1401
1448		- WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1449		- fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1402	+ wrt_reg_dword(&reg->iobase_select, 0xB0500000);
	1403	+ fw->shadow_reg[5] = htonl(rd_reg_dword(&reg->iobase_sdata));
1450	1404
1451		- WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1452		- fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1405	+ wrt_reg_dword(&reg->iobase_select, 0xB0600000);
	1406	+ fw->shadow_reg[6] = htonl(rd_reg_dword(&reg->iobase_sdata));
1453	1407
1454		- WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1455		- fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1408	+ wrt_reg_dword(&reg->iobase_select, 0xB0700000);
	1409	+ fw->shadow_reg[7] = htonl(rd_reg_dword(&reg->iobase_sdata));
1456	1410
1457		- WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1458		- fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1411	+ wrt_reg_dword(&reg->iobase_select, 0xB0800000);
	1412	+ fw->shadow_reg[8] = htonl(rd_reg_dword(&reg->iobase_sdata));
1459	1413
1460		- WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1461		- fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1414	+ wrt_reg_dword(&reg->iobase_select, 0xB0900000);
	1415	+ fw->shadow_reg[9] = htonl(rd_reg_dword(&reg->iobase_sdata));
1462	1416
1463		- WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1464		- fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1417	+ wrt_reg_dword(&reg->iobase_select, 0xB0A00000);
	1418	+ fw->shadow_reg[10] = htonl(rd_reg_dword(&reg->iobase_sdata));
1465	1419
1466	1420	/* RISC I/O register. */
1467		- WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1468		- fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
	1421	+ wrt_reg_dword(&reg->iobase_addr, 0x0010);
	1422	+ fw->risc_io_reg = htonl(rd_reg_dword(&reg->iobase_window));
1469	1423
1470	1424	/* Mailbox registers. */
1471	1425	mbx_reg = &reg->mailbox0;
1472		- for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++)
1473		- fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
	1426	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++)
	1427	+ fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg));
1474	1428
1475	1429	/* Transfer sequence registers. */
1476	1430	iter_reg = fw->xseq_gp_reg;
..	..	@@ -1534,19 +1488,19 @@
1534	1488	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1535	1489	dmp_reg = &reg->iobase_q;
1536	1490	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1537		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1491	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1538	1492
1539	1493	iter_reg = fw->resp0_dma_reg;
1540	1494	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1541	1495	dmp_reg = &reg->iobase_q;
1542	1496	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1543		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1497	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1544	1498
1545	1499	iter_reg = fw->req1_dma_reg;
1546	1500	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1547	1501	dmp_reg = &reg->iobase_q;
1548	1502	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1549		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1503	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1550	1504
1551	1505	/* Transmit DMA registers. */
1552	1506	iter_reg = fw->xmt0_dma_reg;
..	..	@@ -1664,44 +1618,31 @@
1664	1618
1665	1619	qla25xx_fw_dump_failed_0:
1666	1620	qla2xxx_dump_post_process(base_vha, rval);
1667		-
1668		-qla25xx_fw_dump_failed:
1669		-#ifndef __CHECKER__
1670		- if (!hardware_locked)
1671		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
1672		-#else
1673		- ;
1674		-#endif
1675	1621	}
1676	1622
1677	1623	void
1678		-qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
	1624	+qla81xx_fw_dump(scsi_qla_host_t *vha)
1679	1625	{
1680	1626	int rval;
1681	1627	uint32_t cnt;
1682	1628	struct qla_hw_data *ha = vha->hw;
1683	1629	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1684		- uint32_t __iomem *dmp_reg;
1685		- uint32_t *iter_reg;
1686		- uint16_t __iomem *mbx_reg;
1687		- unsigned long flags;
	1630	+ __le32 __iomem *dmp_reg;
	1631	+ __be32 *iter_reg;
	1632	+ __le16 __iomem *mbx_reg;
1688	1633	struct qla81xx_fw_dump *fw;
1689	1634	void nxt, nxt_chain;
1690		- uint32_t *last_chain = NULL;
	1635	+ __be32 *last_chain = NULL;
1691	1636	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1692	1637
1693		- flags = 0;
1694		- ha->fw_dump_cap_flags = 0;
	1638	+ lockdep_assert_held(&ha->hardware_lock);
1695	1639
1696		-#ifndef __CHECKER__
1697		- if (!hardware_locked)
1698		- spin_lock_irqsave(&ha->hardware_lock, flags);
1699		-#endif
	1640	+ ha->fw_dump_cap_flags = 0;
1700	1641
1701	1642	if (!ha->fw_dump) {
1702	1643	ql_log(ql_log_warn, vha, 0xd00a,
1703	1644	"No buffer available for dump.\n");
1704		- goto qla81xx_fw_dump_failed;
	1645	+ return;
1705	1646	}
1706	1647
1707	1648	if (ha->fw_dumped) {
..	..	@@ -1709,12 +1650,12 @@
1709	1650	"Firmware has been previously dumped (%p) "
1710	1651	"-- ignoring request.\n",
1711	1652	ha->fw_dump);
1712		- goto qla81xx_fw_dump_failed;
	1653	+ return;
1713	1654	}
1714	1655	fw = &ha->fw_dump->isp.isp81;
1715	1656	qla2xxx_prep_dump(ha, ha->fw_dump);
1716	1657
1717		- fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
	1658	+ fw->host_status = htonl(rd_reg_dword(&reg->host_status));
1718	1659
1719	1660	/*
1720	1661	* Pause RISC. No need to track timeout, as resetting the chip
..	..	@@ -1728,73 +1669,73 @@
1728	1669	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1729	1670
1730	1671	/* PCIe registers. */
1731		- WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1732		- RD_REG_DWORD(&reg->iobase_addr);
1733		- WRT_REG_DWORD(&reg->iobase_window, 0x01);
	1672	+ wrt_reg_dword(&reg->iobase_addr, 0x7C00);
	1673	+ rd_reg_dword(&reg->iobase_addr);
	1674	+ wrt_reg_dword(&reg->iobase_window, 0x01);
1734	1675	dmp_reg = &reg->iobase_c4;
1735		- fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg));
	1676	+ fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg));
1736	1677	dmp_reg++;
1737		- fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg));
	1678	+ fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg));
1738	1679	dmp_reg++;
1739		- fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1740		- fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
	1680	+ fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg));
	1681	+ fw->pcie_regs[3] = htonl(rd_reg_dword(&reg->iobase_window));
1741	1682
1742		- WRT_REG_DWORD(&reg->iobase_window, 0x00);
1743		- RD_REG_DWORD(&reg->iobase_window);
	1683	+ wrt_reg_dword(&reg->iobase_window, 0x00);
	1684	+ rd_reg_dword(&reg->iobase_window);
1744	1685
1745	1686	/* Host interface registers. */
1746	1687	dmp_reg = &reg->flash_addr;
1747		- for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
1748		- fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
	1688	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++)
	1689	+ fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
1749	1690
1750	1691	/* Disable interrupts. */
1751		- WRT_REG_DWORD(&reg->ictrl, 0);
1752		- RD_REG_DWORD(&reg->ictrl);
	1692	+ wrt_reg_dword(&reg->ictrl, 0);
	1693	+ rd_reg_dword(&reg->ictrl);
1753	1694
1754	1695	/* Shadow registers. */
1755		- WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1756		- RD_REG_DWORD(&reg->iobase_addr);
1757		- WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1758		- fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1696	+ wrt_reg_dword(&reg->iobase_addr, 0x0F70);
	1697	+ rd_reg_dword(&reg->iobase_addr);
	1698	+ wrt_reg_dword(&reg->iobase_select, 0xB0000000);
	1699	+ fw->shadow_reg[0] = htonl(rd_reg_dword(&reg->iobase_sdata));
1759	1700
1760		- WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1761		- fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1701	+ wrt_reg_dword(&reg->iobase_select, 0xB0100000);
	1702	+ fw->shadow_reg[1] = htonl(rd_reg_dword(&reg->iobase_sdata));
1762	1703
1763		- WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1764		- fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1704	+ wrt_reg_dword(&reg->iobase_select, 0xB0200000);
	1705	+ fw->shadow_reg[2] = htonl(rd_reg_dword(&reg->iobase_sdata));
1765	1706
1766		- WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1767		- fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1707	+ wrt_reg_dword(&reg->iobase_select, 0xB0300000);
	1708	+ fw->shadow_reg[3] = htonl(rd_reg_dword(&reg->iobase_sdata));
1768	1709
1769		- WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1770		- fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1710	+ wrt_reg_dword(&reg->iobase_select, 0xB0400000);
	1711	+ fw->shadow_reg[4] = htonl(rd_reg_dword(&reg->iobase_sdata));
1771	1712
1772		- WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1773		- fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1713	+ wrt_reg_dword(&reg->iobase_select, 0xB0500000);
	1714	+ fw->shadow_reg[5] = htonl(rd_reg_dword(&reg->iobase_sdata));
1774	1715
1775		- WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1776		- fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1716	+ wrt_reg_dword(&reg->iobase_select, 0xB0600000);
	1717	+ fw->shadow_reg[6] = htonl(rd_reg_dword(&reg->iobase_sdata));
1777	1718
1778		- WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1779		- fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1719	+ wrt_reg_dword(&reg->iobase_select, 0xB0700000);
	1720	+ fw->shadow_reg[7] = htonl(rd_reg_dword(&reg->iobase_sdata));
1780	1721
1781		- WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1782		- fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1722	+ wrt_reg_dword(&reg->iobase_select, 0xB0800000);
	1723	+ fw->shadow_reg[8] = htonl(rd_reg_dword(&reg->iobase_sdata));
1783	1724
1784		- WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1785		- fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1725	+ wrt_reg_dword(&reg->iobase_select, 0xB0900000);
	1726	+ fw->shadow_reg[9] = htonl(rd_reg_dword(&reg->iobase_sdata));
1786	1727
1787		- WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1788		- fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	1728	+ wrt_reg_dword(&reg->iobase_select, 0xB0A00000);
	1729	+ fw->shadow_reg[10] = htonl(rd_reg_dword(&reg->iobase_sdata));
1789	1730
1790	1731	/* RISC I/O register. */
1791		- WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1792		- fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
	1732	+ wrt_reg_dword(&reg->iobase_addr, 0x0010);
	1733	+ fw->risc_io_reg = htonl(rd_reg_dword(&reg->iobase_window));
1793	1734
1794	1735	/* Mailbox registers. */
1795	1736	mbx_reg = &reg->mailbox0;
1796		- for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++)
1797		- fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
	1737	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++)
	1738	+ fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg));
1798	1739
1799	1740	/* Transfer sequence registers. */
1800	1741	iter_reg = fw->xseq_gp_reg;
..	..	@@ -1858,19 +1799,19 @@
1858	1799	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1859	1800	dmp_reg = &reg->iobase_q;
1860	1801	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1861		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1802	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1862	1803
1863	1804	iter_reg = fw->resp0_dma_reg;
1864	1805	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1865	1806	dmp_reg = &reg->iobase_q;
1866	1807	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1867		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1808	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1868	1809
1869	1810	iter_reg = fw->req1_dma_reg;
1870	1811	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1871	1812	dmp_reg = &reg->iobase_q;
1872	1813	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
1873		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	1814	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
1874	1815
1875	1816	/* Transmit DMA registers. */
1876	1817	iter_reg = fw->xmt0_dma_reg;
..	..	@@ -1992,57 +1933,44 @@
1992	1933
1993	1934	qla81xx_fw_dump_failed_0:
1994	1935	qla2xxx_dump_post_process(base_vha, rval);
1995		-
1996		-qla81xx_fw_dump_failed:
1997		-#ifndef __CHECKER__
1998		- if (!hardware_locked)
1999		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
2000		-#else
2001		- ;
2002		-#endif
2003	1936	}
2004	1937
2005	1938	void
2006		-qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
	1939	+qla83xx_fw_dump(scsi_qla_host_t *vha)
2007	1940	{
2008	1941	int rval;
2009	1942	uint32_t cnt;
2010	1943	struct qla_hw_data *ha = vha->hw;
2011	1944	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2012		- uint32_t __iomem *dmp_reg;
2013		- uint32_t *iter_reg;
2014		- uint16_t __iomem *mbx_reg;
2015		- unsigned long flags;
	1945	+ __le32 __iomem *dmp_reg;
	1946	+ __be32 *iter_reg;
	1947	+ __le16 __iomem *mbx_reg;
2016	1948	struct qla83xx_fw_dump *fw;
2017	1949	void nxt, nxt_chain;
2018		- uint32_t *last_chain = NULL;
	1950	+ __be32 *last_chain = NULL;
2019	1951	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2020	1952
2021		- flags = 0;
2022		- ha->fw_dump_cap_flags = 0;
	1953	+ lockdep_assert_held(&ha->hardware_lock);
2023	1954
2024		-#ifndef __CHECKER__
2025		- if (!hardware_locked)
2026		- spin_lock_irqsave(&ha->hardware_lock, flags);
2027		-#endif
	1955	+ ha->fw_dump_cap_flags = 0;
2028	1956
2029	1957	if (!ha->fw_dump) {
2030	1958	ql_log(ql_log_warn, vha, 0xd00c,
2031	1959	"No buffer available for dump!!!\n");
2032		- goto qla83xx_fw_dump_failed;
	1960	+ return;
2033	1961	}
2034	1962
2035	1963	if (ha->fw_dumped) {
2036	1964	ql_log(ql_log_warn, vha, 0xd00d,
2037	1965	"Firmware has been previously dumped (%p) -- ignoring "
2038	1966	"request...\n", ha->fw_dump);
2039		- goto qla83xx_fw_dump_failed;
	1967	+ return;
2040	1968	}
2041	1969	QLA_FW_STOPPED(ha);
2042	1970	fw = &ha->fw_dump->isp.isp83;
2043	1971	qla2xxx_prep_dump(ha, ha->fw_dump);
2044	1972
2045		- fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
	1973	+ fw->host_status = htonl(rd_reg_dword(&reg->host_status));
2046	1974
2047	1975	/*
2048	1976	* Pause RISC. No need to track timeout, as resetting the chip
..	..	@@ -2050,24 +1978,24 @@
2050	1978	*/
2051	1979	qla24xx_pause_risc(reg, ha);
2052	1980
2053		- WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
	1981	+ wrt_reg_dword(&reg->iobase_addr, 0x6000);
2054	1982	dmp_reg = &reg->iobase_window;
2055		- RD_REG_DWORD(dmp_reg);
2056		- WRT_REG_DWORD(dmp_reg, 0);
	1983	+ rd_reg_dword(dmp_reg);
	1984	+ wrt_reg_dword(dmp_reg, 0);
2057	1985
2058	1986	dmp_reg = &reg->unused_4_1[0];
2059		- RD_REG_DWORD(dmp_reg);
2060		- WRT_REG_DWORD(dmp_reg, 0);
	1987	+ rd_reg_dword(dmp_reg);
	1988	+ wrt_reg_dword(dmp_reg, 0);
2061	1989
2062		- WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
	1990	+ wrt_reg_dword(&reg->iobase_addr, 0x6010);
2063	1991	dmp_reg = &reg->unused_4_1[2];
2064		- RD_REG_DWORD(dmp_reg);
2065		- WRT_REG_DWORD(dmp_reg, 0);
	1992	+ rd_reg_dword(dmp_reg);
	1993	+ wrt_reg_dword(dmp_reg, 0);
2066	1994
2067	1995	/* select PCR and disable ecc checking and correction */
2068		- WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
2069		- RD_REG_DWORD(&reg->iobase_addr);
2070		- WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
	1996	+ wrt_reg_dword(&reg->iobase_addr, 0x0F70);
	1997	+ rd_reg_dword(&reg->iobase_addr);
	1998	+ wrt_reg_dword(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
2071	1999
2072	2000	/* Host/Risc registers. */
2073	2001	iter_reg = fw->host_risc_reg;
..	..	@@ -2076,73 +2004,73 @@
2076	2004	qla24xx_read_window(reg, 0x7040, 16, iter_reg);
2077	2005
2078	2006	/* PCIe registers. */
2079		- WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
2080		- RD_REG_DWORD(&reg->iobase_addr);
2081		- WRT_REG_DWORD(&reg->iobase_window, 0x01);
	2007	+ wrt_reg_dword(&reg->iobase_addr, 0x7C00);
	2008	+ rd_reg_dword(&reg->iobase_addr);
	2009	+ wrt_reg_dword(&reg->iobase_window, 0x01);
2082	2010	dmp_reg = &reg->iobase_c4;
2083		- fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg));
	2011	+ fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg));
2084	2012	dmp_reg++;
2085		- fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg));
	2013	+ fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg));
2086	2014	dmp_reg++;
2087		- fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
2088		- fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
	2015	+ fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg));
	2016	+ fw->pcie_regs[3] = htonl(rd_reg_dword(&reg->iobase_window));
2089	2017
2090		- WRT_REG_DWORD(&reg->iobase_window, 0x00);
2091		- RD_REG_DWORD(&reg->iobase_window);
	2018	+ wrt_reg_dword(&reg->iobase_window, 0x00);
	2019	+ rd_reg_dword(&reg->iobase_window);
2092	2020
2093	2021	/* Host interface registers. */
2094	2022	dmp_reg = &reg->flash_addr;
2095		- for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
2096		- fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
	2023	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++)
	2024	+ fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
2097	2025
2098	2026	/* Disable interrupts. */
2099		- WRT_REG_DWORD(&reg->ictrl, 0);
2100		- RD_REG_DWORD(&reg->ictrl);
	2027	+ wrt_reg_dword(&reg->ictrl, 0);
	2028	+ rd_reg_dword(&reg->ictrl);
2101	2029
2102	2030	/* Shadow registers. */
2103		- WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
2104		- RD_REG_DWORD(&reg->iobase_addr);
2105		- WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
2106		- fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2031	+ wrt_reg_dword(&reg->iobase_addr, 0x0F70);
	2032	+ rd_reg_dword(&reg->iobase_addr);
	2033	+ wrt_reg_dword(&reg->iobase_select, 0xB0000000);
	2034	+ fw->shadow_reg[0] = htonl(rd_reg_dword(&reg->iobase_sdata));
2107	2035
2108		- WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
2109		- fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2036	+ wrt_reg_dword(&reg->iobase_select, 0xB0100000);
	2037	+ fw->shadow_reg[1] = htonl(rd_reg_dword(&reg->iobase_sdata));
2110	2038
2111		- WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
2112		- fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2039	+ wrt_reg_dword(&reg->iobase_select, 0xB0200000);
	2040	+ fw->shadow_reg[2] = htonl(rd_reg_dword(&reg->iobase_sdata));
2113	2041
2114		- WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
2115		- fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2042	+ wrt_reg_dword(&reg->iobase_select, 0xB0300000);
	2043	+ fw->shadow_reg[3] = htonl(rd_reg_dword(&reg->iobase_sdata));
2116	2044
2117		- WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
2118		- fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2045	+ wrt_reg_dword(&reg->iobase_select, 0xB0400000);
	2046	+ fw->shadow_reg[4] = htonl(rd_reg_dword(&reg->iobase_sdata));
2119	2047
2120		- WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
2121		- fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2048	+ wrt_reg_dword(&reg->iobase_select, 0xB0500000);
	2049	+ fw->shadow_reg[5] = htonl(rd_reg_dword(&reg->iobase_sdata));
2122	2050
2123		- WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
2124		- fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2051	+ wrt_reg_dword(&reg->iobase_select, 0xB0600000);
	2052	+ fw->shadow_reg[6] = htonl(rd_reg_dword(&reg->iobase_sdata));
2125	2053
2126		- WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
2127		- fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2054	+ wrt_reg_dword(&reg->iobase_select, 0xB0700000);
	2055	+ fw->shadow_reg[7] = htonl(rd_reg_dword(&reg->iobase_sdata));
2128	2056
2129		- WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
2130		- fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2057	+ wrt_reg_dword(&reg->iobase_select, 0xB0800000);
	2058	+ fw->shadow_reg[8] = htonl(rd_reg_dword(&reg->iobase_sdata));
2131	2059
2132		- WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
2133		- fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2060	+ wrt_reg_dword(&reg->iobase_select, 0xB0900000);
	2061	+ fw->shadow_reg[9] = htonl(rd_reg_dword(&reg->iobase_sdata));
2134	2062
2135		- WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
2136		- fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
	2063	+ wrt_reg_dword(&reg->iobase_select, 0xB0A00000);
	2064	+ fw->shadow_reg[10] = htonl(rd_reg_dword(&reg->iobase_sdata));
2137	2065
2138	2066	/* RISC I/O register. */
2139		- WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
2140		- fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
	2067	+ wrt_reg_dword(&reg->iobase_addr, 0x0010);
	2068	+ fw->risc_io_reg = htonl(rd_reg_dword(&reg->iobase_window));
2141	2069
2142	2070	/* Mailbox registers. */
2143	2071	mbx_reg = &reg->mailbox0;
2144		- for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++)
2145		- fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
	2072	+ for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++)
	2073	+ fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg));
2146	2074
2147	2075	/* Transfer sequence registers. */
2148	2076	iter_reg = fw->xseq_gp_reg;
..	..	@@ -2238,19 +2166,19 @@
2238	2166	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
2239	2167	dmp_reg = &reg->iobase_q;
2240	2168	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
2241		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	2169	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
2242	2170
2243	2171	iter_reg = fw->resp0_dma_reg;
2244	2172	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
2245	2173	dmp_reg = &reg->iobase_q;
2246	2174	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
2247		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	2175	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
2248	2176
2249	2177	iter_reg = fw->req1_dma_reg;
2250	2178	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
2251	2179	dmp_reg = &reg->iobase_q;
2252	2180	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
2253		- *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
	2181	+ *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
2254	2182
2255	2183	/* Transmit DMA registers. */
2256	2184	iter_reg = fw->xmt0_dma_reg;
..	..	@@ -2456,16 +2384,16 @@
2456	2384
2457	2385	ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
2458	2386
2459		- WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2460		- RD_REG_DWORD(&reg->hccr);
	2387	+ wrt_reg_dword(&reg->hccr, HCCRX_SET_RISC_RESET);
	2388	+ rd_reg_dword(&reg->hccr);
2461	2389
2462		- WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2463		- RD_REG_DWORD(&reg->hccr);
	2390	+ wrt_reg_dword(&reg->hccr, HCCRX_REL_RISC_PAUSE);
	2391	+ rd_reg_dword(&reg->hccr);
2464	2392
2465		- WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2466		- RD_REG_DWORD(&reg->hccr);
	2393	+ wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_RESET);
	2394	+ rd_reg_dword(&reg->hccr);
2467	2395
2468		- for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
	2396	+ for (cnt = 30000; cnt && (rd_reg_word(&reg->mailbox0)); cnt--)
2469	2397	udelay(5);
2470	2398
2471	2399	if (!cnt) {
..	..	@@ -2506,19 +2434,28 @@
2506	2434
2507	2435	qla83xx_fw_dump_failed_0:
2508	2436	qla2xxx_dump_post_process(base_vha, rval);
2509		-
2510		-qla83xx_fw_dump_failed:
2511		-#ifndef __CHECKER__
2512		- if (!hardware_locked)
2513		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
2514		-#else
2515		- ;
2516		-#endif
2517	2437	}
2518	2438
2519	2439	/****************************************************************************/
2520	2440	/* Driver Debug Functions. */
2521	2441	/****************************************************************************/
	2442	+
	2443	+/* Write the debug message prefix into @pbuf. */
	2444	+static void ql_dbg_prefix(char *pbuf, int pbuf_size,
	2445	+ const scsi_qla_host_t *vha, uint msg_id)
	2446	+{
	2447	+ if (vha) {
	2448	+ const struct pci_dev *pdev = vha->hw->pdev;
	2449	+
	2450	+ /* <module-name> [<dev-name>]-<msg-id>:<host>: */
	2451	+ snprintf(pbuf, pbuf_size, "%s [%s]-%04x:%lu: ", QL_MSGHDR,
	2452	+ dev_name(&(pdev->dev)), msg_id, vha->host_no);
	2453	+ } else {
	2454	+ /* <module-name> [<dev-name>]-<msg-id>: : */
	2455	+ snprintf(pbuf, pbuf_size, "%s [%s]-%04x: : ", QL_MSGHDR,
	2456	+ "0000:00:00.0", msg_id);
	2457	+ }
	2458	+}
2522	2459
2523	2460	/*
2524	2461	* This function is for formatting and logging debug information.
..	..	@@ -2534,12 +2471,13 @@
2534	2471	* msg: The message to be displayed.
2535	2472	*/
2536	2473	void
2537		-ql_dbg(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
	2474	+ql_dbg(uint level, scsi_qla_host_t vha, uint id, const char fmt, ...)
2538	2475	{
2539	2476	va_list va;
2540	2477	struct va_format vaf;
	2478	+ char pbuf[64];
2541	2479
2542		- if (!ql_mask_match(level))
	2480	+ if (!ql_mask_match(level) && !trace_ql_dbg_log_enabled())
2543	2481	return;
2544	2482
2545	2483	va_start(va, fmt);
..	..	@@ -2547,16 +2485,12 @@
2547	2485	vaf.fmt = fmt;
2548	2486	vaf.va = &va;
2549	2487
2550		- if (vha != NULL) {
2551		- const struct pci_dev *pdev = vha->hw->pdev;
2552		- /* <module-name> <pci-name> <msg-id>:<host> Message */
2553		- pr_warn("%s [%s]-%04x:%ld: %pV",
2554		- QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2555		- vha->host_no, &vaf);
2556		- } else {
2557		- pr_warn("%s [%s]-%04x: : %pV",
2558		- QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
2559		- }
	2488	+ ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), vha, id);
	2489	+
	2490	+ if (!ql_mask_match(level))
	2491	+ trace_ql_dbg_log(pbuf, &vaf);
	2492	+ else
	2493	+ pr_warn("%s%pV", pbuf, &vaf);
2560	2494
2561	2495	va_end(va);
2562	2496
..	..	@@ -2577,11 +2511,11 @@
2577	2511	* msg: The message to be displayed.
2578	2512	*/
2579	2513	void
2580		-ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2581		- const char *fmt, ...)
	2514	+ql_dbg_pci(uint level, struct pci_dev pdev, uint id, const char fmt, ...)
2582	2515	{
2583	2516	va_list va;
2584	2517	struct va_format vaf;
	2518	+ char pbuf[128];
2585	2519
2586	2520	if (pdev == NULL)
2587	2521	return;
..	..	@@ -2593,9 +2527,8 @@
2593	2527	vaf.fmt = fmt;
2594	2528	vaf.va = &va;
2595	2529
2596		- /* <module-name> <dev-name>:<msg-id> Message */
2597		- pr_warn("%s [%s]-%04x: : %pV",
2598		- QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
	2530	+ ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), NULL, id + ql_dbg_offset);
	2531	+ pr_warn("%s%pV", pbuf, &vaf);
2599	2532
2600	2533	va_end(va);
2601	2534	}
..	..	@@ -2614,7 +2547,7 @@
2614	2547	* msg: The message to be displayed.
2615	2548	*/
2616	2549	void
2617		-ql_log(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
	2550	+ql_log(uint level, scsi_qla_host_t vha, uint id, const char fmt, ...)
2618	2551	{
2619	2552	va_list va;
2620	2553	struct va_format vaf;
..	..	@@ -2623,16 +2556,7 @@
2623	2556	if (level > ql_errlev)
2624	2557	return;
2625	2558
2626		- if (vha != NULL) {
2627		- const struct pci_dev *pdev = vha->hw->pdev;
2628		- /* <module-name> <msg-id>:<host> Message */
2629		- snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
2630		- QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
2631		- } else {
2632		- snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2633		- QL_MSGHDR, "0000:00:00.0", id);
2634		- }
2635		- pbuf[sizeof(pbuf) - 1] = 0;
	2559	+ ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), vha, id);
2636	2560
2637	2561	va_start(va, fmt);
2638	2562
..	..	@@ -2672,8 +2596,7 @@
2672	2596	* msg: The message to be displayed.
2673	2597	*/
2674	2598	void
2675		-ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2676		- const char *fmt, ...)
	2599	+ql_log_pci(uint level, struct pci_dev pdev, uint id, const char fmt, ...)
2677	2600	{
2678	2601	va_list va;
2679	2602	struct va_format vaf;
..	..	@@ -2684,10 +2607,7 @@
2684	2607	if (level > ql_errlev)
2685	2608	return;
2686	2609
2687		- /* <module-name> <dev-name>:<msg-id> Message */
2688		- snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2689		- QL_MSGHDR, dev_name(&(pdev->dev)), id);
2690		- pbuf[sizeof(pbuf) - 1] = 0;
	2610	+ ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), NULL, id);
2691	2611
2692	2612	va_start(va, fmt);
2693	2613
..	..	@@ -2713,14 +2633,14 @@
2713	2633	}
2714	2634
2715	2635	void
2716		-ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
	2636	+ql_dump_regs(uint level, scsi_qla_host_t *vha, uint id)
2717	2637	{
2718	2638	int i;
2719	2639	struct qla_hw_data *ha = vha->hw;
2720	2640	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2721	2641	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
2722	2642	struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
2723		- uint16_t __iomem *mbx_reg;
	2643	+ __le16 __iomem *mbx_reg;
2724	2644
2725	2645	if (!ql_mask_match(level))
2726	2646	return;
..	..	@@ -2735,13 +2655,12 @@
2735	2655	ql_dbg(level, vha, id, "Mailbox registers:\n");
2736	2656	for (i = 0; i < 6; i++, mbx_reg++)
2737	2657	ql_dbg(level, vha, id,
2738		- "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg));
	2658	+ "mbox[%d] %#04x\n", i, rd_reg_word(mbx_reg));
2739	2659	}
2740	2660
2741		-
2742	2661	void
2743		-ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
2744		- uint8_t *buf, uint size)
	2662	+ql_dump_buffer(uint level, scsi_qla_host_t vha, uint id, const void buf,
	2663	+ uint size)
2745	2664	{
2746	2665	uint cnt;
2747	2666
..	..	@@ -2783,16 +2702,7 @@
2783	2702	if (level > ql_errlev)
2784	2703	return;
2785	2704
2786		- if (qpair != NULL) {
2787		- const struct pci_dev *pdev = qpair->pdev;
2788		- /* <module-name> <msg-id>:<host> Message */
2789		- snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: ",
2790		- QL_MSGHDR, dev_name(&(pdev->dev)), id);
2791		- } else {
2792		- snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2793		- QL_MSGHDR, "0000:00:00.0", id);
2794		- }
2795		- pbuf[sizeof(pbuf) - 1] = 0;
	2705	+ ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), qpair ? qpair->vha : NULL, id);
2796	2706
2797	2707	va_start(va, fmt);
2798	2708
..	..	@@ -2836,6 +2746,7 @@
2836	2746	{
2837	2747	va_list va;
2838	2748	struct va_format vaf;
	2749	+ char pbuf[128];
2839	2750
2840	2751	if (!ql_mask_match(level))
2841	2752	return;
..	..	@@ -2845,16 +2756,9 @@
2845	2756	vaf.fmt = fmt;
2846	2757	vaf.va = &va;
2847	2758
2848		- if (qpair != NULL) {
2849		- const struct pci_dev *pdev = qpair->pdev;
2850		- /* <module-name> <pci-name> <msg-id>:<host> Message */
2851		- pr_warn("%s [%s]-%04x: %pV",
2852		- QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2853		- &vaf);
2854		- } else {
2855		- pr_warn("%s [%s]-%04x: : %pV",
2856		- QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
2857		- }
	2759	+ ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), qpair ? qpair->vha : NULL,
	2760	+ id + ql_dbg_offset);
	2761	+ pr_warn("%s%pV", pbuf, &vaf);
2858	2762
2859	2763	va_end(va);
2860	2764