| .. | .. |
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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Linux MegaRAID driver for SAS based RAID controllers |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright (c) 2009-2013 LSI Corporation |
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| 5 | | - * Copyright (c) 2013-2014 Avago Technologies |
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| 6 | | - * |
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| 7 | | - * This program is free software; you can redistribute it and/or |
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| 8 | | - * modify it under the terms of the GNU General Public License |
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| 9 | | - * as published by the Free Software Foundation; either version 2 |
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| 10 | | - * of the License, or (at your option) any later version. |
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| 11 | | - * |
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| 12 | | - * This program is distributed in the hope that it will be useful, |
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| 13 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 15 | | - * GNU General Public License for more details. |
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| 16 | | - * |
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| 17 | | - * You should have received a copy of the GNU General Public License |
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| 18 | | - * along with this program. If not, see <http://www.gnu.org/licenses/>. |
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| 6 | + * Copyright (c) 2013-2016 Avago Technologies |
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| 7 | + * Copyright (c) 2016-2018 Broadcom Inc. |
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| 19 | 8 | * |
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| 20 | 9 | * FILE: megaraid_sas_fusion.h |
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| 21 | 10 | * |
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| 22 | | - * Authors: Avago Technologies |
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| 11 | + * Authors: Broadcom Inc. |
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| 23 | 12 | * Manoj Jose |
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| 24 | 13 | * Sumant Patro |
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| 25 | | - * Kashyap Desai <kashyap.desai@avagotech.com> |
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| 26 | | - * Sumit Saxena <sumit.saxena@avagotech.com> |
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| 14 | + * Kashyap Desai <kashyap.desai@broadcom.com> |
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| 15 | + * Sumit Saxena <sumit.saxena@broadcom.com> |
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| 27 | 16 | * |
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| 28 | | - * Send feedback to: megaraidlinux.pdl@avagotech.com |
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| 29 | | - * |
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| 30 | | - * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, |
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| 31 | | - * San Jose, California 95131 |
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| 17 | + * Send feedback to: megaraidlinux.pdl@broadcom.com |
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| 32 | 18 | */ |
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| 33 | 19 | |
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| 34 | 20 | #ifndef _MEGARAID_SAS_FUSION_H_ |
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| .. | .. |
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| 89 | 75 | MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3, |
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| 90 | 76 | MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4, |
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| 91 | 77 | MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6, |
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| 92 | | - MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7 |
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| 78 | + MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7, |
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| 79 | + MR_RAID_FLAGS_IO_SUB_TYPE_R56_DIV_OFFLOAD = 8 |
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| 93 | 80 | }; |
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| 94 | 81 | |
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| 95 | 82 | /* |
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| .. | .. |
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| 103 | 90 | #define MEGASAS_FP_CMD_LEN 16 |
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| 104 | 91 | #define MEGASAS_FUSION_IN_RESET 0 |
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| 105 | 92 | #define MEGASAS_FUSION_OCR_NOT_POSSIBLE 1 |
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| 106 | | -#define THRESHOLD_REPLY_COUNT 50 |
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| 107 | 93 | #define RAID_1_PEER_CMDS 2 |
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| 108 | 94 | #define JBOD_MAPS_COUNT 2 |
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| 109 | 95 | #define MEGASAS_REDUCE_QD_COUNT 64 |
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| .. | .. |
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| 155 | 141 | u16 timeout_value; /* 0x02 -0x03 */ |
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| 156 | 142 | u16 routing_flags; // 0x04 -0x05 routing flags |
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| 157 | 143 | u16 virtual_disk_tgt_id; /* 0x06 -0x07 */ |
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| 158 | | - u64 reg_lock_row_lba; /* 0x08 - 0x0F */ |
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| 144 | + __le64 reg_lock_row_lba; /* 0x08 - 0x0F */ |
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| 159 | 145 | u32 reg_lock_length; /* 0x10 - 0x13 */ |
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| 160 | | - union { |
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| 161 | | - u16 next_lmid; /* 0x14 - 0x15 */ |
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| 162 | | - u16 peer_smid; /* used for the raid 1/10 fp writes */ |
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| 163 | | - } smid; |
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| 146 | + union { // flow specific |
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| 147 | + u16 rmw_op_index; /* 0x14 - 0x15, R5/6 RMW: rmw operation index*/ |
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| 148 | + u16 peer_smid; /* 0x14 - 0x15, R1 Write: peer smid*/ |
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| 149 | + u16 r56_arm_map; /* 0x14 - 0x15, Unused [15], LogArm[14:10], P-Arm[9:5], Q-Arm[4:0] */ |
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| 150 | + |
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| 151 | + } flow_specific; |
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| 152 | + |
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| 164 | 153 | u8 ex_status; /* 0x16 : OUT */ |
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| 165 | 154 | u8 status; /* 0x17 status */ |
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| 166 | 155 | u8 raid_flags; /* 0x18 resvd[7:6], ioSubType[5:4], |
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| .. | .. |
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| 250 | 239 | |
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| 251 | 240 | #define RAID_CTX_SPANARM_SPAN_SHIFT (5) |
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| 252 | 241 | #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) |
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| 242 | + |
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| 243 | +/* LogArm[14:10], P-Arm[9:5], Q-Arm[4:0] */ |
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| 244 | +#define RAID_CTX_R56_Q_ARM_MASK (0x1F) |
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| 245 | +#define RAID_CTX_R56_P_ARM_SHIFT (5) |
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| 246 | +#define RAID_CTX_R56_P_ARM_MASK (0x3E0) |
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| 247 | +#define RAID_CTX_R56_LOG_ARM_SHIFT (10) |
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| 248 | +#define RAID_CTX_R56_LOG_ARM_MASK (0x7C00) |
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| 253 | 249 | |
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| 254 | 250 | /* number of bits per index in U32 TrackStream */ |
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| 255 | 251 | #define BITS_PER_INDEX_STREAM 4 |
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| .. | .. |
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| 726 | 722 | #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/ |
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| 727 | 723 | #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200 |
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| 728 | 724 | #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200 |
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| 725 | +#define MR_DCMD_CTRL_SNAPDUMP_GET_PROPERTIES 0x01200100 |
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| 726 | +#define MR_DCMD_CTRL_DEVICE_LIST_GET 0x01190600 |
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| 729 | 727 | |
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| 730 | 728 | struct MR_DEV_HANDLE_INFO { |
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| 731 | 729 | __le16 curDevHdl; |
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| .. | .. |
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| 776 | 774 | struct MR_CPU_AFFINITY_MASK { |
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| 777 | 775 | union { |
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| 778 | 776 | struct { |
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| 779 | | -#ifndef MFI_BIG_ENDIAN |
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| 777 | +#ifndef __BIG_ENDIAN_BITFIELD |
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| 780 | 778 | u8 hw_path:1; |
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| 781 | 779 | u8 cpu0:1; |
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| 782 | 780 | u8 cpu1:1; |
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| .. | .. |
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| 867 | 865 | u8 regTypeReqOnRead; |
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| 868 | 866 | __le16 seqNum; |
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| 869 | 867 | |
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| 870 | | - struct { |
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| 871 | | - u32 ldSyncRequired:1; |
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| 872 | | - u32 reserved:31; |
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| 868 | +struct { |
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| 869 | +#ifndef __BIG_ENDIAN_BITFIELD |
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| 870 | + u32 ldSyncRequired:1; |
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| 871 | + u32 regTypeReqOnReadIsValid:1; |
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| 872 | + u32 isEPD:1; |
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| 873 | + u32 enableSLDOnAllRWIOs:1; |
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| 874 | + u32 reserved:28; |
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| 875 | +#else |
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| 876 | + u32 reserved:28; |
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| 877 | + u32 enableSLDOnAllRWIOs:1; |
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| 878 | + u32 isEPD:1; |
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| 879 | + u32 regTypeReqOnReadIsValid:1; |
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| 880 | + u32 ldSyncRequired:1; |
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| 881 | +#endif |
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| 873 | 882 | } flags; |
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| 874 | 883 | |
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| 875 | 884 | u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */ |
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| .. | .. |
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| 880 | 889 | /* 0x30 - 0x33, Logical block size for the LD */ |
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| 881 | 890 | u32 logical_block_length; |
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| 882 | 891 | struct { |
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| 883 | | -#ifndef MFI_BIG_ENDIAN |
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| 892 | +#ifndef __BIG_ENDIAN_BITFIELD |
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| 884 | 893 | /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */ |
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| 885 | 894 | u32 ld_pi_exp:4; |
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| 886 | 895 | /* 0x34, LOGICAL BLOCKS PER PHYSICAL |
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| .. | .. |
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| 953 | 962 | u8 pd_after_lb; |
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| 954 | 963 | u16 r1_alt_dev_handle; /* raid 1/10 only */ |
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| 955 | 964 | bool ra_capable; |
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| 965 | + u8 data_arms; |
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| 956 | 966 | }; |
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| 957 | 967 | |
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| 958 | 968 | struct MR_LD_TARGET_SYNC { |
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| .. | .. |
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| 1063 | 1073 | #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) |
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| 1064 | 1074 | #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) |
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| 1065 | 1075 | #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) |
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| 1076 | + |
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| 1077 | +#define MEGASAS_DEFAULT_SNAP_DUMP_WAIT_TIME 15 |
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| 1078 | +#define MEGASAS_MAX_SNAP_DUMP_WAIT_TIME 60 |
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| 1066 | 1079 | |
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| 1067 | 1080 | struct megasas_register_set; |
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| 1068 | 1081 | struct megasas_instance; |
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| .. | .. |
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| 1334 | 1347 | dma_addr_t ioc_init_request_phys; |
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| 1335 | 1348 | struct MPI2_IOC_INIT_REQUEST *ioc_init_request; |
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| 1336 | 1349 | struct megasas_cmd *ioc_init_cmd; |
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| 1337 | | - |
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| 1350 | + bool pcie_bw_limitation; |
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| 1351 | + bool r56_div_offload; |
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| 1338 | 1352 | }; |
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| 1339 | 1353 | |
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| 1340 | 1354 | union desc_value { |
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| .. | .. |
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| 1351 | 1365 | RETURN_CMD = 3, |
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| 1352 | 1366 | }; |
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| 1353 | 1367 | |
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| 1368 | +struct MR_SNAPDUMP_PROPERTIES { |
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| 1369 | + u8 offload_num; |
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| 1370 | + u8 max_num_supported; |
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| 1371 | + u8 cur_num_supported; |
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| 1372 | + u8 trigger_min_num_sec_before_ocr; |
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| 1373 | + u8 reserved[12]; |
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| 1374 | +}; |
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| 1375 | + |
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| 1376 | +struct megasas_debugfs_buffer { |
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| 1377 | + void *buf; |
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| 1378 | + u32 len; |
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| 1379 | +}; |
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| 1380 | + |
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| 1354 | 1381 | void megasas_free_cmds_fusion(struct megasas_instance *instance); |
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| 1355 | 1382 | int megasas_ioc_init_fusion(struct megasas_instance *instance); |
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| 1356 | 1383 | u8 megasas_get_map_info(struct megasas_instance *instance); |
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