enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/regulator/anatop-regulator.c
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@@ -23,18 +23,10 @@
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 #define LDO_FET_FULL_ON			0x1f
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24
 
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 struct anatop_regulator {
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-	u32 control_reg;
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-	struct regmap *anatop;
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-	int vol_bit_shift;
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-	int vol_bit_width;
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 	u32 delay_reg;
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 	int delay_bit_shift;
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 	int delay_bit_width;
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-	int min_bit_val;
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-	int min_voltage;
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-	int max_voltage;
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 	struct regulator_desc rdesc;
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-	struct regulator_init_data *initdata;
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 	bool bypass;
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 	int sel;
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 };
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@@ -55,7 +47,7 @@
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 		 * to calculate how many steps LDO need to
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 		 * ramp up, and how much delay needed. (us)
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 		 */
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-		regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);
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+		regmap_read(reg->regmap, anatop_reg->delay_reg, &val);
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 		val = (val >> anatop_reg->delay_bit_shift) &
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 			((1 << anatop_reg->delay_bit_width) - 1);
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 		ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
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@@ -147,7 +139,7 @@
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 	.map_voltage = regulator_map_voltage_linear,
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 };
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-static struct regulator_ops anatop_core_rops = {
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+static const struct regulator_ops anatop_core_rops = {
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 	.enable = anatop_regmap_enable,
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 	.disable = anatop_regmap_disable,
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 	.is_enabled = anatop_regmap_is_enabled,
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@@ -170,6 +162,13 @@
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 	struct anatop_regulator *sreg;
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 	struct regulator_init_data *initdata;
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 	struct regulator_config config = { };
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+	struct regmap *regmap;
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+	u32 control_reg;
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+	u32 vol_bit_shift;
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+	u32 vol_bit_width;
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+	u32 min_bit_val;
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+	u32 min_voltage;
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+	u32 max_voltage;
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 	int ret = 0;
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 	u32 val;
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@@ -192,48 +191,41 @@
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 		return -ENOMEM;
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 	initdata->supply_regulator = "vin";
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-	sreg->initdata = initdata;
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 	anatop_np = of_get_parent(np);
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 	if (!anatop_np)
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 		return -ENODEV;
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-	sreg->anatop = syscon_node_to_regmap(anatop_np);
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+	regmap = syscon_node_to_regmap(anatop_np);
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 	of_node_put(anatop_np);
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-	if (IS_ERR(sreg->anatop))
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-		return PTR_ERR(sreg->anatop);
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+	if (IS_ERR(regmap))
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+		return PTR_ERR(regmap);
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-	ret = of_property_read_u32(np, "anatop-reg-offset",
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-				   &sreg->control_reg);
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+	ret = of_property_read_u32(np, "anatop-reg-offset", &control_reg);
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 	if (ret) {
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 		dev_err(dev, "no anatop-reg-offset property set\n");
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 		return ret;
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 	}
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-	ret = of_property_read_u32(np, "anatop-vol-bit-width",
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-				   &sreg->vol_bit_width);
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+	ret = of_property_read_u32(np, "anatop-vol-bit-width", &vol_bit_width);
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 	if (ret) {
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 		dev_err(dev, "no anatop-vol-bit-width property set\n");
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 		return ret;
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 	}
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-	ret = of_property_read_u32(np, "anatop-vol-bit-shift",
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-				   &sreg->vol_bit_shift);
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+	ret = of_property_read_u32(np, "anatop-vol-bit-shift", &vol_bit_shift);
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 	if (ret) {
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 		dev_err(dev, "no anatop-vol-bit-shift property set\n");
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 		return ret;
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 	}
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-	ret = of_property_read_u32(np, "anatop-min-bit-val",
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-				   &sreg->min_bit_val);
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+	ret = of_property_read_u32(np, "anatop-min-bit-val", &min_bit_val);
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 	if (ret) {
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 		dev_err(dev, "no anatop-min-bit-val property set\n");
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 		return ret;
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 	}
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-	ret = of_property_read_u32(np, "anatop-min-voltage",
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-				   &sreg->min_voltage);
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+	ret = of_property_read_u32(np, "anatop-min-voltage", &min_voltage);
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 	if (ret) {
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 		dev_err(dev, "no anatop-min-voltage property set\n");
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 		return ret;
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 	}
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-	ret = of_property_read_u32(np, "anatop-max-voltage",
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-				   &sreg->max_voltage);
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+	ret = of_property_read_u32(np, "anatop-max-voltage", &max_voltage);
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 	if (ret) {
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 		dev_err(dev, "no anatop-max-voltage property set\n");
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 		return ret;
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@@ -247,24 +239,23 @@
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 	of_property_read_u32(np, "anatop-delay-bit-shift",
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 			     &sreg->delay_bit_shift);
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-	rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage) / 25000 + 1
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-			    + sreg->min_bit_val;
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-	rdesc->min_uV = sreg->min_voltage;
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+	rdesc->n_voltages = (max_voltage - min_voltage) / 25000 + 1
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+			    + min_bit_val;
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+	rdesc->min_uV = min_voltage;
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 	rdesc->uV_step = 25000;
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-	rdesc->linear_min_sel = sreg->min_bit_val;
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-	rdesc->vsel_reg = sreg->control_reg;
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-	rdesc->vsel_mask = ((1 << sreg->vol_bit_width) - 1) <<
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-			   sreg->vol_bit_shift;
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+	rdesc->linear_min_sel = min_bit_val;
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+	rdesc->vsel_reg = control_reg;
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+	rdesc->vsel_mask = ((1 << vol_bit_width) - 1) << vol_bit_shift;
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 	rdesc->min_dropout_uV = 125000;
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 	config.dev = &pdev->dev;
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 	config.init_data = initdata;
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 	config.driver_data = sreg;
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 	config.of_node = pdev->dev.of_node;
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-	config.regmap = sreg->anatop;
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+	config.regmap = regmap;
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 	/* Only core regulators have the ramp up delay configuration. */
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-	if (sreg->control_reg && sreg->delay_bit_width) {
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+	if (control_reg && sreg->delay_bit_width) {
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 		rdesc->ops = &anatop_core_rops;
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 		ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
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@@ -273,7 +264,7 @@
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 			return ret;
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 		}
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-		sreg->sel = (val & rdesc->vsel_mask) >> sreg->vol_bit_shift;
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+		sreg->sel = (val & rdesc->vsel_mask) >> vol_bit_shift;
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 		if (sreg->sel == LDO_FET_FULL_ON) {
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 			sreg->sel = 0;
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 			sreg->bypass = true;
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@@ -306,7 +297,7 @@
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 			anatop_rops.disable = regulator_disable_regmap;
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 			anatop_rops.is_enabled = regulator_is_enabled_regmap;
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-			rdesc->enable_reg = sreg->control_reg;
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+			rdesc->enable_reg = control_reg;
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 			rdesc->enable_mask = BIT(enable_bit);
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 		}
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 	}
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@@ -314,9 +305,13 @@
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 	/* register regulator */
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 	rdev = devm_regulator_register(dev, rdesc, &config);
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 	if (IS_ERR(rdev)) {
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-		dev_err(dev, "failed to register %s\n",
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-			rdesc->name);
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-		return PTR_ERR(rdev);
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+		ret = PTR_ERR(rdev);
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+		if (ret == -EPROBE_DEFER)
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+			dev_dbg(dev, "failed to register %s, deferring...\n",
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+				rdesc->name);
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+		else
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+			dev_err(dev, "failed to register %s\n", rdesc->name);
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+		return ret;
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 	}
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 	platform_set_drvdata(pdev, rdev);