~hc/RK356X_SDK_RELEASE.git

..	..	@@ -20,10 +20,10 @@
20	20	#include <linux/platform_device.h>
21	21	#include <linux/io.h>
22	22	#include <linux/bitops.h>
23		-#include <linux/gpio.h>
	23	+#include <linux/gpio/driver.h>
24	24	#include <linux/of_address.h>
25		-#include <linux/of_irq.h>
26	25	#include <linux/of_device.h>
	26	+#include <linux/of_irq.h>
27	27	#include <linux/pinctrl/machine.h>
28	28	#include <linux/pinctrl/pinconf.h>
29	29	#include <linux/pinctrl/pinctrl.h>
..	..	@@ -40,7 +40,7 @@
40	40	#include "pinconf.h"
41	41	#include "pinctrl-rockchip.h"
42	42
43		-/**
	43	+/*
44	44	* Generate a bitmask for setting a value (v) with a write mask bit in hiword
45	45	* register 31:16 area.
46	46	*/
..	..	@@ -117,6 +117,25 @@
117	117	{ .drv_type = type2, .offset = -1 }, \
118	118	{ .drv_type = type3, .offset = -1 }, \
119	119	}, \
	120	+ }
	121	+
	122	+#define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \
	123	+ iom2, iom3, pull0, pull1, \
	124	+ pull2, pull3) \
	125	+ { \
	126	+ .bank_num = id, \
	127	+ .nr_pins = pins, \
	128	+ .name = label, \
	129	+ .iomux = { \
	130	+ { .type = iom0, .offset = -1 }, \
	131	+ { .type = iom1, .offset = -1 }, \
	132	+ { .type = iom2, .offset = -1 }, \
	133	+ { .type = iom3, .offset = -1 }, \
	134	+ }, \
	135	+ .pull_type[0] = pull0, \
	136	+ .pull_type[1] = pull1, \
	137	+ .pull_type[2] = pull2, \
	138	+ .pull_type[3] = pull3, \
120	139	}
121	140
122	141	#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
..	..	@@ -204,7 +223,7 @@
204	223	.route_location = FLAG, \
205	224	}
206	225
207		-#define PX30S_PIN_BANK_FLAGS(ID, PIN, LABEL, MTYPE, DTYPE) \
	226	+#define S_PIN_BANK_FLAGS(ID, PIN, LABEL, MTYPE, DTYPE) \
208	227	PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(ID, PIN, LABEL, \
209	228	MTYPE, MTYPE, MTYPE, MTYPE, \
210	229	DTYPE, DTYPE, DTYPE, DTYPE, \
..	..	@@ -218,6 +237,12 @@
218	237
219	238	#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
220	239	PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
	240	+
	241	+#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
	242	+ PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
	243	+
	244	+static struct pinctrl_dev *g_pctldev;
	245	+static DEFINE_MUTEX(iomux_lock);
221	246
222	247	static struct regmap_config rockchip_regmap_config = {
223	248	.reg_bits = 32,
..	..	@@ -309,6 +334,7 @@
309	334	{
310	335	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
311	336	const struct rockchip_pin_group *grp;
	337	+ struct device *dev = info->dev;
312	338	struct pinctrl_map *new_map;
313	339	struct device_node *parent;
314	340	int map_num = 1;
..	..	@@ -320,8 +346,7 @@
320	346	*/
321	347	grp = pinctrl_name_to_group(info, np->name);
322	348	if (!grp) {
323		- dev_err(info->dev, "unable to find group for node %pOFn\n",
324		- np);
	349	+ dev_err(dev, "unable to find group for node %pOFn\n", np);
325	350	return -EINVAL;
326	351	}
327	352
..	..	@@ -355,7 +380,7 @@
355	380	new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
356	381	}
357	382
358		- dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
	383	+ dev_dbg(dev, "maps: function %s group %s num %d\n",
359	384	(map)->data.mux.function, (map)->data.mux.group, map_num);
360	385
361	386	return 0;
..	..	@@ -510,159 +535,110 @@
510	535
511	536	static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
512	537	{
	538	+ /* gpio1b6_sel */
513	539	.num = 1,
514	540	.pin = 14,
515	541	.reg = 0x28,
516	542	.bit = 12,
517	543	.mask = 0xf
518	544	}, {
	545	+ /* gpio1b7_sel */
519	546	.num = 1,
520	547	.pin = 15,
521	548	.reg = 0x2c,
522	549	.bit = 0,
523	550	.mask = 0x3
524	551	}, {
	552	+ /* gpio1c2_sel */
525	553	.num = 1,
526	554	.pin = 18,
527	555	.reg = 0x30,
528	556	.bit = 4,
529	557	.mask = 0xf
530	558	}, {
	559	+ /* gpio1c3_sel */
531	560	.num = 1,
532	561	.pin = 19,
533	562	.reg = 0x30,
534	563	.bit = 8,
535	564	.mask = 0xf
536	565	}, {
	566	+ /* gpio1c4_sel */
537	567	.num = 1,
538	568	.pin = 20,
539	569	.reg = 0x30,
540	570	.bit = 12,
541	571	.mask = 0xf
542	572	}, {
	573	+ /* gpio1c5_sel */
543	574	.num = 1,
544	575	.pin = 21,
545	576	.reg = 0x34,
546	577	.bit = 0,
547	578	.mask = 0xf
548	579	}, {
	580	+ /* gpio1c6_sel */
549	581	.num = 1,
550	582	.pin = 22,
551	583	.reg = 0x34,
552	584	.bit = 4,
553	585	.mask = 0xf
554	586	}, {
	587	+ /* gpio1c7_sel */
555	588	.num = 1,
556	589	.pin = 23,
557	590	.reg = 0x34,
558	591	.bit = 8,
559	592	.mask = 0xf
560	593	}, {
561		- .num = 3,
562		- .pin = 12,
563		- .reg = 0x68,
564		- .bit = 8,
565		- .mask = 0xf
566		- }, {
567		- .num = 3,
568		- .pin = 13,
569		- .reg = 0x68,
570		- .bit = 12,
571		- .mask = 0xf
572		- },
573		-};
574		-
575		-static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = {
576		- {
577		- .num = 1,
578		- .pin = 14,
579		- .reg = 0x28,
580		- .bit = 12,
581		- .mask = 0xf
582		- }, {
583		- .num = 1,
584		- .pin = 15,
585		- .reg = 0x2c,
586		- .bit = 0,
587		- .mask = 0x3
588		- }, {
589		- .num = 1,
590		- .pin = 18,
591		- .reg = 0x30,
592		- .bit = 4,
593		- .mask = 0xf
594		- }, {
595		- .num = 1,
596		- .pin = 19,
597		- .reg = 0x30,
598		- .bit = 8,
599		- .mask = 0xf
600		- }, {
601		- .num = 1,
602		- .pin = 20,
603		- .reg = 0x30,
604		- .bit = 12,
605		- .mask = 0xf
606		- }, {
607		- .num = 1,
608		- .pin = 21,
609		- .reg = 0x34,
610		- .bit = 0,
611		- .mask = 0xf
612		- }, {
613		- .num = 1,
614		- .pin = 22,
615		- .reg = 0x34,
616		- .bit = 4,
617		- .mask = 0xf
618		- }, {
619		- .num = 1,
620		- .pin = 23,
621		- .reg = 0x34,
622		- .bit = 8,
623		- .mask = 0xf
624		- }, {
625		- .num = 3,
626		- .pin = 12,
627		- .reg = 0x68,
628		- .bit = 8,
629		- .mask = 0xf
630		- }, {
631		- .num = 3,
632		- .pin = 13,
633		- .reg = 0x68,
634		- .bit = 12,
635		- .mask = 0xf
636		- }, {
	594	+ /* gpio2a2_sel_plus */
637	595	.num = 2,
638	596	.pin = 2,
639	597	.reg = 0x608,
640	598	.bit = 0,
641	599	.mask = 0x7
642	600	}, {
	601	+ /* gpio2a3_sel_plus */
643	602	.num = 2,
644	603	.pin = 3,
645	604	.reg = 0x608,
646	605	.bit = 4,
647	606	.mask = 0x7
648	607	}, {
	608	+ /* gpio2c0_sel_plus */
649	609	.num = 2,
650	610	.pin = 16,
651	611	.reg = 0x610,
652	612	.bit = 8,
653	613	.mask = 0x7
654	614	}, {
	615	+ /* gpio3b2_sel_plus */
655	616	.num = 3,
656	617	.pin = 10,
657	618	.reg = 0x610,
658	619	.bit = 0,
659	620	.mask = 0x7
660	621	}, {
	622	+ /* gpio3b3_sel_plus */
661	623	.num = 3,
662	624	.pin = 11,
663	625	.reg = 0x610,
664	626	.bit = 4,
665	627	.mask = 0x7
	628	+ }, {
	629	+ /* gpio3b4_sel */
	630	+ .num = 3,
	631	+ .pin = 12,
	632	+ .reg = 0x68,
	633	+ .bit = 8,
	634	+ .mask = 0xf
	635	+ }, {
	636	+ /* gpio3b5_sel */
	637	+ .num = 3,
	638	+ .pin = 13,
	639	+ .reg = 0x68,
	640	+ .bit = 12,
	641	+ .mask = 0xf
666	642	},
667	643	};
668	644
..	..	@@ -725,17 +701,15 @@
725	701	};
726	702
727	703	static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
728		- RK_MUXROUTE_GRF(3, RK_PD1, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_SCLK_RX_M0 */
729		- RK_MUXROUTE_GRF(3, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_SCLK_TX_M0 */
730		- RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_SCLK_RX_M1 */
731		- RK_MUXROUTE_GRF(3, RK_PA4, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_SCLK_TX_M1 */
	704	+ RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
	705	+ RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
732	706
733		- RK_MUXROUTE_GRF(1, RK_PA1, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_SCLK_M0 */
734		- RK_MUXROUTE_GRF(1, RK_PD6, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_SCLK_M1 */
735		- RK_MUXROUTE_GRF(2, RK_PD1, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_SCLK_M2 */
	707	+ RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
	708	+ RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
	709	+ RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
736	710
737		- RK_MUXROUTE_GRF(1, RK_PC6, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_SCLK_M0 */
738		- RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_SCLK_M1 */
	711	+ RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
	712	+ RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
739	713
740	714	RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
741	715	RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
..	..	@@ -916,22 +890,6 @@
916	890	RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) \| BIT(0)), /* rtc_clk */
917	891	RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) \| BIT(16 + 3)), /* uart2_rxm0 */
918	892	RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) \| BIT(16 + 3) \| BIT(2)), /* uart2_rxm1 */
919		- RK_MUXROUTE_SAME(0, RK_PC7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */
920		- RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) \| BIT(4)), /* i2c3_sdam1 */
921		- RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
922		- RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
923		- RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) \| BIT(3)), /* i2s-8ch-1-sclktxm1 */
924		- RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) \| BIT(3)), /* i2s-8ch-1-sclkrxm1 */
925		- RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) \| BIT(16 + 13)), /* pdm-clkm0 */
926		- RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) \| BIT(16 + 13) \| BIT(12)), /* pdm-clkm1 */
927		- RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) \| BIT(16 + 13) \| BIT(13)), /* pdm-clkm2 */
928		- RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) \| BIT(2)), /* pdm-clkm-m2 */
929		-};
930		-
931		-static struct rockchip_mux_route_data rk3308b_mux_route_data[] = {
932		- RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) \| BIT(0)), /* rtc_clk */
933		- RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) \| BIT(16 + 3)), /* uart2_rxm0 */
934		- RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) \| BIT(16 + 3) \| BIT(2)), /* uart2_rxm1 */
935	893	RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) \| BIT(16 + 9)), /* i2c3_sdam0 */
936	894	RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) \| BIT(16 + 9) \| BIT(8)), /* i2c3_sdam1 */
937	895	RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) \| BIT(16 + 9) \| BIT(9)), /* i2c3_sdam2 */
..	..	@@ -1055,24 +1013,12 @@
1055	1013	RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1056	1014	RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1057	1015	RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1058		- RK_MUXROUTE_GRF(1, RK_PA3, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux sclk tx M0 */
1059		- RK_MUXROUTE_GRF(1, RK_PA4, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux sclk rx M0 */
1060	1016	RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1061		- RK_MUXROUTE_GRF(3, RK_PC7, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux sclk tx M1 */
1062		- RK_MUXROUTE_GRF(4, RK_PA6, 5, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux sclk rx M1 */
1063	1017	RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1064		- RK_MUXROUTE_GRF(2, RK_PD1, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux sclk tx M2 */
1065		- RK_MUXROUTE_GRF(3, RK_PC3, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux sclk rx M2 */
1066	1018	RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1067		- RK_MUXROUTE_GRF(2, RK_PC2, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux sclk tx M0 */
1068		- RK_MUXROUTE_GRF(2, RK_PB7, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux sclk rx M0 */
1069	1019	RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1070		- RK_MUXROUTE_GRF(4, RK_PB7, 4, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S1 IO mux sclk tx M1 */
1071		- RK_MUXROUTE_GRF(4, RK_PC1, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S1 IO mux sclk rx M1 */
1072	1020	RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1073		- RK_MUXROUTE_GRF(3, RK_PA3, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux sclk M0 */
1074	1021	RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1075		- RK_MUXROUTE_GRF(4, RK_PC3, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux sclk M1 */
1076	1022	RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1077	1023	RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1078	1024	RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
..	..	@@ -1117,6 +1063,7 @@
1117	1063	static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1118	1064	{
1119	1065	struct rockchip_pinctrl *info = bank->drvdata;
	1066	+ struct rockchip_pin_ctrl *ctrl = info->ctrl;
1120	1067	int iomux_num = (pin / 8);
1121	1068	struct regmap *regmap;
1122	1069	unsigned int val;
..	..	@@ -1162,6 +1109,27 @@
1162	1109	if (bank->recalced_mask & BIT(pin))
1163	1110	rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1164	1111
	1112	+ if (ctrl->type == RK3588) {
	1113	+ if (bank->bank_num == 0) {
	1114	+ if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
	1115	+ u32 reg0 = 0;
	1116	+
	1117	+ reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
	1118	+ ret = regmap_read(regmap, reg0, &val);
	1119	+ if (ret)
	1120	+ return ret;
	1121	+
	1122	+ if (((val >> bit) & mask) != 8)
	1123	+ return ((val >> bit) & mask);
	1124	+
	1125	+ reg = reg + 0x8000; /* BUS_IOC_BASE */
	1126	+ regmap = info->regmap_base;
	1127	+ }
	1128	+ } else if (bank->bank_num > 0) {
	1129	+ reg += 0x8000; /* BUS_IOC_BASE */
	1130	+ }
	1131	+ }
	1132	+
1165	1133	ret = regmap_read(regmap, reg, &val);
1166	1134	if (ret)
1167	1135	return ret;
..	..	@@ -1173,20 +1141,20 @@
1173	1141	int pin, int mux)
1174	1142	{
1175	1143	struct rockchip_pinctrl *info = bank->drvdata;
	1144	+ struct device *dev = info->dev;
1176	1145	int iomux_num = (pin / 8);
1177	1146
1178	1147	if (iomux_num > 3)
1179	1148	return -EINVAL;
1180	1149
1181	1150	if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1182		- dev_err(info->dev, "pin %d is unrouted\n", pin);
	1151	+ dev_err(dev, "pin %d is unrouted\n", pin);
1183	1152	return -EINVAL;
1184	1153	}
1185	1154
1186	1155	if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1187	1156	if (mux != RK_FUNC_GPIO) {
1188		- dev_err(info->dev,
1189		- "pin %d only supports a gpio mux\n", pin);
	1157	+ dev_err(dev, "pin %d only supports a gpio mux\n", pin);
1190	1158	return -ENOTSUPP;
1191	1159	}
1192	1160	}
..	..	@@ -1210,6 +1178,8 @@
1210	1178	static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1211	1179	{
1212	1180	struct rockchip_pinctrl *info = bank->drvdata;
	1181	+ struct rockchip_pin_ctrl *ctrl = info->ctrl;
	1182	+ struct device *dev = info->dev;
1213	1183	int iomux_num = (pin / 8);
1214	1184	struct regmap *regmap;
1215	1185	int reg, ret, mask, mux_type;
..	..	@@ -1223,8 +1193,7 @@
1223	1193	if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1224	1194	return 0;
1225	1195
1226		- dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1227		- bank->bank_num, pin, mux);
	1196	+ dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1228	1197
1229	1198	if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1230	1199	regmap = info->regmap_pmu;
..	..	@@ -1253,6 +1222,64 @@
1253	1222
1254	1223	if (bank->recalced_mask & BIT(pin))
1255	1224	rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
	1225	+
	1226	+ /* rk3562 force jtag m1 */
	1227	+ if (ctrl->type == RK3562) {
	1228	+ if (bank->bank_num == 1) {
	1229	+ if ((pin == RK_PB5) \|\| (pin == RK_PB6)) {
	1230	+ if (mux == 1) {
	1231	+ regmap_update_bits(regmap, 0x504, 0x10001, 0x10001);
	1232	+ } else {
	1233	+ regmap_update_bits(regmap, 0x504, 0x10001, 0x10000);
	1234	+ }
	1235	+ }
	1236	+ }
	1237	+ }
	1238	+
	1239	+ if (ctrl->type == RK3588) {
	1240	+ if (bank->bank_num == 0) {
	1241	+ if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
	1242	+ if (mux < 8) {
	1243	+ u32 reg0 = 0;
	1244	+
	1245	+ reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
	1246	+ data = (mask << (bit + 16));
	1247	+ rmask = data \| (data >> 16);
	1248	+ data \|= (mux & mask) << bit;
	1249	+ ret = regmap_update_bits(regmap, reg0, rmask, data);
	1250	+
	1251	+ reg0 = reg + 0x8000; /* BUS_IOC_BASE */
	1252	+ data = (mask << (bit + 16));
	1253	+ rmask = data \| (data >> 16);
	1254	+ regmap = info->regmap_base;
	1255	+ ret \|= regmap_update_bits(regmap, reg0, rmask, data);
	1256	+ } else {
	1257	+ u32 reg0 = 0;
	1258	+
	1259	+ reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
	1260	+ data = (mask << (bit + 16));
	1261	+ rmask = data \| (data >> 16);
	1262	+ data \|= 8 << bit;
	1263	+ ret = regmap_update_bits(regmap, reg0, rmask, data);
	1264	+
	1265	+ reg0 = reg + 0x8000; /* BUS_IOC_BASE */
	1266	+ data = (mask << (bit + 16));
	1267	+ rmask = data \| (data >> 16);
	1268	+ data \|= (mux & mask) << bit;
	1269	+ regmap = info->regmap_base;
	1270	+ ret \|= regmap_update_bits(regmap, reg0, rmask, data);
	1271	+ }
	1272	+ } else {
	1273	+ data = (mask << (bit + 16));
	1274	+ rmask = data \| (data >> 16);
	1275	+ data \|= (mux & mask) << bit;
	1276	+ ret = regmap_update_bits(regmap, reg, rmask, data);
	1277	+ }
	1278	+ return ret;
	1279	+ } else if (bank->bank_num > 0) {
	1280	+ reg += 0x8000; /* BUS_IOC_BASE */
	1281	+ }
	1282	+ }
1256	1283
1257	1284	if (mux > mask)
1258	1285	return -EINVAL;
..	..	@@ -1302,9 +1329,9 @@
1302	1329	#define PX30_PULL_PINS_PER_REG 8
1303	1330	#define PX30_PULL_BANK_STRIDE 16
1304	1331
1305		-static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1306		- int pin_num, struct regmap **regmap,
1307		- int reg, u8 bit)
	1332	+static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1333	+ int pin_num, struct regmap **regmap,
	1334	+ int reg, u8 bit)
1308	1335	{
1309	1336	struct rockchip_pinctrl *info = bank->drvdata;
1310	1337
..	..	@@ -1324,6 +1351,8 @@
1324	1351	reg += ((pin_num / PX30_PULL_PINS_PER_REG) 4);
1325	1352	*bit = (pin_num % PX30_PULL_PINS_PER_REG);
1326	1353	bit = PX30_PULL_BITS_PER_PIN;
	1354	+
	1355	+ return 0;
1327	1356	}
1328	1357
1329	1358	#define PX30_DRV_PMU_OFFSET 0x20
..	..	@@ -1332,9 +1361,9 @@
1332	1361	#define PX30_DRV_PINS_PER_REG 8
1333	1362	#define PX30_DRV_BANK_STRIDE 16
1334	1363
1335		-static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1336		- int pin_num, struct regmap **regmap,
1337		- int reg, u8 bit)
	1364	+static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1365	+ int pin_num, struct regmap **regmap,
	1366	+ int reg, u8 bit)
1338	1367	{
1339	1368	struct rockchip_pinctrl *info = bank->drvdata;
1340	1369
..	..	@@ -1354,6 +1383,8 @@
1354	1383	reg += ((pin_num / PX30_DRV_PINS_PER_REG) 4);
1355	1384	*bit = (pin_num % PX30_DRV_PINS_PER_REG);
1356	1385	bit = PX30_DRV_BITS_PER_PIN;
	1386	+
	1387	+ return 0;
1357	1388	}
1358	1389
1359	1390	#define PX30_SCHMITT_PMU_OFFSET 0x38
..	..	@@ -1387,15 +1418,175 @@
1387	1418	return 0;
1388	1419	}
1389	1420
	1421	+#define RV1106_DRV_BITS_PER_PIN 8
	1422	+#define RV1106_DRV_PINS_PER_REG 2
	1423	+#define RV1106_DRV_GPIO0_OFFSET 0x10
	1424	+#define RV1106_DRV_GPIO1_OFFSET 0x80
	1425	+#define RV1106_DRV_GPIO2_OFFSET 0x100C0
	1426	+#define RV1106_DRV_GPIO3_OFFSET 0x20100
	1427	+#define RV1106_DRV_GPIO4_OFFSET 0x30020
	1428	+
	1429	+static int rv1106_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1430	+ int pin_num, struct regmap **regmap,
	1431	+ int reg, u8 bit)
	1432	+{
	1433	+ struct rockchip_pinctrl *info = bank->drvdata;
	1434	+
	1435	+ /* GPIO0_IOC is located in PMU */
	1436	+ switch (bank->bank_num) {
	1437	+ case 0:
	1438	+ *regmap = info->regmap_pmu;
	1439	+ *reg = RV1106_DRV_GPIO0_OFFSET;
	1440	+ break;
	1441	+
	1442	+ case 1:
	1443	+ *regmap = info->regmap_base;
	1444	+ *reg = RV1106_DRV_GPIO1_OFFSET;
	1445	+ break;
	1446	+
	1447	+ case 2:
	1448	+ *regmap = info->regmap_base;
	1449	+ *reg = RV1106_DRV_GPIO2_OFFSET;
	1450	+ break;
	1451	+
	1452	+ case 3:
	1453	+ *regmap = info->regmap_base;
	1454	+ *reg = RV1106_DRV_GPIO3_OFFSET;
	1455	+ break;
	1456	+
	1457	+ case 4:
	1458	+ *regmap = info->regmap_base;
	1459	+ *reg = RV1106_DRV_GPIO4_OFFSET;
	1460	+ break;
	1461	+
	1462	+ default:
	1463	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	1464	+ break;
	1465	+ }
	1466	+
	1467	+ reg += ((pin_num / RV1106_DRV_PINS_PER_REG) 4);
	1468	+ *bit = pin_num % RV1106_DRV_PINS_PER_REG;
	1469	+ bit = RV1106_DRV_BITS_PER_PIN;
	1470	+
	1471	+ return 0;
	1472	+}
	1473	+
	1474	+#define RV1106_PULL_BITS_PER_PIN 2
	1475	+#define RV1106_PULL_PINS_PER_REG 8
	1476	+#define RV1106_PULL_GPIO0_OFFSET 0x38
	1477	+#define RV1106_PULL_GPIO1_OFFSET 0x1C0
	1478	+#define RV1106_PULL_GPIO2_OFFSET 0x101D0
	1479	+#define RV1106_PULL_GPIO3_OFFSET 0x201E0
	1480	+#define RV1106_PULL_GPIO4_OFFSET 0x30070
	1481	+
	1482	+static int rv1106_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1483	+ int pin_num, struct regmap **regmap,
	1484	+ int reg, u8 bit)
	1485	+{
	1486	+ struct rockchip_pinctrl *info = bank->drvdata;
	1487	+
	1488	+ /* GPIO0_IOC is located in PMU */
	1489	+ switch (bank->bank_num) {
	1490	+ case 0:
	1491	+ *regmap = info->regmap_pmu;
	1492	+ *reg = RV1106_PULL_GPIO0_OFFSET;
	1493	+ break;
	1494	+
	1495	+ case 1:
	1496	+ *regmap = info->regmap_base;
	1497	+ *reg = RV1106_PULL_GPIO1_OFFSET;
	1498	+ break;
	1499	+
	1500	+ case 2:
	1501	+ *regmap = info->regmap_base;
	1502	+ *reg = RV1106_PULL_GPIO2_OFFSET;
	1503	+ break;
	1504	+
	1505	+ case 3:
	1506	+ *regmap = info->regmap_base;
	1507	+ *reg = RV1106_PULL_GPIO3_OFFSET;
	1508	+ break;
	1509	+
	1510	+ case 4:
	1511	+ *regmap = info->regmap_base;
	1512	+ *reg = RV1106_PULL_GPIO4_OFFSET;
	1513	+ break;
	1514	+
	1515	+ default:
	1516	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	1517	+ break;
	1518	+ }
	1519	+
	1520	+ reg += ((pin_num / RV1106_PULL_PINS_PER_REG) 4);
	1521	+ *bit = pin_num % RV1106_PULL_PINS_PER_REG;
	1522	+ bit = RV1106_PULL_BITS_PER_PIN;
	1523	+
	1524	+ return 0;
	1525	+}
	1526	+
	1527	+#define RV1106_SMT_BITS_PER_PIN 1
	1528	+#define RV1106_SMT_PINS_PER_REG 8
	1529	+#define RV1106_SMT_GPIO0_OFFSET 0x40
	1530	+#define RV1106_SMT_GPIO1_OFFSET 0x280
	1531	+#define RV1106_SMT_GPIO2_OFFSET 0x10290
	1532	+#define RV1106_SMT_GPIO3_OFFSET 0x202A0
	1533	+#define RV1106_SMT_GPIO4_OFFSET 0x300A0
	1534	+
	1535	+static int rv1106_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	1536	+ int pin_num,
	1537	+ struct regmap **regmap,
	1538	+ int reg, u8 bit)
	1539	+{
	1540	+ struct rockchip_pinctrl *info = bank->drvdata;
	1541	+
	1542	+ /* GPIO0_IOC is located in PMU */
	1543	+ switch (bank->bank_num) {
	1544	+ case 0:
	1545	+ *regmap = info->regmap_pmu;
	1546	+ *reg = RV1106_SMT_GPIO0_OFFSET;
	1547	+ break;
	1548	+
	1549	+ case 1:
	1550	+ *regmap = info->regmap_base;
	1551	+ *reg = RV1106_SMT_GPIO1_OFFSET;
	1552	+ break;
	1553	+
	1554	+ case 2:
	1555	+ *regmap = info->regmap_base;
	1556	+ *reg = RV1106_SMT_GPIO2_OFFSET;
	1557	+ break;
	1558	+
	1559	+ case 3:
	1560	+ *regmap = info->regmap_base;
	1561	+ *reg = RV1106_SMT_GPIO3_OFFSET;
	1562	+ break;
	1563	+
	1564	+ case 4:
	1565	+ *regmap = info->regmap_base;
	1566	+ *reg = RV1106_SMT_GPIO4_OFFSET;
	1567	+ break;
	1568	+
	1569	+ default:
	1570	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	1571	+ break;
	1572	+ }
	1573	+
	1574	+ reg += ((pin_num / RV1106_SMT_PINS_PER_REG) 4);
	1575	+ *bit = pin_num % RV1106_SMT_PINS_PER_REG;
	1576	+ bit = RV1106_SMT_BITS_PER_PIN;
	1577	+
	1578	+ return 0;
	1579	+}
	1580	+
1390	1581	#define RV1108_PULL_PMU_OFFSET 0x10
1391	1582	#define RV1108_PULL_OFFSET 0x110
1392	1583	#define RV1108_PULL_PINS_PER_REG 8
1393	1584	#define RV1108_PULL_BITS_PER_PIN 2
1394	1585	#define RV1108_PULL_BANK_STRIDE 16
1395	1586
1396		-static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1397		- int pin_num, struct regmap **regmap,
1398		- int reg, u8 bit)
	1587	+static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1588	+ int pin_num, struct regmap **regmap,
	1589	+ int reg, u8 bit)
1399	1590	{
1400	1591	struct rockchip_pinctrl *info = bank->drvdata;
1401	1592
..	..	@@ -1414,6 +1605,8 @@
1414	1605	reg += ((pin_num / RV1108_PULL_PINS_PER_REG) 4);
1415	1606	*bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1416	1607	bit = RV1108_PULL_BITS_PER_PIN;
	1608	+
	1609	+ return 0;
1417	1610	}
1418	1611
1419	1612	#define RV1108_DRV_PMU_OFFSET 0x20
..	..	@@ -1422,9 +1615,9 @@
1422	1615	#define RV1108_DRV_PINS_PER_REG 8
1423	1616	#define RV1108_DRV_BANK_STRIDE 16
1424	1617
1425		-static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1426		- int pin_num, struct regmap **regmap,
1427		- int reg, u8 bit)
	1618	+static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1619	+ int pin_num, struct regmap **regmap,
	1620	+ int reg, u8 bit)
1428	1621	{
1429	1622	struct rockchip_pinctrl *info = bank->drvdata;
1430	1623
..	..	@@ -1444,6 +1637,8 @@
1444	1637	reg += ((pin_num / RV1108_DRV_PINS_PER_REG) 4);
1445	1638	*bit = pin_num % RV1108_DRV_PINS_PER_REG;
1446	1639	bit = RV1108_DRV_BITS_PER_PIN;
	1640	+
	1641	+ return 0;
1447	1642	}
1448	1643
1449	1644	#define RV1108_SCHMITT_PMU_OFFSET 0x30
..	..	@@ -1483,9 +1678,9 @@
1483	1678	#define RV1126_PULL_BANK_STRIDE 16
1484	1679	#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
1485	1680
1486		-static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1487		- int pin_num, struct regmap **regmap,
1488		- int reg, u8 bit)
	1681	+static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1682	+ int pin_num, struct regmap **regmap,
	1683	+ int reg, u8 bit)
1489	1684	{
1490	1685	struct rockchip_pinctrl *info = bank->drvdata;
1491	1686
..	..	@@ -1497,7 +1692,7 @@
1497	1692	reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) 4);
1498	1693	*bit = pin_num % RV1126_PULL_PINS_PER_REG;
1499	1694	bit = RV1126_PULL_BITS_PER_PIN;
1500		- return;
	1695	+ return 0;
1501	1696	}
1502	1697	*regmap = info->regmap_pmu;
1503	1698	*reg = RV1126_PULL_PMU_OFFSET;
..	..	@@ -1510,6 +1705,8 @@
1510	1705	reg += ((pin_num / RV1126_PULL_PINS_PER_REG) 4);
1511	1706	*bit = (pin_num % RV1126_PULL_PINS_PER_REG);
1512	1707	bit = RV1126_PULL_BITS_PER_PIN;
	1708	+
	1709	+ return 0;
1513	1710	}
1514	1711
1515	1712	#define RV1126_DRV_PMU_OFFSET 0x20
..	..	@@ -1518,9 +1715,9 @@
1518	1715	#define RV1126_DRV_PINS_PER_REG 4
1519	1716	#define RV1126_DRV_BANK_STRIDE 32
1520	1717
1521		-static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1522		- int pin_num, struct regmap **regmap,
1523		- int reg, u8 bit)
	1718	+static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1719	+ int pin_num, struct regmap **regmap,
	1720	+ int reg, u8 bit)
1524	1721	{
1525	1722	struct rockchip_pinctrl *info = bank->drvdata;
1526	1723
..	..	@@ -1533,7 +1730,7 @@
1533	1730	*reg -= 0x4;
1534	1731	*bit = pin_num % RV1126_DRV_PINS_PER_REG;
1535	1732	bit = RV1126_DRV_BITS_PER_PIN;
1536		- return;
	1733	+ return 0;
1537	1734	}
1538	1735	*regmap = info->regmap_pmu;
1539	1736	*reg = RV1126_DRV_PMU_OFFSET;
..	..	@@ -1546,6 +1743,8 @@
1546	1743	reg += ((pin_num / RV1126_DRV_PINS_PER_REG) 4);
1547	1744	*bit = pin_num % RV1126_DRV_PINS_PER_REG;
1548	1745	bit = RV1126_DRV_BITS_PER_PIN;
	1746	+
	1747	+ return 0;
1549	1748	}
1550	1749
1551	1750	#define RV1126_SCHMITT_PMU_OFFSET 0x60
..	..	@@ -1585,15 +1784,35 @@
1585	1784	return 0;
1586	1785	}
1587	1786
	1787	+#define RK3308_SCHMITT_PINS_PER_REG 8
	1788	+#define RK3308_SCHMITT_BANK_STRIDE 16
	1789	+#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
	1790	+
	1791	+static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	1792	+ int pin_num, struct regmap **regmap,
	1793	+ int reg, u8 bit)
	1794	+{
	1795	+ struct rockchip_pinctrl *info = bank->drvdata;
	1796	+
	1797	+ *regmap = info->regmap_base;
	1798	+ *reg = RK3308_SCHMITT_GRF_OFFSET;
	1799	+
	1800	+ reg += bank->bank_num RK3308_SCHMITT_BANK_STRIDE;
	1801	+ reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) 4);
	1802	+ *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
	1803	+
	1804	+ return 0;
	1805	+}
	1806	+
1588	1807	#define RK1808_PULL_PMU_OFFSET 0x10
1589	1808	#define RK1808_PULL_GRF_OFFSET 0x80
1590	1809	#define RK1808_PULL_PINS_PER_REG 8
1591	1810	#define RK1808_PULL_BITS_PER_PIN 2
1592	1811	#define RK1808_PULL_BANK_STRIDE 16
1593	1812
1594		-static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1595		- int pin_num, struct regmap **regmap,
1596		- int reg, u8 bit)
	1813	+static int rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1814	+ int pin_num, struct regmap **regmap,
	1815	+ int reg, u8 bit)
1597	1816	{
1598	1817	struct rockchip_pinctrl *info = bank->drvdata;
1599	1818
..	..	@@ -1609,6 +1828,8 @@
1609	1828	reg += ((pin_num / RK1808_PULL_PINS_PER_REG) 4);
1610	1829	*bit = (pin_num % RK1808_PULL_PINS_PER_REG);
1611	1830	bit = RK1808_PULL_BITS_PER_PIN;
	1831	+
	1832	+ return 0;
1612	1833	}
1613	1834
1614	1835	#define RK1808_DRV_PMU_OFFSET 0x20
..	..	@@ -1617,10 +1838,10 @@
1617	1838	#define RK1808_DRV_PINS_PER_REG 8
1618	1839	#define RK1808_DRV_BANK_STRIDE 16
1619	1840
1620		-static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1621		- int pin_num,
1622		- struct regmap **regmap,
1623		- int reg, u8 bit)
	1841	+static int rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1842	+ int pin_num,
	1843	+ struct regmap **regmap,
	1844	+ int reg, u8 bit)
1624	1845	{
1625	1846	struct rockchip_pinctrl *info = bank->drvdata;
1626	1847
..	..	@@ -1636,6 +1857,8 @@
1636	1857	reg += ((pin_num / RK1808_DRV_PINS_PER_REG) 4);
1637	1858	*bit = pin_num % RK1808_DRV_PINS_PER_REG;
1638	1859	bit = RK1808_DRV_BITS_PER_PIN;
	1860	+
	1861	+ return 0;
1639	1862	}
1640	1863
1641	1864	#define RK1808_SR_PMU_OFFSET 0x0030
..	..	@@ -1694,9 +1917,9 @@
1694	1917	#define RK2928_PULL_PINS_PER_REG 16
1695	1918	#define RK2928_PULL_BANK_STRIDE 8
1696	1919
1697		-static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1698		- int pin_num, struct regmap **regmap,
1699		- int reg, u8 bit)
	1920	+static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1921	+ int pin_num, struct regmap **regmap,
	1922	+ int reg, u8 bit)
1700	1923	{
1701	1924	struct rockchip_pinctrl *info = bank->drvdata;
1702	1925
..	..	@@ -1706,13 +1929,15 @@
1706	1929	reg += (pin_num / RK2928_PULL_PINS_PER_REG) 4;
1707	1930
1708	1931	*bit = pin_num % RK2928_PULL_PINS_PER_REG;
	1932	+
	1933	+ return 0;
1709	1934	};
1710	1935
1711	1936	#define RK3128_PULL_OFFSET 0x118
1712	1937
1713		-static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1714		- int pin_num, struct regmap **regmap,
1715		- int reg, u8 bit)
	1938	+static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1939	+ int pin_num, struct regmap **regmap,
	1940	+ int reg, u8 bit)
1716	1941	{
1717	1942	struct rockchip_pinctrl *info = bank->drvdata;
1718	1943
..	..	@@ -1722,6 +1947,8 @@
1722	1947	reg += ((pin_num / RK2928_PULL_PINS_PER_REG) 4);
1723	1948
1724	1949	*bit = pin_num % RK2928_PULL_PINS_PER_REG;
	1950	+
	1951	+ return 0;
1725	1952	}
1726	1953
1727	1954	#define RK3188_PULL_OFFSET 0x164
..	..	@@ -1730,9 +1957,9 @@
1730	1957	#define RK3188_PULL_BANK_STRIDE 16
1731	1958	#define RK3188_PULL_PMU_OFFSET 0x64
1732	1959
1733		-static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1734		- int pin_num, struct regmap **regmap,
1735		- int reg, u8 bit)
	1960	+static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1961	+ int pin_num, struct regmap **regmap,
	1962	+ int reg, u8 bit)
1736	1963	{
1737	1964	struct rockchip_pinctrl *info = bank->drvdata;
1738	1965
..	..	@@ -1762,12 +1989,14 @@
1762	1989	*bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1763	1990	bit = RK3188_PULL_BITS_PER_PIN;
1764	1991	}
	1992	+
	1993	+ return 0;
1765	1994	}
1766	1995
1767	1996	#define RK3288_PULL_OFFSET 0x140
1768		-static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1769		- int pin_num, struct regmap **regmap,
1770		- int reg, u8 bit)
	1997	+static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1998	+ int pin_num, struct regmap **regmap,
	1999	+ int reg, u8 bit)
1771	2000	{
1772	2001	struct rockchip_pinctrl *info = bank->drvdata;
1773	2002
..	..	@@ -1791,6 +2020,8 @@
1791	2020	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1792	2021	bit = RK3188_PULL_BITS_PER_PIN;
1793	2022	}
	2023	+
	2024	+ return 0;
1794	2025	}
1795	2026
1796	2027	#define RK3288_DRV_PMU_OFFSET 0x70
..	..	@@ -1799,9 +2030,9 @@
1799	2030	#define RK3288_DRV_PINS_PER_REG 8
1800	2031	#define RK3288_DRV_BANK_STRIDE 16
1801	2032
1802		-static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1803		- int pin_num, struct regmap **regmap,
1804		- int reg, u8 bit)
	2033	+static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2034	+ int pin_num, struct regmap **regmap,
	2035	+ int reg, u8 bit)
1805	2036	{
1806	2037	struct rockchip_pinctrl *info = bank->drvdata;
1807	2038
..	..	@@ -1825,13 +2056,15 @@
1825	2056	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1826	2057	bit = RK3288_DRV_BITS_PER_PIN;
1827	2058	}
	2059	+
	2060	+ return 0;
1828	2061	}
1829	2062
1830	2063	#define RK3228_PULL_OFFSET 0x100
1831	2064
1832		-static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1833		- int pin_num, struct regmap **regmap,
1834		- int reg, u8 bit)
	2065	+static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2066	+ int pin_num, struct regmap **regmap,
	2067	+ int reg, u8 bit)
1835	2068	{
1836	2069	struct rockchip_pinctrl *info = bank->drvdata;
1837	2070
..	..	@@ -1842,13 +2075,15 @@
1842	2075
1843	2076	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1844	2077	bit = RK3188_PULL_BITS_PER_PIN;
	2078	+
	2079	+ return 0;
1845	2080	}
1846	2081
1847	2082	#define RK3228_DRV_GRF_OFFSET 0x200
1848	2083
1849		-static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1850		- int pin_num, struct regmap **regmap,
1851		- int reg, u8 bit)
	2084	+static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2085	+ int pin_num, struct regmap **regmap,
	2086	+ int reg, u8 bit)
1852	2087	{
1853	2088	struct rockchip_pinctrl *info = bank->drvdata;
1854	2089
..	..	@@ -1859,13 +2094,15 @@
1859	2094
1860	2095	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1861	2096	bit = RK3288_DRV_BITS_PER_PIN;
	2097	+
	2098	+ return 0;
1862	2099	}
1863	2100
1864	2101	#define RK3308_PULL_OFFSET 0xa0
1865	2102
1866		-static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1867		- int pin_num, struct regmap **regmap,
1868		- int reg, u8 bit)
	2103	+static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2104	+ int pin_num, struct regmap **regmap,
	2105	+ int reg, u8 bit)
1869	2106	{
1870	2107	struct rockchip_pinctrl *info = bank->drvdata;
1871	2108
..	..	@@ -1876,13 +2113,15 @@
1876	2113
1877	2114	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1878	2115	bit = RK3188_PULL_BITS_PER_PIN;
	2116	+
	2117	+ return 0;
1879	2118	}
1880	2119
1881	2120	#define RK3308_DRV_GRF_OFFSET 0x100
1882	2121
1883		-static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1884		- int pin_num, struct regmap **regmap,
1885		- int reg, u8 bit)
	2122	+static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2123	+ int pin_num, struct regmap **regmap,
	2124	+ int reg, u8 bit)
1886	2125	{
1887	2126	struct rockchip_pinctrl *info = bank->drvdata;
1888	2127
..	..	@@ -1893,14 +2132,39 @@
1893	2132
1894	2133	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1895	2134	bit = RK3288_DRV_BITS_PER_PIN;
	2135	+
	2136	+ return 0;
	2137	+}
	2138	+
	2139	+#define RK3308_SLEW_RATE_GRF_OFFSET 0x150
	2140	+#define RK3308_SLEW_RATE_BANK_STRIDE 16
	2141	+#define RK3308_SLEW_RATE_PINS_PER_GRF_REG 8
	2142	+
	2143	+static int rk3308_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
	2144	+ int pin_num,
	2145	+ struct regmap **regmap,
	2146	+ int reg, u8 bit)
	2147	+{
	2148	+ struct rockchip_pinctrl *info = bank->drvdata;
	2149	+ int pins_per_reg;
	2150	+
	2151	+ *regmap = info->regmap_base;
	2152	+ *reg = RK3308_SLEW_RATE_GRF_OFFSET;
	2153	+ reg += (bank->bank_num) RK3308_SLEW_RATE_BANK_STRIDE;
	2154	+ pins_per_reg = RK3308_SLEW_RATE_PINS_PER_GRF_REG;
	2155	+
	2156	+ reg += ((pin_num / pins_per_reg) 4);
	2157	+ *bit = pin_num % pins_per_reg;
	2158	+
	2159	+ return 0;
1896	2160	}
1897	2161
1898	2162	#define RK3368_PULL_GRF_OFFSET 0x100
1899	2163	#define RK3368_PULL_PMU_OFFSET 0x10
1900	2164
1901		-static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1902		- int pin_num, struct regmap **regmap,
1903		- int reg, u8 bit)
	2165	+static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2166	+ int pin_num, struct regmap **regmap,
	2167	+ int reg, u8 bit)
1904	2168	{
1905	2169	struct rockchip_pinctrl *info = bank->drvdata;
1906	2170
..	..	@@ -1924,14 +2188,16 @@
1924	2188	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1925	2189	bit = RK3188_PULL_BITS_PER_PIN;
1926	2190	}
	2191	+
	2192	+ return 0;
1927	2193	}
1928	2194
1929	2195	#define RK3368_DRV_PMU_OFFSET 0x20
1930	2196	#define RK3368_DRV_GRF_OFFSET 0x200
1931	2197
1932		-static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1933		- int pin_num, struct regmap **regmap,
1934		- int reg, u8 bit)
	2198	+static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2199	+ int pin_num, struct regmap **regmap,
	2200	+ int reg, u8 bit)
1935	2201	{
1936	2202	struct rockchip_pinctrl *info = bank->drvdata;
1937	2203
..	..	@@ -1955,15 +2221,17 @@
1955	2221	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1956	2222	bit = RK3288_DRV_BITS_PER_PIN;
1957	2223	}
	2224	+
	2225	+ return 0;
1958	2226	}
1959	2227
1960	2228	#define RK3399_PULL_GRF_OFFSET 0xe040
1961	2229	#define RK3399_PULL_PMU_OFFSET 0x40
1962	2230	#define RK3399_DRV_3BITS_PER_PIN 3
1963	2231
1964		-static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1965		- int pin_num, struct regmap **regmap,
1966		- int reg, u8 bit)
	2232	+static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2233	+ int pin_num, struct regmap **regmap,
	2234	+ int reg, u8 bit)
1967	2235	{
1968	2236	struct rockchip_pinctrl *info = bank->drvdata;
1969	2237
..	..	@@ -1989,11 +2257,13 @@
1989	2257	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1990	2258	bit = RK3188_PULL_BITS_PER_PIN;
1991	2259	}
	2260	+
	2261	+ return 0;
1992	2262	}
1993	2263
1994		-static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1995		- int pin_num, struct regmap **regmap,
1996		- int reg, u8 bit)
	2264	+static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2265	+ int pin_num, struct regmap **regmap,
	2266	+ int reg, u8 bit)
1997	2267	{
1998	2268	struct rockchip_pinctrl *info = bank->drvdata;
1999	2269	int drv_num = (pin_num / 8);
..	..	@@ -2010,6 +2280,8 @@
2010	2280	bit = (pin_num % 8) 3;
2011	2281	else
2012	2282	bit = (pin_num % 8) 2;
	2283	+
	2284	+ return 0;
2013	2285	}
2014	2286
2015	2287	#define RK3528_DRV_BITS_PER_PIN 8
..	..	@@ -2020,9 +2292,9 @@
2020	2292	#define RK3528_DRV_GPIO3_OFFSET 0x20190
2021	2293	#define RK3528_DRV_GPIO4_OFFSET 0x101C0
2022	2294
2023		-static void rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2024		- int pin_num, struct regmap **regmap,
2025		- int reg, u8 bit)
	2295	+static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2296	+ int pin_num, struct regmap **regmap,
	2297	+ int reg, u8 bit)
2026	2298	{
2027	2299	struct rockchip_pinctrl *info = bank->drvdata;
2028	2300
..	..	@@ -2056,6 +2328,8 @@
2056	2328	reg += ((pin_num / RK3528_DRV_PINS_PER_REG) 4);
2057	2329	*bit = pin_num % RK3528_DRV_PINS_PER_REG;
2058	2330	bit = RK3528_DRV_BITS_PER_PIN;
	2331	+
	2332	+ return 0;
2059	2333	}
2060	2334
2061	2335	#define RK3528_PULL_BITS_PER_PIN 2
..	..	@@ -2066,9 +2340,9 @@
2066	2340	#define RK3528_PULL_GPIO3_OFFSET 0x20230
2067	2341	#define RK3528_PULL_GPIO4_OFFSET 0x10240
2068	2342
2069		-static void rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2070		- int pin_num, struct regmap **regmap,
2071		- int reg, u8 bit)
	2343	+static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2344	+ int pin_num, struct regmap **regmap,
	2345	+ int reg, u8 bit)
2072	2346	{
2073	2347	struct rockchip_pinctrl *info = bank->drvdata;
2074	2348
..	..	@@ -2102,6 +2376,8 @@
2102	2376	reg += ((pin_num / RK3528_PULL_PINS_PER_REG) 4);
2103	2377	*bit = pin_num % RK3528_PULL_PINS_PER_REG;
2104	2378	bit = RK3528_PULL_BITS_PER_PIN;
	2379	+
	2380	+ return 0;
2105	2381	}
2106	2382
2107	2383	#define RK3528_SMT_BITS_PER_PIN 1
..	..	@@ -2152,6 +2428,151 @@
2152	2428	return 0;
2153	2429	}
2154	2430
	2431	+#define RK3562_DRV_BITS_PER_PIN 8
	2432	+#define RK3562_DRV_PINS_PER_REG 2
	2433	+#define RK3562_DRV_GPIO0_OFFSET 0x20070
	2434	+#define RK3562_DRV_GPIO1_OFFSET 0x200
	2435	+#define RK3562_DRV_GPIO2_OFFSET 0x240
	2436	+#define RK3562_DRV_GPIO3_OFFSET 0x10280
	2437	+#define RK3562_DRV_GPIO4_OFFSET 0x102C0
	2438	+
	2439	+static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2440	+ int pin_num, struct regmap **regmap,
	2441	+ int reg, u8 bit)
	2442	+{
	2443	+ struct rockchip_pinctrl *info = bank->drvdata;
	2444	+
	2445	+ *regmap = info->regmap_base;
	2446	+ switch (bank->bank_num) {
	2447	+ case 0:
	2448	+ *reg = RK3562_DRV_GPIO0_OFFSET;
	2449	+ break;
	2450	+
	2451	+ case 1:
	2452	+ *reg = RK3562_DRV_GPIO1_OFFSET;
	2453	+ break;
	2454	+
	2455	+ case 2:
	2456	+ *reg = RK3562_DRV_GPIO2_OFFSET;
	2457	+ break;
	2458	+
	2459	+ case 3:
	2460	+ *reg = RK3562_DRV_GPIO3_OFFSET;
	2461	+ break;
	2462	+
	2463	+ case 4:
	2464	+ *reg = RK3562_DRV_GPIO4_OFFSET;
	2465	+ break;
	2466	+
	2467	+ default:
	2468	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	2469	+ break;
	2470	+ }
	2471	+
	2472	+ reg += ((pin_num / RK3562_DRV_PINS_PER_REG) 4);
	2473	+ *bit = pin_num % RK3562_DRV_PINS_PER_REG;
	2474	+ bit = RK3562_DRV_BITS_PER_PIN;
	2475	+
	2476	+ return 0;
	2477	+}
	2478	+
	2479	+#define RK3562_PULL_BITS_PER_PIN 2
	2480	+#define RK3562_PULL_PINS_PER_REG 8
	2481	+#define RK3562_PULL_GPIO0_OFFSET 0x20020
	2482	+#define RK3562_PULL_GPIO1_OFFSET 0x80
	2483	+#define RK3562_PULL_GPIO2_OFFSET 0x90
	2484	+#define RK3562_PULL_GPIO3_OFFSET 0x100A0
	2485	+#define RK3562_PULL_GPIO4_OFFSET 0x100B0
	2486	+
	2487	+static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2488	+ int pin_num, struct regmap **regmap,
	2489	+ int reg, u8 bit)
	2490	+{
	2491	+ struct rockchip_pinctrl *info = bank->drvdata;
	2492	+
	2493	+ *regmap = info->regmap_base;
	2494	+ switch (bank->bank_num) {
	2495	+ case 0:
	2496	+ *reg = RK3562_PULL_GPIO0_OFFSET;
	2497	+ break;
	2498	+
	2499	+ case 1:
	2500	+ *reg = RK3562_PULL_GPIO1_OFFSET;
	2501	+ break;
	2502	+
	2503	+ case 2:
	2504	+ *reg = RK3562_PULL_GPIO2_OFFSET;
	2505	+ break;
	2506	+
	2507	+ case 3:
	2508	+ *reg = RK3562_PULL_GPIO3_OFFSET;
	2509	+ break;
	2510	+
	2511	+ case 4:
	2512	+ *reg = RK3562_PULL_GPIO4_OFFSET;
	2513	+ break;
	2514	+
	2515	+ default:
	2516	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	2517	+ break;
	2518	+ }
	2519	+
	2520	+ reg += ((pin_num / RK3562_PULL_PINS_PER_REG) 4);
	2521	+ *bit = pin_num % RK3562_PULL_PINS_PER_REG;
	2522	+ bit = RK3562_PULL_BITS_PER_PIN;
	2523	+
	2524	+ return 0;
	2525	+}
	2526	+
	2527	+#define RK3562_SMT_BITS_PER_PIN 2
	2528	+#define RK3562_SMT_PINS_PER_REG 8
	2529	+#define RK3562_SMT_GPIO0_OFFSET 0x20030
	2530	+#define RK3562_SMT_GPIO1_OFFSET 0xC0
	2531	+#define RK3562_SMT_GPIO2_OFFSET 0xD0
	2532	+#define RK3562_SMT_GPIO3_OFFSET 0x100E0
	2533	+#define RK3562_SMT_GPIO4_OFFSET 0x100F0
	2534	+
	2535	+static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	2536	+ int pin_num,
	2537	+ struct regmap **regmap,
	2538	+ int reg, u8 bit)
	2539	+{
	2540	+ struct rockchip_pinctrl *info = bank->drvdata;
	2541	+
	2542	+ *regmap = info->regmap_base;
	2543	+ switch (bank->bank_num) {
	2544	+ case 0:
	2545	+ *reg = RK3562_SMT_GPIO0_OFFSET;
	2546	+ break;
	2547	+
	2548	+ case 1:
	2549	+ *reg = RK3562_SMT_GPIO1_OFFSET;
	2550	+ break;
	2551	+
	2552	+ case 2:
	2553	+ *reg = RK3562_SMT_GPIO2_OFFSET;
	2554	+ break;
	2555	+
	2556	+ case 3:
	2557	+ *reg = RK3562_SMT_GPIO3_OFFSET;
	2558	+ break;
	2559	+
	2560	+ case 4:
	2561	+ *reg = RK3562_SMT_GPIO4_OFFSET;
	2562	+ break;
	2563	+
	2564	+ default:
	2565	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	2566	+ break;
	2567	+ }
	2568	+
	2569	+ reg += ((pin_num / RK3562_SMT_PINS_PER_REG) 4);
	2570	+ *bit = pin_num % RK3562_SMT_PINS_PER_REG;
	2571	+ bit = RK3562_SMT_BITS_PER_PIN;
	2572	+
	2573	+ return 0;
	2574	+}
	2575	+
2155	2576	#define RK3568_SR_PMU_OFFSET 0x60
2156	2577	#define RK3568_SR_GRF_OFFSET 0x0180
2157	2578	#define RK3568_SR_BANK_STRIDE 0x10
..	..	@@ -2186,9 +2607,9 @@
2186	2607	#define RK3568_PULL_PINS_PER_REG 8
2187	2608	#define RK3568_PULL_BANK_STRIDE 0x10
2188	2609
2189		-static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2190		- int pin_num, struct regmap **regmap,
2191		- int reg, u8 bit)
	2610	+static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2611	+ int pin_num, struct regmap **regmap,
	2612	+ int reg, u8 bit)
2192	2613	{
2193	2614	struct rockchip_pinctrl *info = bank->drvdata;
2194	2615
..	..	@@ -2209,6 +2630,8 @@
2209	2630	*bit = (pin_num % RK3568_PULL_PINS_PER_REG);
2210	2631	bit = RK3568_PULL_BITS_PER_PIN;
2211	2632	}
	2633	+
	2634	+ return 0;
2212	2635	}
2213	2636
2214	2637	#define RK3568_DRV_PMU_OFFSET 0x70
..	..	@@ -2217,9 +2640,9 @@
2217	2640	#define RK3568_DRV_PINS_PER_REG 2
2218	2641	#define RK3568_DRV_BANK_STRIDE 0x40
2219	2642
2220		-static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2221		- int pin_num, struct regmap **regmap,
2222		- int reg, u8 bit)
	2643	+static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2644	+ int pin_num, struct regmap **regmap,
	2645	+ int reg, u8 bit)
2223	2646	{
2224	2647	struct rockchip_pinctrl *info = bank->drvdata;
2225	2648
..	..	@@ -2246,6 +2669,197 @@
2246	2669	((bank->bank_num == 2 \|\| bank->bank_num == 3 \|\| bank->bank_num == 4) &&
2247	2670	(pin_num == 7 \|\| pin_num == 15 \|\| pin_num == 23 \|\| pin_num == 31)))
2248	2671	*bit -= RK3568_DRV_BITS_PER_PIN;
	2672	+
	2673	+ return 0;
	2674	+}
	2675	+
	2676	+#define RK3588_PMU1_IOC_REG (0x0000)
	2677	+#define RK3588_PMU2_IOC_REG (0x4000)
	2678	+#define RK3588_BUS_IOC_REG (0x8000)
	2679	+#define RK3588_VCCIO1_4_IOC_REG (0x9000)
	2680	+#define RK3588_VCCIO3_5_IOC_REG (0xA000)
	2681	+#define RK3588_VCCIO2_IOC_REG (0xB000)
	2682	+#define RK3588_VCCIO6_IOC_REG (0xC000)
	2683	+#define RK3588_EMMC_IOC_REG (0xD000)
	2684	+
	2685	+static const u32 rk3588_ds_regs[][2] = {
	2686	+ {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
	2687	+ {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
	2688	+ {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
	2689	+ {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
	2690	+ {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
	2691	+ {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
	2692	+ {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
	2693	+ {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
	2694	+ {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
	2695	+ {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
	2696	+ {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
	2697	+ {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
	2698	+ {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
	2699	+ {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
	2700	+ {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
	2701	+ {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
	2702	+ {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
	2703	+ {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
	2704	+ {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
	2705	+ {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
	2706	+ {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
	2707	+ {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
	2708	+ {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
	2709	+ {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
	2710	+ {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
	2711	+ {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
	2712	+ {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
	2713	+ {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
	2714	+ {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
	2715	+ {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
	2716	+ {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
	2717	+ {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
	2718	+ {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
	2719	+ {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
	2720	+ {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
	2721	+ {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
	2722	+ {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
	2723	+ {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
	2724	+ {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
	2725	+ {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
	2726	+};
	2727	+
	2728	+static const u32 rk3588_p_regs[][2] = {
	2729	+ {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
	2730	+ {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
	2731	+ {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
	2732	+ {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
	2733	+ {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
	2734	+ {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
	2735	+ {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
	2736	+ {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
	2737	+ {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
	2738	+ {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
	2739	+ {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0120},
	2740	+ {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
	2741	+ {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
	2742	+ {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
	2743	+ {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
	2744	+ {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
	2745	+ {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
	2746	+ {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
	2747	+ {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
	2748	+ {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
	2749	+ {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
	2750	+ {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
	2751	+ {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
	2752	+};
	2753	+
	2754	+static const u32 rk3588_smt_regs[][2] = {
	2755	+ {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
	2756	+ {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
	2757	+ {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
	2758	+ {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
	2759	+ {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
	2760	+ {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
	2761	+ {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
	2762	+ {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
	2763	+ {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
	2764	+ {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
	2765	+ {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0220},
	2766	+ {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
	2767	+ {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
	2768	+ {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
	2769	+ {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
	2770	+ {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
	2771	+ {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
	2772	+ {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
	2773	+ {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
	2774	+ {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
	2775	+ {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
	2776	+ {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
	2777	+ {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
	2778	+};
	2779	+
	2780	+#define RK3588_PULL_BITS_PER_PIN 2
	2781	+#define RK3588_PULL_PINS_PER_REG 8
	2782	+
	2783	+static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2784	+ int pin_num, struct regmap **regmap,
	2785	+ int reg, u8 bit)
	2786	+{
	2787	+ struct rockchip_pinctrl *info = bank->drvdata;
	2788	+ u8 bank_num = bank->bank_num;
	2789	+ u32 pin = bank_num * 32 + pin_num;
	2790	+ int i;
	2791	+
	2792	+ for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
	2793	+ if (pin >= rk3588_p_regs[i][0]) {
	2794	+ *reg = rk3588_p_regs[i][1];
	2795	+ break;
	2796	+ }
	2797	+ BUG_ON(i == 0);
	2798	+ }
	2799	+
	2800	+ *regmap = info->regmap_base;
	2801	+ reg += ((pin - rk3588_p_regs[i][0]) / RK3588_PULL_PINS_PER_REG) 4;
	2802	+ *bit = pin_num % RK3588_PULL_PINS_PER_REG;
	2803	+ bit = RK3588_PULL_BITS_PER_PIN;
	2804	+
	2805	+ return 0;
	2806	+}
	2807	+
	2808	+#define RK3588_DRV_BITS_PER_PIN 4
	2809	+#define RK3588_DRV_PINS_PER_REG 4
	2810	+
	2811	+static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2812	+ int pin_num, struct regmap **regmap,
	2813	+ int reg, u8 bit)
	2814	+{
	2815	+ struct rockchip_pinctrl *info = bank->drvdata;
	2816	+ u8 bank_num = bank->bank_num;
	2817	+ u32 pin = bank_num * 32 + pin_num;
	2818	+ int i;
	2819	+
	2820	+ for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
	2821	+ if (pin >= rk3588_ds_regs[i][0]) {
	2822	+ *reg = rk3588_ds_regs[i][1];
	2823	+ break;
	2824	+ }
	2825	+ BUG_ON(i == 0);
	2826	+ }
	2827	+
	2828	+ *regmap = info->regmap_base;
	2829	+ reg += ((pin - rk3588_ds_regs[i][0]) / RK3588_DRV_PINS_PER_REG) 4;
	2830	+ *bit = pin_num % RK3588_DRV_PINS_PER_REG;
	2831	+ bit = RK3588_DRV_BITS_PER_PIN;
	2832	+
	2833	+ return 0;
	2834	+}
	2835	+
	2836	+#define RK3588_SMT_BITS_PER_PIN 1
	2837	+#define RK3588_SMT_PINS_PER_REG 8
	2838	+
	2839	+static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	2840	+ int pin_num,
	2841	+ struct regmap **regmap,
	2842	+ int reg, u8 bit)
	2843	+{
	2844	+ struct rockchip_pinctrl *info = bank->drvdata;
	2845	+ u8 bank_num = bank->bank_num;
	2846	+ u32 pin = bank_num * 32 + pin_num;
	2847	+ int i;
	2848	+
	2849	+ for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
	2850	+ if (pin >= rk3588_smt_regs[i][0]) {
	2851	+ *reg = rk3588_smt_regs[i][1];
	2852	+ break;
	2853	+ }
	2854	+ BUG_ON(i == 0);
	2855	+ }
	2856	+
	2857	+ *regmap = info->regmap_base;
	2858	+ reg += ((pin - rk3588_smt_regs[i][0]) / RK3588_SMT_PINS_PER_REG) 4;
	2859	+ *bit = pin_num % RK3588_SMT_PINS_PER_REG;
	2860	+ bit = RK3588_SMT_BITS_PER_PIN;
	2861	+
	2862	+ return 0;
2249	2863	}
2250	2864
2251	2865	static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
..	..	@@ -2262,13 +2876,16 @@
2262	2876	{
2263	2877	struct rockchip_pinctrl *info = bank->drvdata;
2264	2878	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	2879	+ struct device *dev = info->dev;
2265	2880	struct regmap *regmap;
2266	2881	int reg, ret;
2267	2882	u32 data, temp, rmask_bits;
2268	2883	u8 bit;
2269	2884	int drv_type = bank->drv[pin_num / 8].drv_type;
2270	2885
2271		- ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	2886	+ ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	2887	+ if (ret)
	2888	+ return ret;
2272	2889
2273	2890	switch (drv_type) {
2274	2891	case DRV_TYPE_IO_1V8_3V0_AUTO:
..	..	@@ -2307,7 +2924,7 @@
2307	2924	bit -= 16;
2308	2925	break;
2309	2926	default:
2310		- dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
	2927	+ dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2311	2928	bit, drv_type);
2312	2929	return -EINVAL;
2313	2930	}
..	..	@@ -2320,8 +2937,7 @@
2320	2937	rmask_bits = RK3288_DRV_BITS_PER_PIN;
2321	2938	break;
2322	2939	default:
2323		- dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2324		- drv_type);
	2940	+ dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2325	2941	return -EINVAL;
2326	2942	}
2327	2943
..	..	@@ -2354,21 +2970,28 @@
2354	2970	{
2355	2971	struct rockchip_pinctrl *info = bank->drvdata;
2356	2972	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	2973	+ struct device *dev = info->dev;
2357	2974	struct regmap *regmap;
2358	2975	int reg, ret, i, err;
2359	2976	u32 data, rmask, rmask_bits, temp;
2360	2977	u8 bit;
2361	2978	int drv_type = bank->drv[pin_num / 8].drv_type;
2362	2979
2363		- dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
	2980	+ dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
2364	2981	bank->bank_num, pin_num, strength);
2365	2982
2366		- ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2367		- if (ctrl->type == RV1126) {
	2983	+ ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	2984	+ if (ret)
	2985	+ return ret;
	2986	+
	2987	+ if (ctrl->type == RV1126 \|\| ctrl->type == RK3588) {
2368	2988	rmask_bits = RV1126_DRV_BITS_PER_PIN;
2369	2989	ret = strength;
2370	2990	goto config;
2371		- } else if (ctrl->type == RK3568 \|\| ctrl->type == RK3528) {
	2991	+ } else if (ctrl->type == RV1106 \|\|
	2992	+ ctrl->type == RK3528 \|\|
	2993	+ ctrl->type == RK3562 \|\|
	2994	+ ctrl->type == RK3568) {
2372	2995	rmask_bits = RK3568_DRV_BITS_PER_PIN;
2373	2996	ret = (1 << (strength + 1)) - 1;
2374	2997	goto config;
..	..	@@ -2386,8 +3009,7 @@
2386	3009	}
2387	3010
2388	3011	if (ret < 0) {
2389		- dev_err(info->dev, "unsupported driver strength %d\n",
2390		- strength);
	3012	+ dev_err(dev, "unsupported driver strength %d\n", strength);
2391	3013	return ret;
2392	3014	}
2393	3015
..	..	@@ -2426,7 +3048,7 @@
2426	3048	bit -= 16;
2427	3049	break;
2428	3050	default:
2429		- dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
	3051	+ dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2430	3052	bit, drv_type);
2431	3053	return -EINVAL;
2432	3054	}
..	..	@@ -2438,8 +3060,7 @@
2438	3060	rmask_bits = RK3288_DRV_BITS_PER_PIN;
2439	3061	break;
2440	3062	default:
2441		- dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2442		- drv_type);
	3063	+ dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2443	3064	return -EINVAL;
2444	3065	}
2445	3066
..	..	@@ -2508,6 +3129,7 @@
2508	3129	{
2509	3130	struct rockchip_pinctrl *info = bank->drvdata;
2510	3131	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	3132	+ struct device *dev = info->dev;
2511	3133	struct regmap *regmap;
2512	3134	int reg, ret, pull_type;
2513	3135	u8 bit;
..	..	@@ -2517,7 +3139,9 @@
2517	3139	if (ctrl->type == RK3066B)
2518	3140	return PIN_CONFIG_BIAS_DISABLE;
2519	3141
2520		- ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3142	+ ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3143	+ if (ret)
	3144	+ return ret;
2521	3145
2522	3146	ret = regmap_read(regmap, reg, &data);
2523	3147	if (ret)
..	..	@@ -2530,6 +3154,7 @@
2530	3154	? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
2531	3155	: PIN_CONFIG_BIAS_DISABLE;
2532	3156	case PX30:
	3157	+ case RV1106:
2533	3158	case RV1108:
2534	3159	case RV1126:
2535	3160	case RK1808:
..	..	@@ -2539,14 +3164,16 @@
2539	3164	case RK3368:
2540	3165	case RK3399:
2541	3166	case RK3528:
	3167	+ case RK3562:
2542	3168	case RK3568:
	3169	+ case RK3588:
2543	3170	pull_type = bank->pull_type[pin_num / 8];
2544	3171	data >>= bit;
2545	3172	data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2546	3173
2547	3174	return rockchip_pull_list[pull_type][data];
2548	3175	default:
2549		- dev_err(info->dev, "unsupported pinctrl type\n");
	3176	+ dev_err(dev, "unsupported pinctrl type\n");
2550	3177	return -EINVAL;
2551	3178	};
2552	3179	}
..	..	@@ -2556,19 +3183,21 @@
2556	3183	{
2557	3184	struct rockchip_pinctrl *info = bank->drvdata;
2558	3185	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	3186	+ struct device *dev = info->dev;
2559	3187	struct regmap *regmap;
2560	3188	int reg, ret, i, pull_type;
2561	3189	u8 bit;
2562	3190	u32 data, rmask;
2563	3191
2564		- dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2565		- bank->bank_num, pin_num, pull);
	3192	+ dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
2566	3193
2567	3194	/* rk3066b does support any pulls */
2568	3195	if (ctrl->type == RK3066B)
2569	3196	return pull ? -EINVAL : 0;
2570	3197
2571		- ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3198	+ ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3199	+ if (ret)
	3200	+ return ret;
2572	3201
2573	3202	switch (ctrl->type) {
2574	3203	case RK2928:
..	..	@@ -2579,6 +3208,7 @@
2579	3208	ret = regmap_write(regmap, reg, data);
2580	3209	break;
2581	3210	case PX30:
	3211	+ case RV1106:
2582	3212	case RV1108:
2583	3213	case RV1126:
2584	3214	case RK1808:
..	..	@@ -2588,7 +3218,9 @@
2588	3218	case RK3368:
2589	3219	case RK3399:
2590	3220	case RK3528:
	3221	+ case RK3562:
2591	3222	case RK3568:
	3223	+ case RK3588:
2592	3224	pull_type = bank->pull_type[pin_num / 8];
2593	3225	ret = -EINVAL;
2594	3226	for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
..	..	@@ -2599,7 +3231,7 @@
2599	3231	}
2600	3232	}
2601	3233	/*
2602		- * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6,
	3234	+ * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2603	3235	* where that pull up value becomes 3.
2604	3236	*/
2605	3237	if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
..	..	@@ -2608,8 +3240,7 @@
2608	3240	}
2609	3241
2610	3242	if (ret < 0) {
2611		- dev_err(info->dev, "unsupported pull setting %d\n",
2612		- pull);
	3243	+ dev_err(dev, "unsupported pull setting %d\n", pull);
2613	3244	return ret;
2614	3245	}
2615	3246
..	..	@@ -2621,32 +3252,11 @@
2621	3252	ret = regmap_update_bits(regmap, reg, rmask, data);
2622	3253	break;
2623	3254	default:
2624		- dev_err(info->dev, "unsupported pinctrl type\n");
	3255	+ dev_err(dev, "unsupported pinctrl type\n");
2625	3256	return -EINVAL;
2626	3257	}
2627	3258
2628	3259	return ret;
2629		-}
2630		-
2631		-#define RK3308_SCHMITT_PINS_PER_REG 8
2632		-#define RK3308_SCHMITT_BANK_STRIDE 16
2633		-#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
2634		-
2635		-static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2636		- int pin_num,
2637		- struct regmap **regmap,
2638		- int reg, u8 bit)
2639		-{
2640		- struct rockchip_pinctrl *info = bank->drvdata;
2641		-
2642		- *regmap = info->regmap_base;
2643		- *reg = RK3308_SCHMITT_GRF_OFFSET;
2644		-
2645		- reg += bank->bank_num RK3308_SCHMITT_BANK_STRIDE;
2646		- reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) 4);
2647		- *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
2648		-
2649		- return 0;
2650	3260	}
2651	3261
2652	3262	#define RK3328_SCHMITT_BITS_PER_PIN 1
..	..	@@ -2719,6 +3329,7 @@
2719	3329
2720	3330	data >>= bit;
2721	3331	switch (ctrl->type) {
	3332	+ case RK3562:
2722	3333	case RK3568:
2723	3334	return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
2724	3335	default:
..	..	@@ -2733,12 +3344,13 @@
2733	3344	{
2734	3345	struct rockchip_pinctrl *info = bank->drvdata;
2735	3346	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	3347	+ struct device *dev = info->dev;
2736	3348	struct regmap *regmap;
2737	3349	int reg, ret;
2738	3350	u8 bit;
2739	3351	u32 data, rmask;
2740	3352
2741		- dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
	3353	+ dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
2742	3354	bank->bank_num, pin_num, enable);
2743	3355
2744	3356	ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
..	..	@@ -2747,6 +3359,7 @@
2747	3359
2748	3360	/* enable the write to the equivalent lower bits */
2749	3361	switch (ctrl->type) {
	3362	+ case RK3562:
2750	3363	case RK3568:
2751	3364	data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
2752	3365	rmask = data \| (data >> 16);
..	..	@@ -2881,10 +3494,11 @@
2881	3494	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2882	3495	const unsigned int *pins = info->groups[group].pins;
2883	3496	const struct rockchip_pin_config *data = info->groups[group].data;
	3497	+ struct device *dev = info->dev;
2884	3498	struct rockchip_pin_bank *bank;
2885	3499	int cnt, ret = 0;
2886	3500
2887		- dev_dbg(info->dev, "enable function %s group %s\n",
	3501	+ dev_dbg(dev, "enable function %s group %s\n",
2888	3502	info->functions[selector].name, info->groups[group].name);
2889	3503
2890	3504	/*
..	..	@@ -2932,6 +3546,7 @@
2932	3546	case RK3066B:
2933	3547	return pull ? false : true;
2934	3548	case PX30:
	3549	+ case RV1106:
2935	3550	case RV1108:
2936	3551	case RV1126:
2937	3552	case RK1808:
..	..	@@ -2941,11 +3556,31 @@
2941	3556	case RK3368:
2942	3557	case RK3399:
2943	3558	case RK3528:
	3559	+ case RK3562:
2944	3560	case RK3568:
	3561	+ case RK3588:
2945	3562	return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2946	3563	}
2947	3564
2948	3565	return false;
	3566	+}
	3567	+
	3568	+static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
	3569	+ unsigned int pin, u32 param, u32 arg)
	3570	+{
	3571	+ struct rockchip_pin_deferred *cfg;
	3572	+
	3573	+ cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
	3574	+ if (!cfg)
	3575	+ return -ENOMEM;
	3576	+
	3577	+ cfg->pin = pin;
	3578	+ cfg->param = param;
	3579	+ cfg->arg = arg;
	3580	+
	3581	+ list_add_tail(&cfg->head, &bank->deferred_pins);
	3582	+
	3583	+ return 0;
2949	3584	}
2950	3585
2951	3586	/* set the pin config settings for a specified pin */
..	..	@@ -2963,6 +3598,25 @@
2963	3598	for (i = 0; i < num_configs; i++) {
2964	3599	param = pinconf_to_config_param(configs[i]);
2965	3600	arg = pinconf_to_config_argument(configs[i]);
	3601	+
	3602	+ if (param == PIN_CONFIG_OUTPUT \|\| param == PIN_CONFIG_INPUT_ENABLE) {
	3603	+ /*
	3604	+ * Check for gpio driver not being probed yet.
	3605	+ * The lock makes sure that either gpio-probe has completed
	3606	+ * or the gpio driver hasn't probed yet.
	3607	+ */
	3608	+ mutex_lock(&bank->deferred_lock);
	3609	+ if (!gpio \|\| !gpio->direction_output) {
	3610	+ rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
	3611	+ arg);
	3612	+ mutex_unlock(&bank->deferred_lock);
	3613	+ if (rc)
	3614	+ return rc;
	3615	+
	3616	+ break;
	3617	+ }
	3618	+ mutex_unlock(&bank->deferred_lock);
	3619	+ }
2966	3620
2967	3621	switch (param) {
2968	3622	case PIN_CONFIG_BIAS_DISABLE:
..	..	@@ -2989,10 +3643,8 @@
2989	3643	case PIN_CONFIG_OUTPUT:
2990	3644	rc = rockchip_set_mux(bank, pin - bank->pin_base,
2991	3645	RK_FUNC_GPIO);
2992		- if (rc != RK_FUNC_GPIO) {
2993		- dev_err(info->dev, "pin-%d fail to mux to gpio, %d\n", pin, rc);
	3646	+ if (rc != RK_FUNC_GPIO)
2994	3647	return -EINVAL;
2995		- }
2996	3648
2997	3649	rc = gpio->direction_output(gpio, pin - bank->pin_base,
2998	3650	arg);
..	..	@@ -3077,13 +3729,13 @@
3077	3729	break;
3078	3730	case PIN_CONFIG_OUTPUT:
3079	3731	rc = rockchip_get_mux(bank, pin - bank->pin_base);
3080		- if (rc != 0)
	3732	+ if (rc != RK_FUNC_GPIO)
3081	3733	return -EINVAL;
3082	3734
3083		- /* 0 for output, 1 for input */
3084		- rc = gpio->get_direction(gpio, pin - bank->pin_base);
3085		- if (rc)
3086		- return -EINVAL;
	3735	+ if (!gpio \|\| !gpio->get) {
	3736	+ arg = 0;
	3737	+ break;
	3738	+ }
3087	3739
3088	3740	rc = gpio->get(gpio, pin - bank->pin_base);
3089	3741	if (rc < 0)
..	..	@@ -3143,24 +3795,13 @@
3143	3795	{},
3144	3796	};
3145	3797
3146		-static bool is_function_node(const struct device_node *np)
3147		-{
3148		- if (of_match_node(rockchip_bank_match, np))
3149		- return false;
3150		-
3151		- if (!strncmp(np->name, "pcfg", 4))
3152		- return false;
3153		-
3154		- return true;
3155		-}
3156		-
3157	3798	static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
3158	3799	struct device_node *np)
3159	3800	{
3160	3801	struct device_node *child;
3161	3802
3162	3803	for_each_child_of_node(np, child) {
3163		- if (!is_function_node(child))
	3804	+ if (of_match_node(rockchip_bank_match, child))
3164	3805	continue;
3165	3806
3166	3807	info->nfunctions++;
..	..	@@ -3173,6 +3814,7 @@
3173	3814	struct rockchip_pinctrl *info,
3174	3815	u32 index)
3175	3816	{
	3817	+ struct device *dev = info->dev;
3176	3818	struct rockchip_pin_bank *bank;
3177	3819	int size;
3178	3820	const __be32 *list;
..	..	@@ -3180,7 +3822,7 @@
3180	3822	int i, j;
3181	3823	int ret;
3182	3824
3183		- dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
	3825	+ dev_dbg(dev, "group(%d): %pOFn\n", index, np);
3184	3826
3185	3827	/* Initialise group */
3186	3828	grp->name = np->name;
..	..	@@ -3192,19 +3834,13 @@
3192	3834	list = of_get_property(np, "rockchip,pins", &size);
3193	3835	/* we do not check return since it's safe node passed down */
3194	3836	size /= sizeof(*list);
3195		- if (!size \|\| size % 4) {
3196		- dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
3197		- return -EINVAL;
3198		- }
	3837	+ if (!size \|\| size % 4)
	3838	+ return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n");
3199	3839
3200	3840	grp->npins = size / 4;
3201	3841
3202		- grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
3203		- GFP_KERNEL);
3204		- grp->data = devm_kcalloc(info->dev,
3205		- grp->npins,
3206		- sizeof(struct rockchip_pin_config),
3207		- GFP_KERNEL);
	3842	+ grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
	3843	+ grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
3208	3844	if (!grp->pins \|\| !grp->data)
3209	3845	return -ENOMEM;
3210	3846
..	..	@@ -3238,6 +3874,7 @@
3238	3874	struct rockchip_pinctrl *info,
3239	3875	u32 index)
3240	3876	{
	3877	+ struct device *dev = info->dev;
3241	3878	struct device_node *child;
3242	3879	struct rockchip_pmx_func *func;
3243	3880	struct rockchip_pin_group *grp;
..	..	@@ -3245,7 +3882,7 @@
3245	3882	static u32 grp_index;
3246	3883	u32 i = 0;
3247	3884
3248		- dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
	3885	+ dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
3249	3886
3250	3887	func = &info->functions[index];
3251	3888
..	..	@@ -3255,8 +3892,7 @@
3255	3892	if (func->ngroups <= 0)
3256	3893	return 0;
3257	3894
3258		- func->groups = devm_kcalloc(info->dev,
3259		- func->ngroups, sizeof(char *), GFP_KERNEL);
	3895	+ func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
3260	3896	if (!func->groups)
3261	3897	return -ENOMEM;
3262	3898
..	..	@@ -3284,32 +3920,26 @@
3284	3920
3285	3921	rockchip_pinctrl_child_count(info, np);
3286	3922
3287		- dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
3288		- dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
	3923	+ dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
	3924	+ dev_dbg(dev, "ngroups = %d\n", info->ngroups);
3289	3925
3290		- info->functions = devm_kcalloc(dev,
3291		- info->nfunctions,
3292		- sizeof(struct rockchip_pmx_func),
3293		- GFP_KERNEL);
	3926	+ info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
3294	3927	if (!info->functions)
3295	3928	return -ENOMEM;
3296	3929
3297		- info->groups = devm_kcalloc(dev,
3298		- info->ngroups,
3299		- sizeof(struct rockchip_pin_group),
3300		- GFP_KERNEL);
	3930	+ info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
3301	3931	if (!info->groups)
3302	3932	return -ENOMEM;
3303	3933
3304	3934	i = 0;
3305	3935
3306	3936	for_each_child_of_node(np, child) {
3307		- if (!is_function_node(child))
	3937	+ if (of_match_node(rockchip_bank_match, child))
3308	3938	continue;
3309	3939
3310	3940	ret = rockchip_pinctrl_parse_functions(child, info, i++);
3311	3941	if (ret) {
3312		- dev_err(&pdev->dev, "failed to parse function\n");
	3942	+ dev_err(dev, "failed to parse function\n");
3313	3943	of_node_put(child);
3314	3944	return ret;
3315	3945	}
..	..	@@ -3324,6 +3954,7 @@
3324	3954	struct pinctrl_desc *ctrldesc = &info->pctl;
3325	3955	struct pinctrl_pin_desc pindesc, pdesc;
3326	3956	struct rockchip_pin_bank *pin_bank;
	3957	+ struct device *dev = &pdev->dev;
3327	3958	int pin, bank, ret;
3328	3959	int k;
3329	3960
..	..	@@ -3333,9 +3964,7 @@
3333	3964	ctrldesc->pmxops = &rockchip_pmx_ops;
3334	3965	ctrldesc->confops = &rockchip_pinconf_ops;
3335	3966
3336		- pindesc = devm_kcalloc(&pdev->dev,
3337		- info->ctrl->nr_pins, sizeof(*pindesc),
3338		- GFP_KERNEL);
	3967	+ pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
3339	3968	if (!pindesc)
3340	3969	return -ENOMEM;
3341	3970
..	..	@@ -3351,41 +3980,24 @@
3351	3980	pin_bank->name, pin);
3352	3981	pdesc++;
3353	3982	}
	3983	+
	3984	+ INIT_LIST_HEAD(&pin_bank->deferred_pins);
	3985	+ mutex_init(&pin_bank->deferred_lock);
3354	3986	}
3355	3987
3356	3988	ret = rockchip_pinctrl_parse_dt(pdev, info);
3357	3989	if (ret)
3358	3990	return ret;
3359	3991
3360		- info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
3361		- if (IS_ERR(info->pctl_dev)) {
3362		- dev_err(&pdev->dev, "could not register pinctrl driver\n");
3363		- return PTR_ERR(info->pctl_dev);
3364		- }
	3992	+ info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
	3993	+ if (IS_ERR(info->pctl_dev))
	3994	+ return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
3365	3995
3366	3996	return 0;
3367	3997	}
3368	3998
3369	3999	static const struct of_device_id rockchip_pinctrl_dt_match[];
3370		-
3371		-/* Ctrl data specially handle */
3372		-static int rk3308b_ctrl_data_re_init(struct rockchip_pin_ctrl *ctrl)
3373		-{
3374		- /*
3375		- * Special for rk3308b, where we need to replace the recalced
3376		- * and routed arrays.
3377		- */
3378		- if (soc_is_rk3308b()) {
3379		- ctrl->iomux_recalced = rk3308b_mux_recalced_data;
3380		- ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data);
3381		- ctrl->iomux_routes = rk3308b_mux_route_data;
3382		- ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data);
3383		-
3384		- }
3385		-
3386		- return 0;
3387		-}
3388		-
	4000	+static struct rockchip_pin_bank rk3308bs_pin_banks[];
3389	4001	static struct rockchip_pin_bank px30s_pin_banks[];
3390	4002
3391	4003	/* retrieve the soc specific data */
..	..	@@ -3393,22 +4005,19 @@
3393	4005	struct rockchip_pinctrl *d,
3394	4006	struct platform_device *pdev)
3395	4007	{
	4008	+ struct device *dev = &pdev->dev;
	4009	+ struct device_node *node = dev->of_node;
3396	4010	const struct of_device_id *match;
3397		- struct device_node *node = pdev->dev.of_node;
3398	4011	struct rockchip_pin_ctrl *ctrl;
3399	4012	struct rockchip_pin_bank *bank;
3400	4013	int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3401	4014
3402	4015	match = of_match_node(rockchip_pinctrl_dt_match, node);
3403	4016	ctrl = (struct rockchip_pin_ctrl *)match->data;
	4017	+ if (IS_ENABLED(CONFIG_CPU_RK3308) && soc_is_rk3308bs())
	4018	+ ctrl->pin_banks = rk3308bs_pin_banks;
3404	4019	if (IS_ENABLED(CONFIG_CPU_PX30) && soc_is_px30s())
3405	4020	ctrl->pin_banks = px30s_pin_banks;
3406		-
3407		- /* Ctrl data re-initialize for some Socs */
3408		- if (ctrl->ctrl_data_re_init) {
3409		- if (ctrl->ctrl_data_re_init(ctrl))
3410		- return NULL;
3411		- }
3412	4021
3413	4022	grf_offs = ctrl->grf_mux_offset;
3414	4023	pmu_offs = ctrl->pmu_mux_offset;
..	..	@@ -3455,7 +4064,7 @@
3455	4064	drv_pmu_offs : drv_grf_offs;
3456	4065	}
3457	4066
3458		- dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
	4067	+ dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3459	4068	i, j, iom->offset, drv->offset);
3460	4069
3461	4070	/*
..	..	@@ -3562,60 +4171,56 @@
3562	4171
3563	4172	/* SoC data specially handle */
3564	4173
3565		-/* rk3308b SoC data initialize */
3566		-#define RK3308B_GRF_SOC_CON13 0x608
3567		-#define RK3308B_GRF_SOC_CON15 0x610
	4174	+/* rk3308 SoC data initialize */
	4175	+#define RK3308_GRF_SOC_CON13 0x608
	4176	+#define RK3308_GRF_SOC_CON15 0x610
3568	4177
3569		-/* RK3308B_GRF_SOC_CON13 */
3570		-#define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) \| BIT(10))
3571		-#define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) \| BIT(7))
3572		-#define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) \| BIT(3))
	4178	+/* RK3308_GRF_SOC_CON13 */
	4179	+#define RK3308_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) \| BIT(10))
	4180	+#define RK3308_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) \| BIT(7))
	4181	+#define RK3308_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) \| BIT(3))
3573	4182
3574		-/* RK3308B_GRF_SOC_CON15 */
3575		-#define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) \| BIT(11))
3576		-#define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) \| BIT(7))
3577		-#define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) \| BIT(3))
	4183	+/* RK3308_GRF_SOC_CON15 */
	4184	+#define RK3308_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) \| BIT(11))
	4185	+#define RK3308_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) \| BIT(7))
	4186	+#define RK3308_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) \| BIT(3))
3578	4187
3579		-static int rk3308b_soc_data_init(struct rockchip_pinctrl *info)
	4188	+static int rk3308_soc_data_init(struct rockchip_pinctrl *info)
3580	4189	{
3581	4190	int ret;
3582	4191
3583	4192	/*
3584	4193	* Enable the special ctrl of selected sources.
3585	4194	*/
3586		- if (soc_is_rk3308b()) {
3587		- ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON13,
3588		- RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL \|
3589		- RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL \|
3590		- RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL);
3591		- if (ret)
3592		- return ret;
3593	4195
3594		- ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON15,
3595		- RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL \|
3596		- RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL \|
3597		- RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL);
3598		- if (ret)
3599		- return ret;
3600		- }
	4196	+ ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON13,
	4197	+ RK3308_GRF_I2C3_IOFUNC_SRC_CTRL \|
	4198	+ RK3308_GRF_GPIO2A3_SEL_SRC_CTRL \|
	4199	+ RK3308_GRF_GPIO2A2_SEL_SRC_CTRL);
	4200	+ if (ret)
	4201	+ return ret;
3601	4202
3602		- return 0;
	4203	+ ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON15,
	4204	+ RK3308_GRF_GPIO2C0_SEL_SRC_CTRL \|
	4205	+ RK3308_GRF_GPIO3B3_SEL_SRC_CTRL \|
	4206	+ RK3308_GRF_GPIO3B2_SEL_SRC_CTRL);
	4207	+
	4208	+ return ret;
	4209	+
3603	4210	}
3604	4211
3605	4212	static int rockchip_pinctrl_probe(struct platform_device *pdev)
3606	4213	{
3607	4214	struct rockchip_pinctrl *info;
3608	4215	struct device *dev = &pdev->dev;
	4216	+ struct device_node np = dev->of_node, node;
3609	4217	struct rockchip_pin_ctrl *ctrl;
3610		- struct device_node np = pdev->dev.of_node, node;
3611	4218	struct resource *res;
3612	4219	void __iomem *base;
3613	4220	int ret;
3614	4221
3615		- if (!dev->of_node) {
3616		- dev_err(dev, "device tree node not found\n");
3617		- return -ENODEV;
3618		- }
	4222	+ if (!dev->of_node)
	4223	+ return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
3619	4224
3620	4225	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3621	4226	if (!info)
..	..	@@ -3624,44 +4229,39 @@
3624	4229	info->dev = dev;
3625	4230
3626	4231	ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3627		- if (!ctrl) {
3628		- dev_err(dev, "driver data not available\n");
3629		- return -EINVAL;
3630		- }
	4232	+ if (!ctrl)
	4233	+ return dev_err_probe(dev, -EINVAL, "driver data not available\n");
3631	4234	info->ctrl = ctrl;
3632	4235
3633	4236	node = of_parse_phandle(np, "rockchip,grf", 0);
3634	4237	if (node) {
3635	4238	info->regmap_base = syscon_node_to_regmap(node);
	4239	+ of_node_put(node);
3636	4240	if (IS_ERR(info->regmap_base))
3637	4241	return PTR_ERR(info->regmap_base);
3638	4242	} else {
3639		- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3640		- base = devm_ioremap_resource(&pdev->dev, res);
	4243	+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
3641	4244	if (IS_ERR(base))
3642	4245	return PTR_ERR(base);
3643	4246
3644	4247	rockchip_regmap_config.max_register = resource_size(res) - 4;
3645	4248	rockchip_regmap_config.name = "rockchip,pinctrl";
3646		- info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3647		- &rockchip_regmap_config);
	4249	+ info->regmap_base =
	4250	+ devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3648	4251
3649	4252	/* to check for the old dt-bindings */
3650	4253	info->reg_size = resource_size(res);
3651	4254
3652	4255	/* Honor the old binding, with pull registers as 2nd resource */
3653	4256	if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3654		- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3655		- base = devm_ioremap_resource(&pdev->dev, res);
	4257	+ base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
3656	4258	if (IS_ERR(base))
3657	4259	return PTR_ERR(base);
3658	4260
3659		- rockchip_regmap_config.max_register =
3660		- resource_size(res) - 4;
	4261	+ rockchip_regmap_config.max_register = resource_size(res) - 4;
3661	4262	rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3662		- info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3663		- base,
3664		- &rockchip_regmap_config);
	4263	+ info->regmap_pull =
	4264	+ devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3665	4265	}
3666	4266	}
3667	4267
..	..	@@ -3669,13 +4269,13 @@
3669	4269	node = of_parse_phandle(np, "rockchip,pmu", 0);
3670	4270	if (node) {
3671	4271	info->regmap_pmu = syscon_node_to_regmap(node);
	4272	+ of_node_put(node);
3672	4273	if (IS_ERR(info->regmap_pmu))
3673	4274	return PTR_ERR(info->regmap_pmu);
3674	4275	}
3675	4276
3676		- /* Special handle for some Socs */
3677		- if (ctrl->soc_data_init) {
3678		- ret = ctrl->soc_data_init(info);
	4277	+ if (IS_ENABLED(CONFIG_CPU_RK3308) && ctrl->type == RK3308) {
	4278	+ ret = rk3308_soc_data_init(info);
3679	4279	if (ret)
3680	4280	return ret;
3681	4281	}
..	..	@@ -3685,16 +4285,49 @@
3685	4285	return ret;
3686	4286
3687	4287	platform_set_drvdata(pdev, info);
	4288	+ g_pctldev = info->pctl_dev;
3688	4289
3689		- ret = of_platform_populate(np, rockchip_bank_match, NULL, NULL);
3690		- if (ret) {
3691		- dev_err(&pdev->dev, "failed to register gpio device\n");
3692		- return ret;
3693		- }
	4290	+ ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
	4291	+ if (ret)
	4292	+ return dev_err_probe(dev, ret, "failed to register gpio device\n");
	4293	+
3694	4294	dev_info(dev, "probed %s\n", dev_name(dev));
3695	4295
3696	4296	return 0;
3697	4297	}
	4298	+
	4299	+static int rockchip_pinctrl_remove(struct platform_device *pdev)
	4300	+{
	4301	+ struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
	4302	+ struct rockchip_pin_bank *bank;
	4303	+ struct rockchip_pin_deferred *cfg;
	4304	+ int i;
	4305	+
	4306	+ g_pctldev = NULL;
	4307	+ of_platform_depopulate(&pdev->dev);
	4308	+
	4309	+ for (i = 0; i < info->ctrl->nr_banks; i++) {
	4310	+ bank = &info->ctrl->pin_banks[i];
	4311	+
	4312	+ mutex_lock(&bank->deferred_lock);
	4313	+ while (!list_empty(&bank->deferred_pins)) {
	4314	+ cfg = list_first_entry(&bank->deferred_pins,
	4315	+ struct rockchip_pin_deferred, head);
	4316	+ list_del(&cfg->head);
	4317	+ kfree(cfg);
	4318	+ }
	4319	+ mutex_unlock(&bank->deferred_lock);
	4320	+ }
	4321	+
	4322	+ return 0;
	4323	+}
	4324	+
	4325	+static struct rockchip_pin_bank px30s_pin_banks[] __maybe_unused = {
	4326	+ S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, DRV_TYPE_IO_SMIC),
	4327	+ S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
	4328	+ S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
	4329	+ S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
	4330	+};
3698	4331
3699	4332	static struct rockchip_pin_bank px30_pin_banks[] = {
3700	4333	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
..	..	@@ -3719,13 +4352,6 @@
3719	4352	),
3720	4353	};
3721	4354
3722		-static struct rockchip_pin_bank px30s_pin_banks[] __maybe_unused = {
3723		- PX30S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, DRV_TYPE_IO_SMIC),
3724		- PX30S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
3725		- PX30S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
3726		- PX30S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
3727		-};
3728		-
3729	4355	static struct rockchip_pin_ctrl px30_pin_ctrl __maybe_unused = {
3730	4356	.pin_banks = px30_pin_banks,
3731	4357	.nr_banks = ARRAY_SIZE(px30_pin_banks),
..	..	@@ -3739,6 +4365,48 @@
3739	4365	.drv_calc_reg = px30_calc_drv_reg_and_bit,
3740	4366	.schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3741	4367	.slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit,
	4368	+};
	4369	+
	4370	+static struct rockchip_pin_bank rv1106_pin_banks[] = {
	4371	+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
	4372	+ IOMUX_WIDTH_4BIT \| IOMUX_SOURCE_PMU,
	4373	+ IOMUX_WIDTH_4BIT \| IOMUX_SOURCE_PMU,
	4374	+ IOMUX_WIDTH_4BIT \| IOMUX_SOURCE_PMU,
	4375	+ IOMUX_WIDTH_4BIT \| IOMUX_SOURCE_PMU),
	4376	+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
	4377	+ IOMUX_WIDTH_4BIT,
	4378	+ IOMUX_WIDTH_4BIT,
	4379	+ IOMUX_WIDTH_4BIT,
	4380	+ IOMUX_WIDTH_4BIT,
	4381	+ 0, 0x08, 0x10, 0x18),
	4382	+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
	4383	+ IOMUX_WIDTH_4BIT,
	4384	+ IOMUX_WIDTH_4BIT,
	4385	+ IOMUX_WIDTH_4BIT,
	4386	+ IOMUX_WIDTH_4BIT,
	4387	+ 0x10020, 0x10028, 0, 0),
	4388	+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
	4389	+ IOMUX_WIDTH_4BIT,
	4390	+ IOMUX_WIDTH_4BIT,
	4391	+ IOMUX_WIDTH_4BIT,
	4392	+ IOMUX_WIDTH_4BIT,
	4393	+ 0x20040, 0x20048, 0x20050, 0x20058),
	4394	+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 24, "gpio4",
	4395	+ IOMUX_WIDTH_4BIT,
	4396	+ IOMUX_WIDTH_4BIT,
	4397	+ IOMUX_WIDTH_4BIT,
	4398	+ 0,
	4399	+ 0x30000, 0x30008, 0x30010, 0),
	4400	+};
	4401	+
	4402	+static struct rockchip_pin_ctrl rv1106_pin_ctrl __maybe_unused = {
	4403	+ .pin_banks = rv1106_pin_banks,
	4404	+ .nr_banks = ARRAY_SIZE(rv1106_pin_banks),
	4405	+ .label = "RV1106-GPIO",
	4406	+ .type = RV1106,
	4407	+ .pull_calc_reg = rv1106_calc_pull_reg_and_bit,
	4408	+ .drv_calc_reg = rv1106_calc_drv_reg_and_bit,
	4409	+ .schmitt_calc_reg = rv1106_calc_schmitt_reg_and_bit,
3742	4410	};
3743	4411
3744	4412	static struct rockchip_pin_bank rv1108_pin_banks[] = {
..	..	@@ -4011,6 +4679,14 @@
4011	4679	.drv_calc_reg = rk3288_calc_drv_reg_and_bit,
4012	4680	};
4013	4681
	4682	+static struct rockchip_pin_bank rk3308bs_pin_banks[] __maybe_unused = {
	4683	+ S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4684	+ S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4685	+ S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4686	+ S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4687	+ S_PIN_BANK_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4688	+};
	4689	+
4014	4690	static struct rockchip_pin_bank rk3308_pin_banks[] = {
4015	4691	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
4016	4692	IOMUX_WIDTH_2BIT,
..	..	@@ -4044,11 +4720,10 @@
4044	4720	.niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
4045	4721	.iomux_routes = rk3308_mux_route_data,
4046	4722	.niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
4047		- .ctrl_data_re_init = rk3308b_ctrl_data_re_init,
4048		- .soc_data_init = rk3308b_soc_data_init,
4049	4723	.pull_calc_reg = rk3308_calc_pull_reg_and_bit,
4050	4724	.drv_calc_reg = rk3308_calc_drv_reg_and_bit,
4051	4725	.schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
	4726	+ .slew_rate_calc_reg = rk3308_calc_slew_rate_reg_and_bit,
4052	4727	};
4053	4728
4054	4729	static struct rockchip_pin_bank rk3328_pin_banks[] = {
..	..	@@ -4213,6 +4888,49 @@
4213	4888	.schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit,
4214	4889	};
4215	4890
	4891	+static struct rockchip_pin_bank rk3562_pin_banks[] = {
	4892	+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
	4893	+ IOMUX_WIDTH_4BIT,
	4894	+ IOMUX_WIDTH_4BIT,
	4895	+ IOMUX_WIDTH_4BIT,
	4896	+ IOMUX_WIDTH_4BIT,
	4897	+ 0x20000, 0x20008, 0x20010, 0x20018),
	4898	+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
	4899	+ IOMUX_WIDTH_4BIT,
	4900	+ IOMUX_WIDTH_4BIT,
	4901	+ IOMUX_WIDTH_4BIT,
	4902	+ IOMUX_WIDTH_4BIT,
	4903	+ 0, 0x08, 0x10, 0x18),
	4904	+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
	4905	+ IOMUX_WIDTH_4BIT,
	4906	+ IOMUX_WIDTH_4BIT,
	4907	+ IOMUX_WIDTH_4BIT,
	4908	+ IOMUX_WIDTH_4BIT,
	4909	+ 0x20, 0, 0, 0),
	4910	+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
	4911	+ IOMUX_WIDTH_4BIT,
	4912	+ IOMUX_WIDTH_4BIT,
	4913	+ IOMUX_WIDTH_4BIT,
	4914	+ IOMUX_WIDTH_4BIT,
	4915	+ 0x10040, 0x10048, 0x10050, 0x10058),
	4916	+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
	4917	+ IOMUX_WIDTH_4BIT,
	4918	+ IOMUX_WIDTH_4BIT,
	4919	+ 0,
	4920	+ 0,
	4921	+ 0x10060, 0x10068, 0, 0),
	4922	+};
	4923	+
	4924	+static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = {
	4925	+ .pin_banks = rk3562_pin_banks,
	4926	+ .nr_banks = ARRAY_SIZE(rk3562_pin_banks),
	4927	+ .label = "RK3562-GPIO",
	4928	+ .type = RK3562,
	4929	+ .pull_calc_reg = rk3562_calc_pull_reg_and_bit,
	4930	+ .drv_calc_reg = rk3562_calc_drv_reg_and_bit,
	4931	+ .schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit,
	4932	+};
	4933	+
4216	4934	static struct rockchip_pin_bank rk3568_pin_banks[] = {
4217	4935	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU \| IOMUX_WIDTH_4BIT,
4218	4936	IOMUX_SOURCE_PMU \| IOMUX_WIDTH_4BIT,
..	..	@@ -4253,12 +4971,39 @@
4253	4971	.schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
4254	4972	};
4255	4973
	4974	+static struct rockchip_pin_bank rk3588_pin_banks[] = {
	4975	+ RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
	4976	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	4977	+ RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
	4978	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	4979	+ RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
	4980	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	4981	+ RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
	4982	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	4983	+ RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
	4984	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	4985	+};
	4986	+
	4987	+static struct rockchip_pin_ctrl rk3588_pin_ctrl __maybe_unused = {
	4988	+ .pin_banks = rk3588_pin_banks,
	4989	+ .nr_banks = ARRAY_SIZE(rk3588_pin_banks),
	4990	+ .label = "RK3588-GPIO",
	4991	+ .type = RK3588,
	4992	+ .pull_calc_reg = rk3588_calc_pull_reg_and_bit,
	4993	+ .drv_calc_reg = rk3588_calc_drv_reg_and_bit,
	4994	+ .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit,
	4995	+};
	4996	+
4256	4997	static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4257	4998	#ifdef CONFIG_CPU_PX30
4258	4999	{ .compatible = "rockchip,px30-pinctrl",
4259	5000	.data = &px30_pin_ctrl },
4260	5001	#endif
4261		-#ifdef CONFIG_CPU_RV110X
	5002	+#ifdef CONFIG_CPU_RV1106
	5003	+ { .compatible = "rockchip,rv1106-pinctrl",
	5004	+ .data = &rv1106_pin_ctrl },
	5005	+#endif
	5006	+#ifdef CONFIG_CPU_RV1108
4262	5007	{ .compatible = "rockchip,rv1108-pinctrl",
4263	5008	.data = &rv1108_pin_ctrl },
4264	5009	#endif
..	..	@@ -4320,15 +5065,24 @@
4320	5065	{ .compatible = "rockchip,rk3528-pinctrl",
4321	5066	.data = &rk3528_pin_ctrl },
4322	5067	#endif
	5068	+#ifdef CONFIG_CPU_RK3562
	5069	+ { .compatible = "rockchip,rk3562-pinctrl",
	5070	+ .data = &rk3562_pin_ctrl },
	5071	+#endif
4323	5072	#ifdef CONFIG_CPU_RK3568
4324	5073	{ .compatible = "rockchip,rk3568-pinctrl",
4325	5074	.data = &rk3568_pin_ctrl },
	5075	+#endif
	5076	+#ifdef CONFIG_CPU_RK3588
	5077	+ { .compatible = "rockchip,rk3588-pinctrl",
	5078	+ .data = &rk3588_pin_ctrl },
4326	5079	#endif
4327	5080	{},
4328	5081	};
4329	5082
4330	5083	static struct platform_driver rockchip_pinctrl_driver = {
4331	5084	.probe = rockchip_pinctrl_probe,
	5085	+ .remove = rockchip_pinctrl_remove,
4332	5086	.driver = {
4333	5087	.name = "rockchip-pinctrl",
4334	5088	.pm = &rockchip_pinctrl_dev_pm_ops,
..	..	@@ -4348,6 +5102,103 @@
4348	5102	}
4349	5103	module_exit(rockchip_pinctrl_drv_unregister);
4350	5104
	5105	+/**
	5106	+ * rk_iomux_set - set the rockchip iomux by pin number.
	5107	+ *
	5108	+ * @bank: the gpio bank index, from 0 to the max bank num.
	5109	+ * @pin: the gpio pin index, from 0 to 31.
	5110	+ * @mux: the pointer to store mux value.
	5111	+ *
	5112	+ * Return 0 if set success, else return error code.
	5113	+ */
	5114	+int rk_iomux_set(int bank, int pin, int mux)
	5115	+{
	5116	+ struct pinctrl_dev *pctldev = g_pctldev;
	5117	+ struct rockchip_pinctrl *info;
	5118	+ struct rockchip_pin_bank *gpio;
	5119	+ struct rockchip_pin_group *grp = NULL;
	5120	+ struct rockchip_pin_config *cfg = NULL;
	5121	+ int i, j, ret;
	5122	+
	5123	+ if (!g_pctldev)
	5124	+ return -ENODEV;
	5125	+
	5126	+ info = pinctrl_dev_get_drvdata(pctldev);
	5127	+ if (bank >= info->ctrl->nr_banks)
	5128	+ return -EINVAL;
	5129	+
	5130	+ if (pin > 31 \|\| pin < 0)
	5131	+ return -EINVAL;
	5132	+
	5133	+ gpio = &info->ctrl->pin_banks[bank];
	5134	+
	5135	+ mutex_lock(&iomux_lock);
	5136	+ for (i = 0; i < info->ngroups; i++) {
	5137	+ grp = &info->groups[i];
	5138	+ for (j = 0; j < grp->npins; i++) {
	5139	+ if (grp->pins[i] == (gpio->pin_base + pin)) {
	5140	+ cfg = grp->data;
	5141	+ break;
	5142	+ }
	5143	+ }
	5144	+ }
	5145	+
	5146	+ ret = rockchip_set_mux(gpio, pin, mux);
	5147	+ if (ret) {
	5148	+ dev_err(info->dev, "mux GPIO%d-%d %d fail\n", bank, pin, mux);
	5149	+ goto out;
	5150	+ }
	5151	+
	5152	+ if (cfg && (cfg->func != mux))
	5153	+ cfg->func = mux;
	5154	+
	5155	+out:
	5156	+ mutex_unlock(&iomux_lock);
	5157	+
	5158	+ return ret;
	5159	+}
	5160	+EXPORT_SYMBOL_GPL(rk_iomux_set);
	5161	+
	5162	+/**
	5163	+ * rk_iomux_get - get the rockchip iomux by pin number.
	5164	+ *
	5165	+ * @bank: the gpio bank index, from 0 to the max bank num.
	5166	+ * @pin: the gpio pin index, from 0 to 31.
	5167	+ * @mux: the pointer to store mux value.
	5168	+ *
	5169	+ * Return 0 if get success, else return error code.
	5170	+ */
	5171	+int rk_iomux_get(int bank, int pin, int *mux)
	5172	+{
	5173	+ struct pinctrl_dev *pctldev = g_pctldev;
	5174	+ struct rockchip_pinctrl *info;
	5175	+ struct rockchip_pin_bank *gpio;
	5176	+ int ret;
	5177	+
	5178	+ if (!g_pctldev)
	5179	+ return -ENODEV;
	5180	+ if (!mux)
	5181	+ return -EINVAL;
	5182	+
	5183	+ info = pinctrl_dev_get_drvdata(pctldev);
	5184	+ if (bank >= info->ctrl->nr_banks)
	5185	+ return -EINVAL;
	5186	+
	5187	+ if (pin > 31 \|\| pin < 0)
	5188	+ return -EINVAL;
	5189	+
	5190	+ gpio = &info->ctrl->pin_banks[bank];
	5191	+
	5192	+ mutex_lock(&iomux_lock);
	5193	+ ret = rockchip_get_mux(gpio, pin);
	5194	+ mutex_unlock(&iomux_lock);
	5195	+
	5196	+ *mux = ret;
	5197	+
	5198	+ return (ret >= 0) ? 0 : ret;
	5199	+}
	5200	+EXPORT_SYMBOL_GPL(rk_iomux_get);
	5201	+
4351	5202	MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
4352	5203	MODULE_LICENSE("GPL");
4353	5204	MODULE_ALIAS("platform:pinctrl-rockchip");