forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c
....@@ -21,11 +21,24 @@
2121 #include <media/v4l2-fwnode.h>
2222 #include <media/v4l2-subdev.h>
2323 #include <media/v4l2-device.h>
24
+#include <linux/reset.h>
2425 #include "phy-rockchip-csi2-dphy-common.h"
26
+
27
+/* RK3562 DPHY GRF REG OFFSET */
28
+#define RK3562_GRF_VI_CON0	(0x0520)
29
+#define RK3562_GRF_VI_CON1	(0x0524)
2530 
2631 /* GRF REG OFFSET */
2732 #define GRF_VI_CON0	(0x0340)
2833 #define GRF_VI_CON1	(0x0344)
34
+
35
+/*RK3588 DPHY GRF REG OFFSET */
36
+#define GRF_DPHY_CON0	(0x0)
37
+#define GRF_SOC_CON2	(0x0308)
38
+
39
+/*RV1106 DPHY GRF REG OFFSET */
40
+#define GRF_VI_MISC_CON0	(0x50000)
41
+#define GRF_VI_CSIPHY_CON5	(0x50014)
2942 
3043 /*GRF REG BIT DEFINE */
3144 #define GRF_CSI2PHY_LANE_SEL_SPLIT	(0x1)
....@@ -37,7 +50,10 @@
3750 #define CSI2_DPHY_CTRL_PWRCTL	\
3851 				CSI2_DPHY_CTRL_INVALID_OFFSET
3952 #define CSI2_DPHY_CTRL_LANE_ENABLE	(0x00)
53
+#define CSI2_DPHY_CLK1_LANE_EN		(0x2C)
4054 #define CSI2_DPHY_DUAL_CAL_EN		(0x80)
55
+#define CSI2_DPHY_CLK_INV		(0X84)
56
+
4157 #define CSI2_DPHY_CLK_WR_THS_SETTLE	(0x160)
4258 #define CSI2_DPHY_CLK_CALIB_EN		(0x168)
4359 #define CSI2_DPHY_LANE0_WR_THS_SETTLE	(0x1e0)
....@@ -50,6 +66,11 @@
5066 #define CSI2_DPHY_LANE3_CALIB_EN	(0x368)
5167 #define CSI2_DPHY_CLK1_WR_THS_SETTLE	(0x3e0)
5268 #define CSI2_DPHY_CLK1_CALIB_EN		(0x3e8)
69
+
70
+#define CSI2_DPHY_PATH0_MODE_SEL	(0x44C)
71
+#define CSI2_DPHY_PATH0_LVDS_MODE_SEL	(0x480)
72
+#define CSI2_DPHY_PATH1_MODE_SEL	(0x84C)
73
+#define CSI2_DPHY_PATH1_LVDS_MODE_SEL	(0x880)
5374 
5475 /* PHY REG BIT DEFINE */
5576 #define CSI2_DPHY_LANE_MODE_FULL	(0x4)
....@@ -128,8 +149,26 @@
128149 	GRF_DPHY_ISP_CSI2PHY_SEL,
129150 	GRF_DPHY_CIF_CSI2PHY_SEL,
130151 	GRF_DPHY_CSI2PHY_LANE_SEL,
152
+	GRF_DPHY_CSI2PHY1_LANE_SEL,
131153 	GRF_DPHY_CSI2PHY_DATALANE_EN0,
132154 	GRF_DPHY_CSI2PHY_DATALANE_EN1,
155
+	GRF_CPHY_MODE,
156
+	GRF_DPHY_CSIHOST2_SEL,
157
+	GRF_DPHY_CSIHOST3_SEL,
158
+	GRF_DPHY_CSIHOST4_SEL,
159
+	GRF_DPHY_CSIHOST5_SEL,
160
+	/* below is for rv1106 only */
161
+	GRF_MIPI_HOST0_SEL,
162
+	GRF_LVDS_HOST0_SEL,
163
+	/* below is for rk3562 */
164
+	GRF_DPHY1_CLK_INV_SEL,
165
+	GRF_DPHY1_CLK1_INV_SEL,
166
+	GRF_DPHY1_CSI2PHY_CLKLANE1_EN,
167
+	GRF_DPHY1_CSI2PHY_FORCERXMODE,
168
+	GRF_DPHY1_CSI2PHY_CLKLANE_EN,
169
+	GRF_DPHY1_CSI2PHY_DATALANE_EN,
170
+	GRF_DPHY1_CSI2PHY_DATALANE_EN0,
171
+	GRF_DPHY1_CSI2PHY_DATALANE_EN1,
133172 };
134173 
135174 enum csi2dphy_reg_id {
....@@ -152,7 +191,28 @@
152191 	//rk3568 only
153192 	CSI2PHY_DUAL_CLK_EN,
154193 	CSI2PHY_CLK1_THS_SETTLE,
155
-	CSI2PHY_CLK1_CALIB_ENABLE
194
+	CSI2PHY_CLK1_CALIB_ENABLE,
195
+	//rk3588
196
+	CSI2PHY_CLK_LANE_ENABLE,
197
+	CSI2PHY_CLK1_LANE_ENABLE,
198
+	CSI2PHY_DATA_LANE0_ENABLE,
199
+	CSI2PHY_DATA_LANE1_ENABLE,
200
+	CSI2PHY_DATA_LANE2_ENABLE,
201
+	CSI2PHY_DATA_LANE3_ENABLE,
202
+	CSI2PHY_LANE0_ERR_SOT_SYNC,
203
+	CSI2PHY_LANE1_ERR_SOT_SYNC,
204
+	CSI2PHY_LANE2_ERR_SOT_SYNC,
205
+	CSI2PHY_LANE3_ERR_SOT_SYNC,
206
+	CSI2PHY_S0C_GNR_CON1,
207
+	CSI2PHY_COMBO_S0D0_GNR_CON1,
208
+	CSI2PHY_COMBO_S0D1_GNR_CON1,
209
+	CSI2PHY_COMBO_S0D2_GNR_CON1,
210
+	CSI2PHY_S0D3_GNR_CON1,
211
+	CSI2PHY_PATH0_MODEL,
212
+	CSI2PHY_PATH0_LVDS_MODEL,
213
+	CSI2PHY_PATH1_MODEL,
214
+	CSI2PHY_PATH1_LVDS_MODEL,
215
+	CSI2PHY_CLK_INV,
156216 };
157217 
158218 #define HIWORD_UPDATE(val, mask, shift) \
....@@ -166,8 +226,18 @@
166226 
167227 struct hsfreq_range {
168228 	u32 range_h;
169
-	u8 cfg_bit;
229
+	u16 cfg_bit;
170230 };
231
+
232
+static inline void write_sys_grf_reg(struct csi2_dphy_hw *hw,
233
+				     int index, u8 value)
234
+{
235
+	const struct grf_reg *reg = &hw->grf_regs[index];
236
+	unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
237
+
238
+	if (reg->mask)
239
+		regmap_write(hw->regmap_sys_grf, reg->offset, val);
240
+}
171241 
172242 static inline void write_grf_reg(struct csi2_dphy_hw *hw,
173243 				     int index, u8 value)
....@@ -175,7 +245,7 @@
175245 	const struct grf_reg *reg = &hw->grf_regs[index];
176246 	unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
177247 
178
-	if (reg->offset)
248
+	if (reg->mask)
179249 		regmap_write(hw->regmap_grf, reg->offset, val);
180250 }
181251 
....@@ -184,7 +254,7 @@
184254 	const struct grf_reg *reg = &hw->grf_regs[index];
185255 	unsigned int val = 0;
186256 
187
-	if (reg->offset) {
257
+	if (reg->mask) {
188258 		regmap_read(hw->regmap_grf, reg->offset, &val);
189259 		val = (val >> reg->shift) & reg->mask;
190260 	}
....@@ -198,9 +268,22 @@
198268 	const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
199269 
200270 	if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) ||
271
+	    (index == CSI2PHY_CLK_LANE_ENABLE) ||
201272 	    (index != CSI2PHY_REG_CTRL_LANE_ENABLE &&
202273 	     reg->offset != 0x0))
203274 		writel(value, hw->hw_base_addr + reg->offset);
275
+}
276
+
277
+static inline void write_csi2_dphy_reg_mask(struct csi2_dphy_hw *hw,
278
+					    int index, u32 value, u32 mask)
279
+{
280
+	const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
281
+	u32 read_val = 0;
282
+
283
+	read_val = readl(hw->hw_base_addr + reg->offset);
284
+	read_val &= ~mask;
285
+	read_val |= value;
286
+	writel(read_val, hw->hw_base_addr + reg->offset);
204287 }
205288 
206289 static inline void read_csi2_dphy_reg(struct csi2_dphy_hw *hw,
....@@ -209,6 +292,7 @@
209292 	const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
210293 
211294 	if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) ||
295
+	    (index == CSI2PHY_CLK_LANE_ENABLE) ||
212296 	    (index != CSI2PHY_REG_CTRL_LANE_ENABLE &&
213297 	     reg->offset != 0x0))
214298 		*value = readl(hw->hw_base_addr + reg->offset);
....@@ -280,8 +364,114 @@
280364 	[CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
281365 };
282366 
283
-static const struct clk_bulk_data rk3568_csi2_dphy_hw_clks[] = {
284
-	{ .id = "pclk" },
367
+static const struct grf_reg rk3588_grf_dphy_regs[] = {
368
+	[GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_DPHY_CON0, 4, 0),
369
+	[GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_DPHY_CON0, 4, 4),
370
+	[GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_DPHY_CON0, 2, 4),
371
+	[GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_DPHY_CON0, 2, 6),
372
+	[GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_DPHY_CON0, 1, 8),
373
+	[GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 9),
374
+	[GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_DPHY_CON0, 1, 10),
375
+	[GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 11),
376
+	[GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 6),
377
+	[GRF_DPHY_CSI2PHY1_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 7),
378
+	[GRF_DPHY_CSIHOST2_SEL] = GRF_REG(GRF_SOC_CON2, 1, 8),
379
+	[GRF_DPHY_CSIHOST3_SEL] = GRF_REG(GRF_SOC_CON2, 1, 9),
380
+	[GRF_DPHY_CSIHOST4_SEL] = GRF_REG(GRF_SOC_CON2, 1, 10),
381
+	[GRF_DPHY_CSIHOST5_SEL] = GRF_REG(GRF_SOC_CON2, 1, 11),
382
+};
383
+
384
+static const struct csi2dphy_reg rk3588_csi2dphy_regs[] = {
385
+	[CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
386
+	[CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
387
+	[CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
388
+	[CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
389
+	[CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
390
+	[CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
391
+	[CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
392
+	[CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
393
+	[CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
394
+	[CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
395
+	[CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
396
+	[CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
397
+	[CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
398
+	[CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
399
+	[CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
400
+};
401
+
402
+static const struct grf_reg rv1106_grf_dphy_regs[] = {
403
+	[GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_VI_CSIPHY_CON5, 4, 0),
404
+	[GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 8),
405
+	[GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_VI_CSIPHY_CON5, 4, 4),
406
+	[GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_VI_CSIPHY_CON5, 2, 4),
407
+	[GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_VI_CSIPHY_CON5, 2, 6),
408
+	[GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 9),
409
+	[GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 10),
410
+	[GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 11),
411
+	[GRF_MIPI_HOST0_SEL] = GRF_REG(GRF_VI_MISC_CON0, 1, 0),
412
+	[GRF_LVDS_HOST0_SEL] = GRF_REG(GRF_VI_MISC_CON0, 1, 2),
413
+};
414
+
415
+static const struct csi2dphy_reg rv1106_csi2dphy_regs[] = {
416
+	[CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
417
+	[CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
418
+	[CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
419
+	[CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
420
+	[CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
421
+	[CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
422
+	[CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
423
+	[CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
424
+	[CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
425
+	[CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
426
+	[CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
427
+	[CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
428
+	[CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
429
+	[CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
430
+	[CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
431
+	[CSI2PHY_PATH0_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH0_MODE_SEL),
432
+	[CSI2PHY_PATH0_LVDS_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH0_LVDS_MODE_SEL),
433
+	[CSI2PHY_PATH1_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH1_MODE_SEL),
434
+	[CSI2PHY_PATH1_LVDS_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH1_LVDS_MODE_SEL),
435
+	[CSI2PHY_CLK_INV] = CSI2PHY_REG(CSI2_DPHY_CLK_INV),
436
+};
437
+
438
+static const struct grf_reg rk3562_grf_dphy_regs[] = {
439
+	[GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(RK3562_GRF_VI_CON0, 4, 0),
440
+	[GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(RK3562_GRF_VI_CON0, 4, 4),
441
+	[GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(RK3562_GRF_VI_CON0, 2, 4),
442
+	[GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(RK3562_GRF_VI_CON0, 2, 6),
443
+	[GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(RK3562_GRF_VI_CON0, 1, 8),
444
+	[GRF_DPHY_CLK_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 9),
445
+	[GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(RK3562_GRF_VI_CON0, 1, 10),
446
+	[GRF_DPHY_CLK1_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 11),
447
+	[GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 12),
448
+	[GRF_DPHY_CSI2PHY1_LANE_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 13),
449
+	[GRF_DPHY1_CSI2PHY_FORCERXMODE] = GRF_REG(RK3562_GRF_VI_CON1, 4, 0),
450
+	[GRF_DPHY1_CSI2PHY_DATALANE_EN] = GRF_REG(RK3562_GRF_VI_CON1, 4, 4),
451
+	[GRF_DPHY1_CSI2PHY_DATALANE_EN0] = GRF_REG(RK3562_GRF_VI_CON1, 2, 4),
452
+	[GRF_DPHY1_CSI2PHY_DATALANE_EN1] = GRF_REG(RK3562_GRF_VI_CON1, 2, 6),
453
+	[GRF_DPHY1_CSI2PHY_CLKLANE_EN] = GRF_REG(RK3562_GRF_VI_CON1, 1, 8),
454
+	[GRF_DPHY1_CLK_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON1, 1, 9),
455
+	[GRF_DPHY1_CSI2PHY_CLKLANE1_EN] = GRF_REG(RK3562_GRF_VI_CON1, 1, 10),
456
+	[GRF_DPHY1_CLK1_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON1, 1, 11),
457
+};
458
+
459
+static const struct csi2dphy_reg rk3562_csi2dphy_regs[] = {
460
+	[CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
461
+	[CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
462
+	[CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
463
+	[CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
464
+	[CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
465
+	[CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
466
+	[CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
467
+	[CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
468
+	[CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
469
+	[CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
470
+	[CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
471
+	[CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
472
+	[CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
473
+	[CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
474
+	[CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
285475 };
286476 
287477 /* These tables must be sorted by .range_h ascending. */
....@@ -321,6 +511,51 @@
321511 	return NULL;
322512 }
323513 
514
+static unsigned char get_lvds_data_width(u32 pixelformat)
515
+{
516
+	switch (pixelformat) {
517
+	/* csi raw8 */
518
+	case MEDIA_BUS_FMT_SBGGR8_1X8:
519
+	case MEDIA_BUS_FMT_SGBRG8_1X8:
520
+	case MEDIA_BUS_FMT_SGRBG8_1X8:
521
+	case MEDIA_BUS_FMT_SRGGB8_1X8:
522
+		return 0x2;
523
+	/* csi raw10 */
524
+	case MEDIA_BUS_FMT_SBGGR10_1X10:
525
+	case MEDIA_BUS_FMT_SGBRG10_1X10:
526
+	case MEDIA_BUS_FMT_SGRBG10_1X10:
527
+	case MEDIA_BUS_FMT_SRGGB10_1X10:
528
+		return 0x0;
529
+	/* csi raw12 */
530
+	case MEDIA_BUS_FMT_SBGGR12_1X12:
531
+	case MEDIA_BUS_FMT_SGBRG12_1X12:
532
+	case MEDIA_BUS_FMT_SGRBG12_1X12:
533
+	case MEDIA_BUS_FMT_SRGGB12_1X12:
534
+		return 0x1;
535
+	/* csi uyvy 422 */
536
+	case MEDIA_BUS_FMT_UYVY8_2X8:
537
+	case MEDIA_BUS_FMT_VYUY8_2X8:
538
+	case MEDIA_BUS_FMT_YUYV8_2X8:
539
+	case MEDIA_BUS_FMT_YVYU8_2X8:
540
+	case MEDIA_BUS_FMT_RGB888_1X24:
541
+		return 0x2;
542
+
543
+	default:
544
+		return 0x2;
545
+	}
546
+}
547
+
548
+static void csi2_dphy_hw_do_reset(struct csi2_dphy_hw *hw)
549
+{
550
+	if (hw->rsts_bulk)
551
+		reset_control_assert(hw->rsts_bulk);
552
+
553
+	udelay(5);
554
+
555
+	if (hw->rsts_bulk)
556
+		reset_control_deassert(hw->rsts_bulk);
557
+}
558
+
324559 static void csi2_dphy_config_dual_mode(struct csi2_dphy *dphy,
325560 					       struct csi2_sensor *sensor)
326561 {
....@@ -337,38 +572,108 @@
337572 		is_cif = false;
338573 
339574 	if (hw->lane_mode == LANE_MODE_FULL) {
340
-		val = ~GRF_CSI2PHY_LANE_SEL_SPLIT;
341
-		write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
342
-		write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
343
-			      GENMASK(sensor->lanes - 1, 0));
344
-		write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
575
+		val = !GRF_CSI2PHY_LANE_SEL_SPLIT;
576
+		if (dphy->phy_index < 3) {
577
+			write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
578
+				      GENMASK(sensor->lanes - 1, 0));
579
+			write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
580
+			if (hw->drv_data->chip_id != CHIP_ID_RK3588)
581
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
582
+			else
583
+				write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
584
+		} else {
585
+			if (hw->drv_data->chip_id <= CHIP_ID_RK3588) {
586
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
587
+					      GENMASK(sensor->lanes - 1, 0));
588
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
589
+			} else {
590
+				write_grf_reg(hw, GRF_DPHY1_CSI2PHY_DATALANE_EN,
591
+					      GENMASK(sensor->lanes - 1, 0));
592
+				write_grf_reg(hw, GRF_DPHY1_CSI2PHY_CLKLANE_EN, 0x1);
593
+			}
594
+			if (hw->drv_data->chip_id != CHIP_ID_RK3588)
595
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
596
+			else
597
+				write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
598
+		}
345599 	} else {
346600 		val = GRF_CSI2PHY_LANE_SEL_SPLIT;
347
-		write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
348601 
349
-		if (dphy->phy_index == DPHY1) {
602
+		switch (dphy->phy_index) {
603
+		case 1:
350604 			write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0,
351605 				      GENMASK(sensor->lanes - 1, 0));
352606 			write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
353
-			if (is_cif)
354
-				write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
355
-					      GRF_CSI2PHY_SEL_SPLIT_0_1);
356
-			else
357
-				write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
358
-					      GRF_CSI2PHY_SEL_SPLIT_0_1);
359
-		}
360
-
361
-		if (dphy->phy_index == DPHY2) {
607
+			if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
608
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
609
+				if (is_cif)
610
+					write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
611
+						      GRF_CSI2PHY_SEL_SPLIT_0_1);
612
+				else
613
+					write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
614
+						      GRF_CSI2PHY_SEL_SPLIT_0_1);
615
+			} else if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
616
+				write_sys_grf_reg(hw, GRF_DPHY_CSIHOST2_SEL, 0x0);
617
+				write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
618
+			} else if (hw->drv_data->chip_id == CHIP_ID_RV1106) {
619
+				if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY)
620
+					write_grf_reg(hw, GRF_MIPI_HOST0_SEL, 0x1);
621
+				else
622
+					write_grf_reg(hw, GRF_LVDS_HOST0_SEL, 0x1);
623
+			} else if (hw->drv_data->chip_id == CHIP_ID_RK3562) {
624
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
625
+			}
626
+			break;
627
+		case 2:
362628 			write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1,
363629 				      GENMASK(sensor->lanes - 1, 0));
364630 			write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
365
-			if (is_cif)
366
-				write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
367
-					      GRF_CSI2PHY_SEL_SPLIT_2_3);
368
-			else
369
-				write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
370
-					      GRF_CSI2PHY_SEL_SPLIT_2_3);
371
-		}
631
+			if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
632
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
633
+				if (is_cif)
634
+					write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
635
+						GRF_CSI2PHY_SEL_SPLIT_2_3);
636
+				else
637
+					write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
638
+						GRF_CSI2PHY_SEL_SPLIT_2_3);
639
+			} else if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
640
+				write_sys_grf_reg(hw, GRF_DPHY_CSIHOST3_SEL, 0x1);
641
+				write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
642
+			} else if (hw->drv_data->chip_id == CHIP_ID_RK3562) {
643
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
644
+			}
645
+			break;
646
+		case 4:
647
+			if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
648
+				write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
649
+				write_sys_grf_reg(hw, GRF_DPHY_CSIHOST4_SEL, 0x0);
650
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0,
651
+					      GENMASK(sensor->lanes - 1, 0));
652
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
653
+			} else if (hw->drv_data->chip_id == CHIP_ID_RK3562) {
654
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
655
+				write_grf_reg(hw, GRF_DPHY1_CSI2PHY_DATALANE_EN0,
656
+					      GENMASK(sensor->lanes - 1, 0));
657
+				write_grf_reg(hw, GRF_DPHY1_CSI2PHY_CLKLANE_EN, 0x1);
658
+			}
659
+			break;
660
+		case 5:
661
+			if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
662
+				write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
663
+				write_sys_grf_reg(hw, GRF_DPHY_CSIHOST5_SEL, 0x1);
664
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1,
665
+					      GENMASK(sensor->lanes - 1, 0));
666
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
667
+			} else if (hw->drv_data->chip_id == CHIP_ID_RK3562) {
668
+				write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
669
+				write_grf_reg(hw, GRF_DPHY1_CSI2PHY_DATALANE_EN1,
670
+					      GENMASK(sensor->lanes - 1, 0));
671
+				write_grf_reg(hw, GRF_DPHY1_CSI2PHY_CLKLANE1_EN, 0x1);
672
+			}
673
+			break;
674
+		default:
675
+			break;
676
+		};
372677 	}
373678 }
374679 
....@@ -376,13 +681,20 @@
376681 					struct v4l2_subdev *sd)
377682 {
378683 	struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
379
-	struct csi2_sensor *sensor = sd_to_sensor(dphy, sensor_sd);
684
+	struct csi2_sensor *sensor;
380685 	struct csi2_dphy_hw *hw = dphy->dphy_hw;
381686 	const struct dphy_hw_drv_data *drv_data = hw->drv_data;
382687 	const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
383688 	int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
384689 	int i, hsfreq = 0;
385690 	u32 val = 0, pre_val;
691
+	u8 lvds_width = 0;
692
+
693
+	if (!sensor_sd)
694
+		return -ENODEV;
695
+	sensor = sd_to_sensor(dphy, sensor_sd);
696
+	if (!sensor)
697
+		return -ENODEV;
386698 
387699 	mutex_lock(&hw->mutex);
388700 
....@@ -401,31 +713,32 @@
401713 		if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)))
402714 			val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
403715 
404
-		if (dphy->phy_index == DPHY1)
716
+		if (dphy->phy_index % 3 == DPHY1)
405717 			val |= (GENMASK(sensor->lanes - 1, 0) <<
406718 				CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT);
407719 
408
-		if (dphy->phy_index == DPHY2)
720
+		if (dphy->phy_index % 3 == DPHY2) {
409721 			val |= (GENMASK(sensor->lanes - 1, 0) <<
410722 				CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT);
723
+			if (hw->drv_data->chip_id >= CHIP_ID_RK3588)
724
+				write_csi2_dphy_reg(hw, CSI2PHY_CLK1_LANE_ENABLE, BIT(6));
725
+		}
411726 	}
412727 	val |= pre_val;
413728 	write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, val);
414729 
415
-	if (sensor->mbus.type == V4L2_MBUS_CSI2) {
416
-		/* Reset dphy digital part */
417
-		if (hw->lane_mode == LANE_MODE_FULL) {
418
-			write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1e);
419
-			write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1f);
420
-		} else {
421
-			read_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, &val);
422
-			if (!(val & CSI2_DPHY_LANE_DUAL_MODE_EN)) {
423
-				write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5e);
424
-				write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
425
-			}
730
+	/* Reset dphy digital part */
731
+	if (hw->lane_mode == LANE_MODE_FULL) {
732
+		write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1e);
733
+		write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1f);
734
+	} else {
735
+		read_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, &val);
736
+		if (!(val & CSI2_DPHY_LANE_DUAL_MODE_EN)) {
737
+			write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5e);
738
+			write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
426739 		}
427
-		csi2_dphy_config_dual_mode(dphy, sensor);
428740 	}
741
+	csi2_dphy_config_dual_mode(dphy, sensor);
429742 
430743 	/* not into receive mode/wait stopstate */
431744 	write_grf_reg(hw, GRF_DPHY_CSI2PHY_FORCERXMODE, 0x0);
....@@ -443,7 +756,7 @@
443756 			if (sensor->lanes > 0x03)
444757 				write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
445758 		} else {
446
-			if (dphy->phy_index == DPHY1) {
759
+			if (dphy->phy_index % 3 == DPHY1) {
447760 				write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
448761 				if (sensor->lanes > 0x00)
449762 					write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
....@@ -451,7 +764,7 @@
451764 					write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
452765 			}
453766 
454
-			if (dphy->phy_index == DPHY2) {
767
+			if (dphy->phy_index % 3 == DPHY2) {
455768 				write_csi2_dphy_reg(hw, CSI2PHY_CLK1_CALIB_ENABLE, 0x80);
456769 				if (sensor->lanes > 0x00)
457770 					write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
....@@ -487,16 +800,43 @@
487800 		if (sensor->lanes > 0x03)
488801 			csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
489802 	} else {
490
-		if (dphy->phy_index == DPHY1) {
803
+		if (dphy->phy_index % 3 == DPHY1) {
491804 			csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
492805 			csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
493806 			csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
494807 		}
495808 
496
-		if (dphy->phy_index == DPHY2) {
809
+		if (dphy->phy_index % 3 == DPHY2) {
497810 			csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK1);
498811 			csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
499812 			csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
813
+		}
814
+	}
815
+
816
+	if (hw->drv_data->chip_id == CHIP_ID_RV1106) {
817
+		if (dphy->phy_index % 3 == DPHY0 ||
818
+		    dphy->phy_index % 3 == DPHY1) {
819
+			if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
820
+				write_csi2_dphy_reg(hw, CSI2PHY_PATH0_MODEL, 0x2);
821
+			} else {
822
+				write_csi2_dphy_reg(hw, CSI2PHY_PATH0_MODEL, 0x4);
823
+				lvds_width = get_lvds_data_width(sensor->format.code);
824
+				write_csi2_dphy_reg(hw, CSI2PHY_PATH0_LVDS_MODEL, (lvds_width << 4) | 0X0f);
825
+			}
826
+		} else {
827
+			if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
828
+				write_csi2_dphy_reg(hw, CSI2PHY_PATH1_MODEL, 0x2);
829
+			} else {
830
+				write_csi2_dphy_reg(hw, CSI2PHY_PATH1_MODEL, 0x4);
831
+				lvds_width = get_lvds_data_width(sensor->format.code);
832
+				write_csi2_dphy_reg(hw, CSI2PHY_PATH1_LVDS_MODEL, (lvds_width << 4) | 0X0f);
833
+			}
834
+		}
835
+		if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
836
+			if (hw->lane_mode == LANE_MODE_FULL)
837
+				write_csi2_dphy_reg(hw, CSI2PHY_CLK_INV, 0x04);
838
+			else
839
+				write_csi2_dphy_reg(hw, CSI2PHY_CLK_INV, 0x14);
500840 		}
501841 	}
502842 
....@@ -518,6 +858,7 @@
518858 	mutex_lock(&hw->mutex);
519859 
520860 	write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x01);
861
+	csi2_dphy_hw_do_reset(hw);
521862 	usleep_range(500, 1000);
522863 
523864 	mutex_unlock(&hw->mutex);
....@@ -525,26 +866,109 @@
525866 	return 0;
526867 }
527868 
869
+static int csi2_dphy_hw_ttl_mode_enable(struct csi2_dphy_hw *hw)
870
+{
871
+	int ret = 0;
872
+
873
+	ret = clk_bulk_prepare_enable(hw->num_clks, hw->clks_bulk);
874
+	if (ret) {
875
+		dev_err(hw->dev, "failed to enable clks\n");
876
+		return ret;
877
+	}
878
+
879
+	write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x7d);
880
+	write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
881
+	write_csi2_dphy_reg(hw, CSI2PHY_PATH0_MODEL, 0x1);
882
+	write_csi2_dphy_reg(hw, CSI2PHY_PATH1_MODEL, 0x1);
883
+	return ret;
884
+}
885
+
886
+static void csi2_dphy_hw_ttl_mode_disable(struct csi2_dphy_hw *hw)
887
+{
888
+	write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x01);
889
+	clk_bulk_disable_unprepare(hw->num_clks, hw->clks_bulk);
890
+}
891
+
528892 static void rk3568_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
529893 {
530894 	hw->grf_regs = rk3568_grf_dphy_regs;
531895 }
532896 
897
+static void rk3588_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
898
+{
899
+	hw->grf_regs = rk3588_grf_dphy_regs;
900
+}
901
+
902
+static void rv1106_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
903
+{
904
+	hw->grf_regs = rv1106_grf_dphy_regs;
905
+}
906
+
907
+static void rk3562_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
908
+{
909
+	hw->grf_regs = rk3562_grf_dphy_regs;
910
+}
911
+
533912 static const struct dphy_hw_drv_data rk3568_csi2_dphy_hw_drv_data = {
534
-	.clks = rk3568_csi2_dphy_hw_clks,
535
-	.num_clks = ARRAY_SIZE(rk3568_csi2_dphy_hw_clks),
536913 	.hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
537914 	.num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
538915 	.csi2dphy_regs = rk3568_csi2dphy_regs,
539916 	.grf_regs = rk3568_grf_dphy_regs,
540917 	.individual_init = rk3568_csi2_dphy_hw_individual_init,
541918 	.chip_id = CHIP_ID_RK3568,
919
+	.stream_on = csi2_dphy_hw_stream_on,
920
+	.stream_off = csi2_dphy_hw_stream_off,
921
+};
922
+
923
+static const struct dphy_hw_drv_data rk3588_csi2_dphy_hw_drv_data = {
924
+	.hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
925
+	.num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
926
+	.csi2dphy_regs = rk3588_csi2dphy_regs,
927
+	.grf_regs = rk3588_grf_dphy_regs,
928
+	.individual_init = rk3588_csi2_dphy_hw_individual_init,
929
+	.chip_id = CHIP_ID_RK3588,
930
+	.stream_on = csi2_dphy_hw_stream_on,
931
+	.stream_off = csi2_dphy_hw_stream_off,
932
+};
933
+
934
+static const struct dphy_hw_drv_data rv1106_csi2_dphy_hw_drv_data = {
935
+	.hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
936
+	.num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
937
+	.csi2dphy_regs = rv1106_csi2dphy_regs,
938
+	.grf_regs = rv1106_grf_dphy_regs,
939
+	.individual_init = rv1106_csi2_dphy_hw_individual_init,
940
+	.chip_id = CHIP_ID_RV1106,
941
+	.stream_on = csi2_dphy_hw_stream_on,
942
+	.stream_off = csi2_dphy_hw_stream_off,
943
+};
944
+
945
+static const struct dphy_hw_drv_data rk3562_csi2_dphy_hw_drv_data = {
946
+	.hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
947
+	.num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
948
+	.csi2dphy_regs = rk3562_csi2dphy_regs,
949
+	.grf_regs = rk3562_grf_dphy_regs,
950
+	.individual_init = rk3562_csi2_dphy_hw_individual_init,
951
+	.chip_id = CHIP_ID_RK3562,
952
+	.stream_on = csi2_dphy_hw_stream_on,
953
+	.stream_off = csi2_dphy_hw_stream_off,
542954 };
543955 
544956 static const struct of_device_id rockchip_csi2_dphy_hw_match_id[] = {
545957 	{
546958 		.compatible = "rockchip,rk3568-csi2-dphy-hw",
547959 		.data = &rk3568_csi2_dphy_hw_drv_data,
960
+	},
961
+	{
962
+		.compatible = "rockchip,rk3588-csi2-dphy-hw",
963
+		.data = &rk3588_csi2_dphy_hw_drv_data,
964
+	},
965
+	{
966
+		.compatible = "rockchip,rv1106-csi2-dphy-hw",
967
+		.data = &rv1106_csi2_dphy_hw_drv_data,
968
+	},
969
+	{
970
+		.compatible = "rockchip,rk3562-csi2-dphy-hw",
971
+		.data = &rk3562_csi2_dphy_hw_drv_data,
548972 	},
549973 	{}
550974 };
....@@ -558,7 +982,6 @@
558982 	struct resource *res;
559983 	const struct of_device_id *of_id;
560984 	const struct dphy_hw_drv_data *drv_data;
561
-	int ret;
562985 
563986 	dphy_hw = devm_kzalloc(dev, sizeof(*dphy_hw), GFP_KERNEL);
564987 	if (!dphy_hw)
....@@ -569,33 +992,33 @@
569992 	if (!of_id)
570993 		return -EINVAL;
571994 
572
-	grf = syscon_node_to_regmap(dev->parent->of_node);
995
+	drv_data = of_id->data;
996
+
997
+	grf = syscon_regmap_lookup_by_phandle(dev->of_node,
998
+					      "rockchip,grf");
573999 	if (IS_ERR(grf)) {
574
-		grf = syscon_regmap_lookup_by_phandle(dev->of_node,
575
-						      "rockchip,grf");
576
-		if (IS_ERR(grf)) {
577
-			dev_err(dev, "Can't find GRF syscon\n");
578
-			return -ENODEV;
579
-		}
1000
+		dev_err(dev, "Can't find GRF syscon\n");
1001
+		return -ENODEV;
5801002 	}
5811003 	dphy_hw->regmap_grf = grf;
5821004 
583
-	drv_data = of_id->data;
584
-	dphy_hw->num_clks = drv_data->num_clks;
585
-	dphy_hw->clks = devm_kmemdup(dev, drv_data->clks,
586
-				     drv_data->num_clks * sizeof(struct clk_bulk_data),
587
-				     GFP_KERNEL);
588
-	if (!dphy_hw->clks) {
589
-		dev_err(dev, "failed to acquire csi2 dphy clks mem\n");
590
-		return -ENOMEM;
1005
+	if (drv_data->chip_id == CHIP_ID_RK3588) {
1006
+		grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1007
+						      "rockchip,sys_grf");
1008
+		if (IS_ERR(grf)) {
1009
+			dev_err(dev, "Can't find SYS GRF syscon\n");
1010
+			return -ENODEV;
1011
+		}
1012
+		dphy_hw->regmap_sys_grf = grf;
5911013 	}
592
-	ret = devm_clk_bulk_get(dev, dphy_hw->num_clks, dphy_hw->clks);
593
-	if (ret == -EPROBE_DEFER) {
594
-		dev_err(dev, "get csi2 dphy clks failed\n");
595
-		return -EPROBE_DEFER;
596
-	}
597
-	if (ret)
598
-		dphy_hw->num_clks = 0;
1014
+
1015
+	dphy_hw->num_clks = devm_clk_bulk_get_all(dev, &dphy_hw->clks_bulk);
1016
+	if (dphy_hw->num_clks < 0)
1017
+		dev_err(dev, "failed to get csi2 clks\n");
1018
+
1019
+	dphy_hw->rsts_bulk = devm_reset_control_array_get_optional_exclusive(dev);
1020
+	if (IS_ERR(dphy_hw->rsts_bulk))
1021
+		dev_err_probe(dev, PTR_ERR(dphy_hw->rsts_bulk), "failed to get dphy reset\n");
5991022 
6001023 	dphy_hw->dphy_dev_num = 0;
6011024 	dphy_hw->drv_data = drv_data;
....@@ -616,8 +1039,16 @@
6161039 			return -ENODEV;
6171040 		}
6181041 	}
619
-	dphy_hw->stream_on = csi2_dphy_hw_stream_on;
620
-	dphy_hw->stream_off = csi2_dphy_hw_stream_off;
1042
+	dphy_hw->stream_on = drv_data->stream_on;
1043
+	dphy_hw->stream_off = drv_data->stream_off;
1044
+
1045
+	if (drv_data->chip_id == CHIP_ID_RV1106) {
1046
+		dphy_hw->ttl_mode_enable = csi2_dphy_hw_ttl_mode_enable;
1047
+		dphy_hw->ttl_mode_disable = csi2_dphy_hw_ttl_mode_disable;
1048
+	} else {
1049
+		dphy_hw->ttl_mode_enable = NULL;
1050
+		dphy_hw->ttl_mode_disable = NULL;
1051
+	}
6211052 
6221053 	atomic_set(&dphy_hw->stream_cnt, 0);
6231054 
....@@ -626,8 +1057,6 @@
6261057 	platform_set_drvdata(pdev, dphy_hw);
6271058 
6281059 	pm_runtime_enable(&pdev->dev);
629
-
630
-	platform_driver_register(&rockchip_csi2_dphy_driver);
6311060 
6321061 	dev_info(dev, "csi2 dphy hw probe successfully!\n");
6331062 
....@@ -652,7 +1081,19 @@
6521081 		.of_match_table = rockchip_csi2_dphy_hw_match_id,
6531082 	},
6541083 };
1084
+
1085
+int rockchip_csi2_dphy_hw_init(void)
1086
+{
1087
+	return platform_driver_register(&rockchip_csi2_dphy_hw_driver);
1088
+}
1089
+
1090
+#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1091
+subsys_initcall(rockchip_csi2_dphy_hw_init);
1092
+#else
1093
+#if !defined(CONFIG_VIDEO_REVERSE_IMAGE)
6551094 module_platform_driver(rockchip_csi2_dphy_hw_driver);
1095
+#endif
1096
+#endif
6561097 
6571098 MODULE_AUTHOR("Rockchip Camera/ISP team");
6581099 MODULE_DESCRIPTION("Rockchip MIPI CSI2 DPHY HW driver");