enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/pci/controller/pcie-rockchip-ep.c
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@@ -22,6 +22,7 @@
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 /**
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  * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
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  * @rockchip: Rockchip PCIe controller
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+ * @epc: PCI EPC device
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  * @max_regions: maximum number of regions supported by hardware
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  * @ob_region_map: bitmask of mapped outbound regions
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  * @ob_addr: base addresses in the AXI bus where the outbound regions start
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@@ -263,8 +264,7 @@
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 	struct rockchip_pcie *pcie = &ep->rockchip;
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 	u32 r;
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-	r = find_first_zero_bit(&ep->ob_region_map,
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-				sizeof(ep->ob_region_map) * BITS_PER_LONG);
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+	r = find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG);
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 	/*
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 	 * Region 0 is reserved for configuration space and shouldn't
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 	 * be used elsewhere per TRM, so leave it out.
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@@ -499,10 +499,19 @@
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 	rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG);
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-	list_for_each_entry(epf, &epc->pci_epf, list)
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-		pci_epf_linkup(epf);
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-
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 	return 0;
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+}
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+
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+static const struct pci_epc_features rockchip_pcie_epc_features = {
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+	.linkup_notifier = false,
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+	.msi_capable = true,
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+	.msix_capable = false,
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+};
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+
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+static const struct pci_epc_features*
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+rockchip_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
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+{
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+	return &rockchip_pcie_epc_features;
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 }
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 static const struct pci_epc_ops rockchip_pcie_epc_ops = {
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@@ -515,6 +524,7 @@
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 	.get_msi	= rockchip_pcie_ep_get_msi,
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 	.raise_irq	= rockchip_pcie_ep_raise_irq,
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 	.start		= rockchip_pcie_ep_start,
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+	.get_features	= rockchip_pcie_ep_get_features,
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 };
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 static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip,
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@@ -605,7 +615,7 @@
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 	rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
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 	err = pci_epc_mem_init(epc, rockchip->mem_res->start,
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-			       resource_size(rockchip->mem_res));
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+			       resource_size(rockchip->mem_res), PAGE_SIZE);
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 	if (err < 0) {
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 		dev_err(dev, "failed to initialize the memory space\n");
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 		goto err_uninit_port;