enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
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@@ -1,4 +1,4 @@
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-// SPDX-License-Identifier: GPL-2.0+
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+/* SPDX-License-Identifier: GPL-2.0+ */
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 // Copyright (c) 2016-2017 Hisilicon Limited.
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 #ifndef __HCLGE_TM_H
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@@ -12,12 +12,14 @@
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 #define HCLGE_TM_PORT_BASE_MODE_MSK	BIT(0)
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-#define HCLGE_DEFAULT_PAUSE_TRANS_GAP	0xFF
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+#define HCLGE_DEFAULT_PAUSE_TRANS_GAP	0x7F
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 #define HCLGE_DEFAULT_PAUSE_TRANS_TIME	0xFFFF
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 /* SP or DWRR */
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 #define HCLGE_TM_TX_SCHD_DWRR_MSK	BIT(0)
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 #define HCLGE_TM_TX_SCHD_SP_MSK		(0xFE)
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+
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+#define HCLGE_ETHER_MAX_RATE	100000
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 struct hclge_pg_to_pri_link_cmd {
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 	u8 pg_id;
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@@ -40,6 +42,13 @@
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 	__le16 qset_id;
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 };
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+struct hclge_tqp_tx_queue_tc_cmd {
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+	__le16 queue_id;
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+	__le16 rsvd;
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+	u8 tc_id;
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+	u8 rev[3];
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+};
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+
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 struct hclge_pg_weight_cmd {
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 	u8 pg_id;
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 	u8 dwrr;
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@@ -53,6 +62,12 @@
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 struct hclge_qs_weight_cmd {
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 	__le16 qs_id;
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 	u8 dwrr;
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+};
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+
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+struct hclge_ets_tc_weight_cmd {
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+	u8 tc_weight[HNAE3_MAX_TC];
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+	u8 weight_offset;
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+	u8 rsvd[15];
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 };
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 #define HCLGE_TM_SHAP_IR_B_MSK  GENMASK(7, 0)
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@@ -83,6 +98,12 @@
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 	__le32 pg_shapping_para;
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 };
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+struct hclge_qs_shapping_cmd {
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+	__le16 qs_id;
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+	u8 rsvd[2];
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+	__le32 qs_shapping_para;
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+};
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+
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 #define HCLGE_BP_GRP_NUM		32
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 #define HCLGE_BP_SUB_GRP_ID_S		0
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 #define HCLGE_BP_SUB_GRP_ID_M		GENMASK(4, 0)
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@@ -106,6 +127,10 @@
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 	u8 pause_trans_gap;
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 	u8 rsvd;
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 	__le16 pause_trans_time;
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+	u8 rsvd1[6];
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+	/* extra mac address to do double check for pause frame */
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+	u8 mac_addr_extra[ETH_ALEN];
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+	u16 rsvd2;
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 };
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 struct hclge_pfc_stats_cmd {
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@@ -114,6 +139,12 @@
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 struct hclge_port_shapping_cmd {
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 	__le32 port_shapping_para;
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+};
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+
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+struct hclge_shaper_ir_para {
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+	u8 ir_b; /* IR_B parameter of IR shaper */
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+	u8 ir_u; /* IR_U parameter of IR shaper */
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+	u8 ir_s; /* IR_S parameter of IR shaper */
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 };
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 #define hclge_tm_set_field(dest, string, val) \
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@@ -125,15 +156,18 @@
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 				       (HCLGE_TM_SHAP_##string##_LSH))
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 int hclge_tm_schd_init(struct hclge_dev *hdev);
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-int hclge_pause_setup_hw(struct hclge_dev *hdev);
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-int hclge_tm_schd_mode_hw(struct hclge_dev *hdev);
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-int hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc);
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+int hclge_tm_vport_map_update(struct hclge_dev *hdev);
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+int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init);
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+int hclge_tm_schd_setup_hw(struct hclge_dev *hdev);
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+void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc);
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 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc);
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+void hclge_tm_pfc_info_update(struct hclge_dev *hdev);
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 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);
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-int hclge_tm_map_cfg(struct hclge_dev *hdev);
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-int hclge_tm_init_hw(struct hclge_dev *hdev);
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+int hclge_tm_init_hw(struct hclge_dev *hdev, bool init);
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 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx);
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 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
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 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);
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 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats);
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+int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate);
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+
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 #endif