enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/net/ethernet/chelsio/cxgb/subr.c
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@@ -170,7 +170,7 @@
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 	t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
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 }
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-static int t1_pci_intr_handler(adapter_t *adapter)
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+static bool t1_pci_intr_handler(adapter_t *adapter)
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 {
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 	u32 pcix_cause;
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..
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@@ -179,9 +179,13 @@
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 	if (pcix_cause) {
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 		pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
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 				       pcix_cause);
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-		t1_fatal_err(adapter);    /* PCI errors are fatal */
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+		/* PCI errors are fatal */
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+		t1_interrupts_disable(adapter);
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+		adapter->pending_thread_intr |= F_PL_INTR_SGE_ERR;
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+		pr_alert("%s: PCI error encountered.\n", adapter->name);
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+		return true;
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 	}
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-	return 0;
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+	return false;
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 }
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 #ifdef CONFIG_CHELSIO_T1_1G
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@@ -210,13 +214,16 @@
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 /*
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  * Slow path interrupt handler for FPGAs.
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  */
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-static int fpga_slow_intr(adapter_t *adapter)
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+static irqreturn_t fpga_slow_intr(adapter_t *adapter)
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 {
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 	u32 cause = readl(adapter->regs + A_PL_CAUSE);
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+	irqreturn_t ret = IRQ_NONE;
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221
 
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 	cause &= ~F_PL_INTR_SGE_DATA;
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-	if (cause & F_PL_INTR_SGE_ERR)
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-		t1_sge_intr_error_handler(adapter->sge);
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+	if (cause & F_PL_INTR_SGE_ERR) {
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+		if (t1_sge_intr_error_handler(adapter->sge))
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+			ret = IRQ_WAKE_THREAD;
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+	}
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 	if (cause & FPGA_PCIX_INTERRUPT_GMAC)
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 		fpga_phy_intr_handler(adapter);
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@@ -231,14 +238,19 @@
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 		/* Clear TP interrupt */
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 		writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
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 	}
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-	if (cause & FPGA_PCIX_INTERRUPT_PCIX)
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-		t1_pci_intr_handler(adapter);
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+	if (cause & FPGA_PCIX_INTERRUPT_PCIX) {
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+		if (t1_pci_intr_handler(adapter))
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+			ret = IRQ_WAKE_THREAD;
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+	}
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 	/* Clear the interrupts just processed. */
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 	if (cause)
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 		writel(cause, adapter->regs + A_PL_CAUSE);
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-	return cause != 0;
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+	if (ret != IRQ_NONE)
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+		return ret;
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+
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+	return cause == 0 ? IRQ_NONE : IRQ_HANDLED;
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 }
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 #endif
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@@ -842,31 +854,45 @@
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 /*
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  * Slow path interrupt handler for ASICs.
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  */
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-static int asic_slow_intr(adapter_t *adapter)
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+static irqreturn_t asic_slow_intr(adapter_t *adapter)
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 {
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 	u32 cause = readl(adapter->regs + A_PL_CAUSE);
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+	irqreturn_t ret = IRQ_HANDLED;
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 	cause &= adapter->slow_intr_mask;
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 	if (!cause)
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-		return 0;
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-	if (cause & F_PL_INTR_SGE_ERR)
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-		t1_sge_intr_error_handler(adapter->sge);
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+		return IRQ_NONE;
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+	if (cause & F_PL_INTR_SGE_ERR) {
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+		if (t1_sge_intr_error_handler(adapter->sge))
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+			ret = IRQ_WAKE_THREAD;
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+	}
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 	if (cause & F_PL_INTR_TP)
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 		t1_tp_intr_handler(adapter->tp);
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 	if (cause & F_PL_INTR_ESPI)
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 		t1_espi_intr_handler(adapter->espi);
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-	if (cause & F_PL_INTR_PCIX)
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-		t1_pci_intr_handler(adapter);
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-	if (cause & F_PL_INTR_EXT)
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-		t1_elmer0_ext_intr(adapter);
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+	if (cause & F_PL_INTR_PCIX) {
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+		if (t1_pci_intr_handler(adapter))
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+			ret = IRQ_WAKE_THREAD;
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+	}
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+	if (cause & F_PL_INTR_EXT) {
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+		/* Wake the threaded interrupt to handle external interrupts as
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+		 * we require a process context. We disable EXT interrupts in
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+		 * the interim and let the thread reenable them when it's done.
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+		 */
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+		adapter->pending_thread_intr |= F_PL_INTR_EXT;
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+		adapter->slow_intr_mask &= ~F_PL_INTR_EXT;
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+		writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,
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+		       adapter->regs + A_PL_ENABLE);
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+		ret = IRQ_WAKE_THREAD;
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+	}
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 	/* Clear the interrupts just processed. */
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 	writel(cause, adapter->regs + A_PL_CAUSE);
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 	readl(adapter->regs + A_PL_CAUSE); /* flush writes */
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-	return 1;
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+	return ret;
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 }
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-int t1_slow_intr_handler(adapter_t *adapter)
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+irqreturn_t t1_slow_intr_handler(adapter_t *adapter)
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 {
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 #ifdef CONFIG_CHELSIO_T1_1G
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 	if (!t1_is_asic(adapter))