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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/net/dsa/mv88e6xxx/global1.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Marvell 88E6xxx Switch Global (1) Registers support
34  *
....@@ -5,11 +6,6 @@
56  *
67  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
78  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
8
- *
9
- * This program is free software; you can redistribute it and/or modify
10
- * it under the terms of the GNU General Public License as published by
11
- * the Free Software Foundation; either version 2 of the License, or
12
- * (at your option) any later version.
139  */
1410 
1511 #include <linux/bitfield.h>
....@@ -31,100 +27,83 @@
3127 	return mv88e6xxx_write(chip, addr, reg, val);
3228 }
3329 
34
-int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
30
+int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
31
+			  bit, int val)
3532 {
36
-	return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask);
33
+	return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,
34
+				  bit, val);
35
+}
36
+
37
+int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
38
+			   u16 mask, u16 val)
39
+{
40
+	return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,
41
+				   mask, val);
3742 }
3843 
3944 /* Offset 0x00: Switch Global Status Register */
4045 
4146 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
4247 {
43
-	u16 state;
44
-	int i, err;
45
-
46
-	for (i = 0; i < 16; i++) {
47
-		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
48
-		if (err)
49
-			return err;
50
-
51
-		/* Check the value of the PPUState bits 15:14 */
52
-		state &= MV88E6185_G1_STS_PPU_STATE_MASK;
53
-		if (state != MV88E6185_G1_STS_PPU_STATE_POLLING)
54
-			return 0;
55
-
56
-		usleep_range(1000, 2000);
57
-	}
58
-
59
-	return -ETIMEDOUT;
48
+	return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
49
+				      MV88E6185_G1_STS_PPU_STATE_MASK,
50
+				      MV88E6185_G1_STS_PPU_STATE_DISABLED);
6051 }
6152 
6253 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
6354 {
64
-	u16 state;
65
-	int i, err;
66
-
67
-	for (i = 0; i < 16; ++i) {
68
-		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
69
-		if (err)
70
-			return err;
71
-
72
-		/* Check the value of the PPUState bits 15:14 */
73
-		state &= MV88E6185_G1_STS_PPU_STATE_MASK;
74
-		if (state == MV88E6185_G1_STS_PPU_STATE_POLLING)
75
-			return 0;
76
-
77
-		usleep_range(1000, 2000);
78
-	}
79
-
80
-	return -ETIMEDOUT;
55
+	return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
56
+				      MV88E6185_G1_STS_PPU_STATE_MASK,
57
+				      MV88E6185_G1_STS_PPU_STATE_POLLING);
8158 }
8259 
8360 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
8461 {
85
-	u16 state;
86
-	int i, err;
62
+	int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE);
8763 
88
-	for (i = 0; i < 16; ++i) {
89
-		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
90
-		if (err)
91
-			return err;
92
-
93
-		/* Check the value of the PPUState (or InitState) bit 15 */
94
-		if (state & MV88E6352_G1_STS_PPU_STATE)
95
-			return 0;
96
-
97
-		usleep_range(1000, 2000);
98
-	}
99
-
100
-	return -ETIMEDOUT;
64
+	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
10165 }
10266 
10367 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
10468 {
105
-	const unsigned long timeout = jiffies + 1 * HZ;
106
-	u16 val;
107
-	int err;
69
+	int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY);
10870 
10971 	/* Wait up to 1 second for the switch to be ready. The InitReady bit 11
11072 	 * is set to a one when all units inside the device (ATU, VTU, etc.)
11173 	 * have finished their initialization and are ready to accept frames.
11274 	 */
75
+	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
76
+}
77
+
78
+void mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip)
79
+{
80
+	const unsigned long timeout = jiffies + 1 * HZ;
81
+	u16 val;
82
+	int err;
83
+
84
+	/* Wait up to 1 second for the switch to finish reading the
85
+	 * EEPROM.
86
+	 */
11387 	while (time_before(jiffies, timeout)) {
11488 		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val);
115
-		if (err)
116
-			return err;
89
+		if (err) {
90
+			dev_err(chip->dev, "Error reading status");
91
+			return;
92
+		}
11793 
118
-		if (val & MV88E6XXX_G1_STS_INIT_READY)
119
-			break;
94
+		/* If the switch is still resetting, it may not
95
+		 * respond on the bus, and so MDIO read returns
96
+		 * 0xffff. Differentiate between that, and waiting for
97
+		 * the EEPROM to be done by bit 0 being set.
98
+		 */
99
+		if (val != 0xffff &&
100
+		    val & BIT(MV88E6XXX_G1_STS_IRQ_EEPROM_DONE))
101
+			return;
120102 
121103 		usleep_range(1000, 2000);
122104 	}
123105 
124
-	if (time_after(jiffies, timeout))
125
-		return -ETIMEDOUT;
126
-
127
-	return 0;
106
+	dev_err(chip->dev, "Timeout waiting for EEPROM done");
128107 }
129108 
130109 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
....@@ -182,7 +161,7 @@
182161 	return mv88e6185_g1_wait_ppu_polling(chip);
183162 }
184163 
185
-int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
164
+int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip)
186165 {
187166 	u16 val;
188167 	int err;
....@@ -198,7 +177,14 @@
198177 	if (err)
199178 		return err;
200179 
201
-	err = mv88e6xxx_g1_wait_init_ready(chip);
180
+	return mv88e6xxx_g1_wait_init_ready(chip);
181
+}
182
+
183
+int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
184
+{
185
+	int err;
186
+
187
+	err = mv88e6250_g1_reset(chip);
202188 	if (err)
203189 		return err;
204190 
....@@ -239,6 +225,25 @@
239225 		return err;
240226 
241227 	return mv88e6185_g1_wait_ppu_disabled(chip);
228
+}
229
+
230
+int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu)
231
+{
232
+	u16 val;
233
+	int err;
234
+
235
+	mtu += ETH_HLEN + ETH_FCS_LEN;
236
+
237
+	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
238
+	if (err)
239
+		return err;
240
+
241
+	val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632;
242
+
243
+	if (mtu > 1518)
244
+		val |= MV88E6185_G1_CTL1_MAX_FRAME_1632;
245
+
246
+	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
242247 }
243248 
244249 /* Offset 0x10: IP-PRI Mapping Register 0
....@@ -299,11 +304,20 @@
299304 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
300305 }
301306 
307
+int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
308
+{
309
+	/* Reset the IEEE Tag priorities to defaults */
310
+	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50);
311
+}
312
+
302313 /* Offset 0x1a: Monitor Control */
303314 /* Offset 0x1a: Monitor & MGMT Control on some devices */
304315 
305
-int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
316
+int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
317
+				 enum mv88e6xxx_egress_direction direction,
318
+				 int port)
306319 {
320
+	int *dest_port_chip;
307321 	u16 reg;
308322 	int err;
309323 
....@@ -311,13 +325,28 @@
311325 	if (err)
312326 		return err;
313327 
314
-	reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK |
315
-		 MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
328
+	switch (direction) {
329
+	case MV88E6XXX_EGRESS_DIR_INGRESS:
330
+		dest_port_chip = &chip->ingress_dest_port;
331
+		reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;
332
+		reg |= port <<
333
+		       __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);
334
+		break;
335
+	case MV88E6XXX_EGRESS_DIR_EGRESS:
336
+		dest_port_chip = &chip->egress_dest_port;
337
+		reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;
338
+		reg |= port <<
339
+		       __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
340
+		break;
341
+	default:
342
+		return -EINVAL;
343
+	}
316344 
317
-	reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) |
318
-		port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
345
+	err = mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
346
+	if (!err)
347
+		*dest_port_chip = port;
319348 
320
-	return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
349
+	return err;
321350 }
322351 
323352 /* Older generations also call this the ARP destination. It has been
....@@ -349,22 +378,32 @@
349378 	return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
350379 }
351380 
352
-int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
381
+int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
382
+				 enum mv88e6xxx_egress_direction direction,
383
+				 int port)
353384 {
385
+	int *dest_port_chip;
354386 	u16 ptr;
355387 	int err;
356388 
357
-	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
358
-	err = mv88e6390_g1_monitor_write(chip, ptr, port);
359
-	if (err)
360
-		return err;
389
+	switch (direction) {
390
+	case MV88E6XXX_EGRESS_DIR_INGRESS:
391
+		dest_port_chip = &chip->ingress_dest_port;
392
+		ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
393
+		break;
394
+	case MV88E6XXX_EGRESS_DIR_EGRESS:
395
+		dest_port_chip = &chip->egress_dest_port;
396
+		ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
397
+		break;
398
+	default:
399
+		return -EINVAL;
400
+	}
361401 
362
-	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
363402 	err = mv88e6390_g1_monitor_write(chip, ptr, port);
364
-	if (err)
365
-		return err;
403
+	if (!err)
404
+		*dest_port_chip = port;
366405 
367
-	return 0;
406
+	return err;
368407 }
369408 
370409 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
....@@ -384,26 +423,26 @@
384423 	u16 ptr;
385424 	int err;
386425 
387
-	/* 01:c2:80:00:00:00:00-01:c2:80:00:00:00:07 are Management */
388
-	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO;
426
+	/* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */
427
+	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO;
389428 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
390429 	if (err)
391430 		return err;
392431 
393
-	/* 01:c2:80:00:00:00:08-01:c2:80:00:00:00:0f are Management */
394
-	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI;
432
+	/* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */
433
+	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI;
395434 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
396435 	if (err)
397436 		return err;
398437 
399
-	/* 01:c2:80:00:00:00:20-01:c2:80:00:00:00:27 are Management */
400
-	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO;
438
+	/* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */
439
+	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO;
401440 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
402441 	if (err)
403442 		return err;
404443 
405
-	/* 01:c2:80:00:00:00:28-01:c2:80:00:00:00:2f are Management */
406
-	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI;
444
+	/* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */
445
+	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI;
407446 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
408447 	if (err)
409448 		return err;
....@@ -470,10 +509,11 @@
470509 
471510 /* Offset 0x1d: Statistics Operation 2 */
472511 
473
-int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
512
+static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
474513 {
475
-	return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP,
476
-				 MV88E6XXX_G1_STATS_OP_BUSY);
514
+	int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY);
515
+
516
+	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0);
477517 }
478518 
479519 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)