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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/mtd/nand/raw/denali.h
....@@ -1,22 +1,15 @@
1
+/* SPDX-License-Identifier: GPL-2.0 */
12 /*
23  * NAND Flash Controller Device Driver
34  * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
135  */
146 
157 #ifndef __DENALI_H__
168 #define __DENALI_H__
179 
18
-#include <linux/bitops.h>
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+#include <linux/bits.h>
1911 #include <linux/completion.h>
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+#include <linux/list.h>
2013 #include <linux/mtd/rawnand.h>
2114 #include <linux/spinlock_types.h>
2215 #include <linux/types.h>
....@@ -298,39 +291,108 @@
298291 #define     CHNL_ACTIVE__CHANNEL2			BIT(2)
299292 #define     CHNL_ACTIVE__CHANNEL3			BIT(3)
300293 
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-struct denali_nand_info {
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-	struct nand_chip nand;
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-	unsigned long clk_rate;		/* core clock rate */
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-	unsigned long clk_x_rate;	/* bus interface clock rate */
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-	int active_bank;		/* currently selected bank */
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+/**
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+ * struct denali_chip_sel - per-CS data of Denali NAND
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+ *
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+ * @bank:                  bank id of the controller this CS is connected to
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+ * @hwhr2_and_we_2_re:     value of timing register HWHR2_AND_WE_2_RE
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+ * @tcwaw_and_addr_2_data: value of timing register TCWAW_AND_ADDR_2_DATA
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+ * @re_2_we:               value of timing register RE_2_WE
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+ * @acc_clks:              value of timing register ACC_CLKS
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+ * @rdwr_en_lo_cnt:        value of timing register RDWR_EN_LO_CNT
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+ * @rdwr_en_hi_cnt:        value of timing register RDWR_EN_HI_CNT
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+ * @cs_setup_cnt:          value of timing register CS_SETUP_CNT
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+ * @re_2_re:               value of timing register RE_2_RE
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+ */
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+struct denali_chip_sel {
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+	int bank;
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+	u32 hwhr2_and_we_2_re;
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+	u32 tcwaw_and_addr_2_data;
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+	u32 re_2_we;
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+	u32 acc_clks;
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+	u32 rdwr_en_lo_cnt;
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+	u32 rdwr_en_hi_cnt;
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+	u32 cs_setup_cnt;
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+	u32 re_2_re;
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+};
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+
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+/**
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+ * struct denali_chip - per-chip data of Denali NAND
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+ *
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+ * @chip:  base NAND chip structure
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+ * @node:  node to be used to associate this chip with the controller
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+ * @nsels: the number of CS lines of this chip
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+ * @sels:  the array of per-cs data
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+ */
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+struct denali_chip {
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+	struct nand_chip chip;
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+	struct list_head node;
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+	unsigned int nsels;
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+	struct denali_chip_sel sels[];
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+};
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+
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+/**
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+ * struct denali_controller - Denali NAND controller data
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+ *
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+ * @controller:     base NAND controller structure
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+ * @dev:            device
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+ * @chips:          the list of chips attached to this controller
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+ * @clk_rate:       frequency of core clock
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+ * @clk_x_rate:     frequency of bus interface clock
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+ * @reg:            base of Register Interface
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+ * @host:           base of Host Data/Command interface
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+ * @complete:       completion used to wait for interrupts
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+ * @irq:            interrupt number
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+ * @irq_mask:       interrupt bits the controller is waiting for
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+ * @irq_status:     interrupt bits of events that have happened
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+ * @irq_lock:       lock to protect @irq_mask and @irq_status
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+ * @dma_avail:      set if DMA engine is available
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+ * @devs_per_cs:    number of devices connected in parallel
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+ * @oob_skip_bytes: number of bytes in OOB skipped by the ECC engine
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+ * @active_bank:    active bank id
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+ * @nbanks:         the number of banks supported by this controller
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+ * @revision:       IP revision
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+ * @caps:           controller capabilities that cannot be detected run-time
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+ * @ecc_caps:       ECC engine capabilities
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+ * @host_read:      callback for read access of Host Data/Command Interface
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+ * @host_write:     callback for write access of Host Data/Command Interface
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+ * @setup_dma:      callback for setup of the Data DMA
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+ */
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+struct denali_controller {
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+	struct nand_controller controller;
306363 	struct device *dev;
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-	void __iomem *reg;		/* Register Interface */
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-	void __iomem *host;		/* Host Data/Command Interface */
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+	struct list_head chips;
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+	unsigned long clk_rate;
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+	unsigned long clk_x_rate;
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+	void __iomem *reg;
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+	void __iomem *host;
309369 	struct completion complete;
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-	spinlock_t irq_lock;		/* protect irq_mask and irq_status */
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-	u32 irq_mask;			/* interrupts we are waiting for */
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-	u32 irq_status;			/* interrupts that have happened */
313370 	int irq;
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-	void *buf;			/* for syndrome layout conversion */
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-	dma_addr_t dma_addr;
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-	int dma_avail;			/* can support DMA? */
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-	int devs_per_cs;		/* devices connected in parallel */
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-	int oob_skip_bytes;		/* number of bytes reserved for BBM */
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-	int max_banks;
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-	unsigned int revision;		/* IP revision */
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-	unsigned int caps;		/* IP capability (or quirk) */
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+	u32 irq_mask;
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+	u32 irq_status;
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+	spinlock_t irq_lock;
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+	bool dma_avail;
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+	int devs_per_cs;
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+	int oob_skip_bytes;
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+	int active_bank;
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+	int nbanks;
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+	unsigned int revision;
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+	unsigned int caps;
322381 	const struct nand_ecc_caps *ecc_caps;
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-	u32 (*host_read)(struct denali_nand_info *denali, u32 addr);
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-	void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data);
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-	void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr,
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-			  int page, int write);
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+	u32 (*host_read)(struct denali_controller *denali, u32 addr);
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+	void (*host_write)(struct denali_controller *denali, u32 addr,
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+			   u32 data);
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+	void (*setup_dma)(struct denali_controller *denali, dma_addr_t dma_addr,
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+			  int page, bool write);
327387 };
328388 
329389 #define DENALI_CAP_HW_ECC_FIXUP			BIT(0)
330390 #define DENALI_CAP_DMA_64BIT			BIT(1)
331391 
332392 int denali_calc_ecc_bytes(int step_size, int strength);
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-int denali_init(struct denali_nand_info *denali);
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-void denali_remove(struct denali_nand_info *denali);
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+int denali_chip_init(struct denali_controller *denali,
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+		     struct denali_chip *dchip);
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+int denali_init(struct denali_controller *denali);
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+void denali_remove(struct denali_controller *denali);
335397 
336398 #endif /* __DENALI_H__ */