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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/mtd/nand/raw/au1550nd.c
....@@ -1,10 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  *  Copyright (C) 2004 Embedded Edge, LLC
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
7
- *
84  */
95 
106 #include <linux/slab.h>
....@@ -20,360 +16,101 @@
2016 
2117 
2218 struct au1550nd_ctx {
19
+	struct nand_controller controller;
2320 	struct nand_chip chip;
2421 
2522 	int cs;
2623 	void __iomem *base;
27
-	void (*write_byte)(struct mtd_info *, u_char);
2824 };
2925 
30
-/**
31
- * au_read_byte -  read one byte from the chip
32
- * @mtd:	MTD device structure
33
- *
34
- * read function for 8bit buswidth
35
- */
36
-static u_char au_read_byte(struct mtd_info *mtd)
26
+static struct au1550nd_ctx *chip_to_au_ctx(struct nand_chip *this)
3727 {
38
-	struct nand_chip *this = mtd_to_nand(mtd);
39
-	u_char ret = readb(this->IO_ADDR_R);
40
-	wmb(); /* drain writebuffer */
41
-	return ret;
42
-}
43
-
44
-/**
45
- * au_write_byte -  write one byte to the chip
46
- * @mtd:	MTD device structure
47
- * @byte:	pointer to data byte to write
48
- *
49
- * write function for 8it buswidth
50
- */
51
-static void au_write_byte(struct mtd_info *mtd, u_char byte)
52
-{
53
-	struct nand_chip *this = mtd_to_nand(mtd);
54
-	writeb(byte, this->IO_ADDR_W);
55
-	wmb(); /* drain writebuffer */
56
-}
57
-
58
-/**
59
- * au_read_byte16 -  read one byte endianness aware from the chip
60
- * @mtd:	MTD device structure
61
- *
62
- * read function for 16bit buswidth with endianness conversion
63
- */
64
-static u_char au_read_byte16(struct mtd_info *mtd)
65
-{
66
-	struct nand_chip *this = mtd_to_nand(mtd);
67
-	u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
68
-	wmb(); /* drain writebuffer */
69
-	return ret;
70
-}
71
-
72
-/**
73
- * au_write_byte16 -  write one byte endianness aware to the chip
74
- * @mtd:	MTD device structure
75
- * @byte:	pointer to data byte to write
76
- *
77
- * write function for 16bit buswidth with endianness conversion
78
- */
79
-static void au_write_byte16(struct mtd_info *mtd, u_char byte)
80
-{
81
-	struct nand_chip *this = mtd_to_nand(mtd);
82
-	writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
83
-	wmb(); /* drain writebuffer */
84
-}
85
-
86
-/**
87
- * au_read_word -  read one word from the chip
88
- * @mtd:	MTD device structure
89
- *
90
- * read function for 16bit buswidth without endianness conversion
91
- */
92
-static u16 au_read_word(struct mtd_info *mtd)
93
-{
94
-	struct nand_chip *this = mtd_to_nand(mtd);
95
-	u16 ret = readw(this->IO_ADDR_R);
96
-	wmb(); /* drain writebuffer */
97
-	return ret;
28
+	return container_of(this, struct au1550nd_ctx, chip);
9829 }
9930 
10031 /**
10132  * au_write_buf -  write buffer to chip
102
- * @mtd:	MTD device structure
33
+ * @this:	NAND chip object
10334  * @buf:	data buffer
10435  * @len:	number of bytes to write
10536  *
10637  * write function for 8bit buswidth
10738  */
108
-static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
39
+static void au_write_buf(struct nand_chip *this, const void *buf,
40
+			 unsigned int len)
10941 {
42
+	struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
43
+	const u8 *p = buf;
11044 	int i;
111
-	struct nand_chip *this = mtd_to_nand(mtd);
11245 
11346 	for (i = 0; i < len; i++) {
114
-		writeb(buf[i], this->IO_ADDR_W);
47
+		writeb(p[i], ctx->base + MEM_STNAND_DATA);
11548 		wmb(); /* drain writebuffer */
11649 	}
11750 }
11851 
11952 /**
12053  * au_read_buf -  read chip data into buffer
121
- * @mtd:	MTD device structure
54
+ * @this:	NAND chip object
12255  * @buf:	buffer to store date
12356  * @len:	number of bytes to read
12457  *
12558  * read function for 8bit buswidth
12659  */
127
-static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
60
+static void au_read_buf(struct nand_chip *this, void *buf,
61
+			unsigned int len)
12862 {
63
+	struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
64
+	u8 *p = buf;
12965 	int i;
130
-	struct nand_chip *this = mtd_to_nand(mtd);
13166 
13267 	for (i = 0; i < len; i++) {
133
-		buf[i] = readb(this->IO_ADDR_R);
68
+		p[i] = readb(ctx->base + MEM_STNAND_DATA);
13469 		wmb(); /* drain writebuffer */
13570 	}
13671 }
13772 
13873 /**
13974  * au_write_buf16 -  write buffer to chip
140
- * @mtd:	MTD device structure
75
+ * @this:	NAND chip object
14176  * @buf:	data buffer
14277  * @len:	number of bytes to write
14378  *
14479  * write function for 16bit buswidth
14580  */
146
-static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
81
+static void au_write_buf16(struct nand_chip *this, const void *buf,
82
+			   unsigned int len)
14783 {
148
-	int i;
149
-	struct nand_chip *this = mtd_to_nand(mtd);
150
-	u16 *p = (u16 *) buf;
151
-	len >>= 1;
84
+	struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
85
+	const u16 *p = buf;
86
+	unsigned int i;
15287 
88
+	len >>= 1;
15389 	for (i = 0; i < len; i++) {
154
-		writew(p[i], this->IO_ADDR_W);
90
+		writew(p[i], ctx->base + MEM_STNAND_DATA);
15591 		wmb(); /* drain writebuffer */
15692 	}
157
-
15893 }
15994 
16095 /**
16196  * au_read_buf16 -  read chip data into buffer
162
- * @mtd:	MTD device structure
97
+ * @this:	NAND chip object
16398  * @buf:	buffer to store date
16499  * @len:	number of bytes to read
165100  *
166101  * read function for 16bit buswidth
167102  */
168
-static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
103
+static void au_read_buf16(struct nand_chip *this, void *buf, unsigned int len)
169104 {
170
-	int i;
171
-	struct nand_chip *this = mtd_to_nand(mtd);
172
-	u16 *p = (u16 *) buf;
173
-	len >>= 1;
105
+	struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
106
+	unsigned int i;
107
+	u16 *p = buf;
174108 
109
+	len >>= 1;
175110 	for (i = 0; i < len; i++) {
176
-		p[i] = readw(this->IO_ADDR_R);
111
+		p[i] = readw(ctx->base + MEM_STNAND_DATA);
177112 		wmb(); /* drain writebuffer */
178113 	}
179
-}
180
-
181
-/* Select the chip by setting nCE to low */
182
-#define NAND_CTL_SETNCE		1
183
-/* Deselect the chip by setting nCE to high */
184
-#define NAND_CTL_CLRNCE		2
185
-/* Select the command latch by setting CLE to high */
186
-#define NAND_CTL_SETCLE		3
187
-/* Deselect the command latch by setting CLE to low */
188
-#define NAND_CTL_CLRCLE		4
189
-/* Select the address latch by setting ALE to high */
190
-#define NAND_CTL_SETALE		5
191
-/* Deselect the address latch by setting ALE to low */
192
-#define NAND_CTL_CLRALE		6
193
-
194
-static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
195
-{
196
-	struct nand_chip *this = mtd_to_nand(mtd);
197
-	struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
198
-						chip);
199
-
200
-	switch (cmd) {
201
-
202
-	case NAND_CTL_SETCLE:
203
-		this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
204
-		break;
205
-
206
-	case NAND_CTL_CLRCLE:
207
-		this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
208
-		break;
209
-
210
-	case NAND_CTL_SETALE:
211
-		this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
212
-		break;
213
-
214
-	case NAND_CTL_CLRALE:
215
-		this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
216
-		/* FIXME: Nobody knows why this is necessary,
217
-		 * but it works only that way */
218
-		udelay(1);
219
-		break;
220
-
221
-	case NAND_CTL_SETNCE:
222
-		/* assert (force assert) chip enable */
223
-		alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
224
-		break;
225
-
226
-	case NAND_CTL_CLRNCE:
227
-		/* deassert chip enable */
228
-		alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
229
-		break;
230
-	}
231
-
232
-	this->IO_ADDR_R = this->IO_ADDR_W;
233
-
234
-	wmb(); /* Drain the writebuffer */
235
-}
236
-
237
-int au1550_device_ready(struct mtd_info *mtd)
238
-{
239
-	return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
240
-}
241
-
242
-/**
243
- * au1550_select_chip - control -CE line
244
- *	Forbid driving -CE manually permitting the NAND controller to do this.
245
- *	Keeping -CE asserted during the whole sector reads interferes with the
246
- *	NOR flash and PCMCIA drivers as it causes contention on the static bus.
247
- *	We only have to hold -CE low for the NAND read commands since the flash
248
- *	chip needs it to be asserted during chip not ready time but the NAND
249
- *	controller keeps it released.
250
- *
251
- * @mtd:	MTD device structure
252
- * @chip:	chipnumber to select, -1 for deselect
253
- */
254
-static void au1550_select_chip(struct mtd_info *mtd, int chip)
255
-{
256
-}
257
-
258
-/**
259
- * au1550_command - Send command to NAND device
260
- * @mtd:	MTD device structure
261
- * @command:	the command to be sent
262
- * @column:	the column address for this command, -1 if none
263
- * @page_addr:	the page address for this command, -1 if none
264
- */
265
-static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
266
-{
267
-	struct nand_chip *this = mtd_to_nand(mtd);
268
-	struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
269
-						chip);
270
-	int ce_override = 0, i;
271
-	unsigned long flags = 0;
272
-
273
-	/* Begin command latch cycle */
274
-	au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
275
-	/*
276
-	 * Write out the command to the device.
277
-	 */
278
-	if (command == NAND_CMD_SEQIN) {
279
-		int readcmd;
280
-
281
-		if (column >= mtd->writesize) {
282
-			/* OOB area */
283
-			column -= mtd->writesize;
284
-			readcmd = NAND_CMD_READOOB;
285
-		} else if (column < 256) {
286
-			/* First 256 bytes --> READ0 */
287
-			readcmd = NAND_CMD_READ0;
288
-		} else {
289
-			column -= 256;
290
-			readcmd = NAND_CMD_READ1;
291
-		}
292
-		ctx->write_byte(mtd, readcmd);
293
-	}
294
-	ctx->write_byte(mtd, command);
295
-
296
-	/* Set ALE and clear CLE to start address cycle */
297
-	au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
298
-
299
-	if (column != -1 || page_addr != -1) {
300
-		au1550_hwcontrol(mtd, NAND_CTL_SETALE);
301
-
302
-		/* Serially input address */
303
-		if (column != -1) {
304
-			/* Adjust columns for 16 bit buswidth */
305
-			if (this->options & NAND_BUSWIDTH_16 &&
306
-					!nand_opcode_8bits(command))
307
-				column >>= 1;
308
-			ctx->write_byte(mtd, column);
309
-		}
310
-		if (page_addr != -1) {
311
-			ctx->write_byte(mtd, (u8)(page_addr & 0xff));
312
-
313
-			if (command == NAND_CMD_READ0 ||
314
-			    command == NAND_CMD_READ1 ||
315
-			    command == NAND_CMD_READOOB) {
316
-				/*
317
-				 * NAND controller will release -CE after
318
-				 * the last address byte is written, so we'll
319
-				 * have to forcibly assert it. No interrupts
320
-				 * are allowed while we do this as we don't
321
-				 * want the NOR flash or PCMCIA drivers to
322
-				 * steal our precious bytes of data...
323
-				 */
324
-				ce_override = 1;
325
-				local_irq_save(flags);
326
-				au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
327
-			}
328
-
329
-			ctx->write_byte(mtd, (u8)(page_addr >> 8));
330
-
331
-			if (this->options & NAND_ROW_ADDR_3)
332
-				ctx->write_byte(mtd,
333
-						((page_addr >> 16) & 0x0f));
334
-		}
335
-		/* Latch in address */
336
-		au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
337
-	}
338
-
339
-	/*
340
-	 * Program and erase have their own busy handlers.
341
-	 * Status and sequential in need no delay.
342
-	 */
343
-	switch (command) {
344
-
345
-	case NAND_CMD_PAGEPROG:
346
-	case NAND_CMD_ERASE1:
347
-	case NAND_CMD_ERASE2:
348
-	case NAND_CMD_SEQIN:
349
-	case NAND_CMD_STATUS:
350
-		return;
351
-
352
-	case NAND_CMD_RESET:
353
-		break;
354
-
355
-	case NAND_CMD_READ0:
356
-	case NAND_CMD_READ1:
357
-	case NAND_CMD_READOOB:
358
-		/* Check if we're really driving -CE low (just in case) */
359
-		if (unlikely(!ce_override))
360
-			break;
361
-
362
-		/* Apply a short delay always to ensure that we do wait tWB. */
363
-		ndelay(100);
364
-		/* Wait for a chip to become ready... */
365
-		for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
366
-			udelay(1);
367
-
368
-		/* Release -CE and re-enable interrupts. */
369
-		au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
370
-		local_irq_restore(flags);
371
-		return;
372
-	}
373
-	/* Apply this short delay always to ensure that we do wait tWB. */
374
-	ndelay(100);
375
-
376
-	while(!this->dev_ready(mtd));
377114 }
378115 
379116 static int find_nand_cs(unsigned long nand_base)
....@@ -396,6 +133,122 @@
396133 
397134 	return -ENODEV;
398135 }
136
+
137
+static int au1550nd_waitrdy(struct nand_chip *this, unsigned int timeout_ms)
138
+{
139
+	unsigned long timeout_jiffies = jiffies;
140
+
141
+	timeout_jiffies += msecs_to_jiffies(timeout_ms) + 1;
142
+	do {
143
+		if (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1)
144
+			return 0;
145
+
146
+		usleep_range(10, 100);
147
+	} while (time_before(jiffies, timeout_jiffies));
148
+
149
+	return -ETIMEDOUT;
150
+}
151
+
152
+static int au1550nd_exec_instr(struct nand_chip *this,
153
+			       const struct nand_op_instr *instr)
154
+{
155
+	struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
156
+	unsigned int i;
157
+	int ret = 0;
158
+
159
+	switch (instr->type) {
160
+	case NAND_OP_CMD_INSTR:
161
+		writeb(instr->ctx.cmd.opcode,
162
+		       ctx->base + MEM_STNAND_CMD);
163
+		/* Drain the writebuffer */
164
+		wmb();
165
+		break;
166
+
167
+	case NAND_OP_ADDR_INSTR:
168
+		for (i = 0; i < instr->ctx.addr.naddrs; i++) {
169
+			writeb(instr->ctx.addr.addrs[i],
170
+			       ctx->base + MEM_STNAND_ADDR);
171
+			/* Drain the writebuffer */
172
+			wmb();
173
+		}
174
+		break;
175
+
176
+	case NAND_OP_DATA_IN_INSTR:
177
+		if ((this->options & NAND_BUSWIDTH_16) &&
178
+		    !instr->ctx.data.force_8bit)
179
+			au_read_buf16(this, instr->ctx.data.buf.in,
180
+				      instr->ctx.data.len);
181
+		else
182
+			au_read_buf(this, instr->ctx.data.buf.in,
183
+				    instr->ctx.data.len);
184
+		break;
185
+
186
+	case NAND_OP_DATA_OUT_INSTR:
187
+		if ((this->options & NAND_BUSWIDTH_16) &&
188
+		    !instr->ctx.data.force_8bit)
189
+			au_write_buf16(this, instr->ctx.data.buf.out,
190
+				       instr->ctx.data.len);
191
+		else
192
+			au_write_buf(this, instr->ctx.data.buf.out,
193
+				     instr->ctx.data.len);
194
+		break;
195
+
196
+	case NAND_OP_WAITRDY_INSTR:
197
+		ret = au1550nd_waitrdy(this, instr->ctx.waitrdy.timeout_ms);
198
+		break;
199
+	default:
200
+		return -EINVAL;
201
+	}
202
+
203
+	if (instr->delay_ns)
204
+		ndelay(instr->delay_ns);
205
+
206
+	return ret;
207
+}
208
+
209
+static int au1550nd_exec_op(struct nand_chip *this,
210
+			    const struct nand_operation *op,
211
+			    bool check_only)
212
+{
213
+	struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
214
+	unsigned int i;
215
+	int ret;
216
+
217
+	if (check_only)
218
+		return 0;
219
+
220
+	/* assert (force assert) chip enable */
221
+	alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
222
+	/* Drain the writebuffer */
223
+	wmb();
224
+
225
+	for (i = 0; i < op->ninstrs; i++) {
226
+		ret = au1550nd_exec_instr(this, &op->instrs[i]);
227
+		if (ret)
228
+			break;
229
+	}
230
+
231
+	/* deassert chip enable */
232
+	alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
233
+	/* Drain the writebuffer */
234
+	wmb();
235
+
236
+	return ret;
237
+}
238
+
239
+static int au1550nd_attach_chip(struct nand_chip *chip)
240
+{
241
+	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
242
+	    chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
243
+		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
244
+
245
+	return 0;
246
+}
247
+
248
+static const struct nand_controller_ops au1550nd_ops = {
249
+	.exec_op = au1550nd_exec_op,
250
+	.attach_chip = au1550nd_attach_chip,
251
+};
399252 
400253 static int au1550nd_probe(struct platform_device *pdev)
401254 {
....@@ -428,7 +281,7 @@
428281 		goto out1;
429282 	}
430283 
431
-	ctx->base = ioremap_nocache(r->start, 0x1000);
284
+	ctx->base = ioremap(r->start, 0x1000);
432285 	if (!ctx->base) {
433286 		dev_err(&pdev->dev, "cannot remap NAND memory area\n");
434287 		ret = -ENODEV;
....@@ -448,23 +301,19 @@
448301 	}
449302 	ctx->cs = cs;
450303 
451
-	this->dev_ready = au1550_device_ready;
452
-	this->select_chip = au1550_select_chip;
453
-	this->cmdfunc = au1550_command;
454
-
455
-	/* 30 us command delay time */
456
-	this->chip_delay = 30;
457
-	this->ecc.mode = NAND_ECC_SOFT;
458
-	this->ecc.algo = NAND_ECC_HAMMING;
304
+	nand_controller_init(&ctx->controller);
305
+	ctx->controller.ops = &au1550nd_ops;
306
+	this->controller = &ctx->controller;
459307 
460308 	if (pd->devwidth)
461309 		this->options |= NAND_BUSWIDTH_16;
462310 
463
-	this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
464
-	ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
465
-	this->read_word = au_read_word;
466
-	this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
467
-	this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
311
+	/*
312
+	 * This driver assumes that the default ECC engine should be TYPE_SOFT.
313
+	 * Set ->engine_type before registering the NAND devices in order to
314
+	 * provide a driver specific default value.
315
+	 */
316
+	this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
468317 
469318 	ret = nand_scan(this, 1);
470319 	if (ret) {
....@@ -491,8 +340,12 @@
491340 {
492341 	struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
493342 	struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343
+	struct nand_chip *chip = &ctx->chip;
344
+	int ret;
494345 
495
-	nand_release(&ctx->chip);
346
+	ret = mtd_device_unregister(nand_to_mtd(chip));
347
+	WARN_ON(ret);
348
+	nand_cleanup(chip);
496349 	iounmap(ctx->base);
497350 	release_mem_region(r->start, 0x1000);
498351 	kfree(ctx);