enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/mmc/host/tmio_mmc.c
..
..
@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0
1
2
 /*
2
3
  * Driver for the MMC / SD / SDIO cell found in:
3
4
  *
..
..
@@ -7,12 +8,9 @@
7
8
  * Copyright (C) 2017 Horms Solutions, Simon Horman
8
9
  * Copyright (C) 2007 Ian Molton
9
10
  * Copyright (C) 2004 Ian Molton
10
- *
11
- * This program is free software; you can redistribute it and/or modify
12
- * it under the terms of the GNU General Public License version 2 as
13
- * published by the Free Software Foundation.
14
11
  */
15
12
 
13
+#include <linux/delay.h>
16
14
 #include <linux/device.h>
17
15
 #include <linux/mfd/core.h>
18
16
 #include <linux/mfd/tmio.h>
..
..
@@ -22,6 +20,68 @@
22
20
 #include <linux/scatterlist.h>
23
21
 
24
22
 #include "tmio_mmc.h"
23
+
24
+/* Registers specific to this variant */
25
+#define CTL_SDIO_REGS		0x100
26
+#define CTL_CLK_AND_WAIT_CTL	0x138
27
+#define CTL_RESET_SDIO		0x1e0
28
+
29
+static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
30
+{
31
+	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
32
+		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
33
+
34
+	usleep_range(10000, 11000);
35
+	sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
36
+	usleep_range(10000, 11000);
37
+}
38
+
39
+static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
40
+{
41
+	sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
42
+	usleep_range(10000, 11000);
43
+
44
+	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
45
+		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
46
+
47
+	usleep_range(10000, 11000);
48
+}
49
+
50
+static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
51
+			       unsigned int new_clock)
52
+{
53
+	unsigned int divisor;
54
+	u32 clk = 0;
55
+	int clk_sel;
56
+
57
+	if (new_clock == 0) {
58
+		tmio_mmc_clk_stop(host);
59
+		return;
60
+	}
61
+
62
+	divisor = host->pdata->hclk / new_clock;
63
+
64
+	/* bit7 set: 1/512, ... bit0 set: 1/4, all bits clear: 1/2 */
65
+	clk_sel = (divisor <= 1);
66
+	clk = clk_sel ? 0 : (roundup_pow_of_two(divisor) >> 2);
67
+
68
+	host->pdata->set_clk_div(host->pdev, clk_sel);
69
+
70
+	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
71
+			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
72
+	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
73
+	usleep_range(10000, 11000);
74
+
75
+	tmio_mmc_clk_start(host);
76
+}
77
+
78
+static void tmio_mmc_reset(struct tmio_mmc_host *host)
79
+{
80
+	sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
81
+	usleep_range(10000, 11000);
82
+	sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
83
+	usleep_range(10000, 11000);
84
+}
25
85
 
26
86
 #ifdef CONFIG_PM_SLEEP
27
87
 static int tmio_mmc_suspend(struct device *dev)
..
..
@@ -90,8 +150,6 @@
90
150
 		goto cell_disable;
91
151
 	}
92
152
 
93
-	pdata->flags |= TMIO_MMC_HAVE_HIGH_REG;
94
-
95
153
 	host = tmio_mmc_host_alloc(pdev, pdata);
96
154
 	if (IS_ERR(host)) {
97
155
 		ret = PTR_ERR(host);
..
..
@@ -100,6 +158,8 @@
100
158
 
101
159
 	/* SD control register space size is 0x200, 0x400 for bus_shift=1 */
102
160
 	host->bus_shift = resource_size(res) >> 10;
161
+	host->set_clock = tmio_mmc_set_clock;
162
+	host->reset = tmio_mmc_reset;
103
163
 
104
164
 	host->mmc->f_max = pdata->hclk;
105
165
 	host->mmc->f_min = pdata->hclk / 512;
..
..
@@ -153,6 +213,7 @@
153
213
 static struct platform_driver tmio_mmc_driver = {
154
214
 	.driver = {
155
215
 		.name = "tmio-mmc",
216
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
156
217
 		.pm = &tmio_mmc_dev_pm_ops,
157
218
 	},
158
219
 	.probe = tmio_mmc_probe,