forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/mmc/host/mmci.h
....@@ -1,11 +1,8 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  *  linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
34  *
45  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
96  */
107 #define MMCIPOWER		0x000
118 #define MCI_PWR_OFF		0x00
....@@ -23,6 +20,14 @@
2320 #define MCI_ST_DATA31DIREN	(1 << 5)
2421 #define MCI_ST_FBCLKEN		(1 << 7)
2522 #define MCI_ST_DATA74DIREN	(1 << 8)
23
+/*
24
+ * The STM32 sdmmc does not have PWR_UP/OD/ROD
25
+ * and uses the power register for
26
+ */
27
+#define MCI_STM32_PWR_CYC	0x02
28
+#define MCI_STM32_VSWITCH	BIT(2)
29
+#define MCI_STM32_VSWITCHEN	BIT(3)
30
+#define MCI_STM32_DIRPOL	BIT(4)
2631 
2732 #define MMCICLOCK		0x004
2833 #define MCI_CLK_ENABLE		(1 << 8)
....@@ -50,6 +55,19 @@
5055 #define MCI_QCOM_CLK_SELECT_IN_FBCLK	BIT(15)
5156 #define MCI_QCOM_CLK_SELECT_IN_DDR_MODE	(BIT(14) | BIT(15))
5257 
58
+/* Modified on STM32 sdmmc */
59
+#define MCI_STM32_CLK_CLKDIV_MSK	GENMASK(9, 0)
60
+#define MCI_STM32_CLK_WIDEBUS_4		BIT(14)
61
+#define MCI_STM32_CLK_WIDEBUS_8		BIT(15)
62
+#define MCI_STM32_CLK_NEGEDGE		BIT(16)
63
+#define MCI_STM32_CLK_HWFCEN		BIT(17)
64
+#define MCI_STM32_CLK_DDR		BIT(18)
65
+#define MCI_STM32_CLK_BUSSPEED		BIT(19)
66
+#define MCI_STM32_CLK_SEL_MSK		GENMASK(21, 20)
67
+#define MCI_STM32_CLK_SELCK		(0 << 20)
68
+#define MCI_STM32_CLK_SELCKIN		(1 << 20)
69
+#define MCI_STM32_CLK_SELFBCK		(2 << 20)
70
+
5371 #define MMCIARGUMENT		0x008
5472 
5573 /* The command register controls the Command Path State Machine (CPSM) */
....@@ -72,6 +90,15 @@
7290 #define MCI_CPSM_QCOM_CCSDISABLE	BIT(15)
7391 #define MCI_CPSM_QCOM_AUTO_CMD19	BIT(16)
7492 #define MCI_CPSM_QCOM_AUTO_CMD21	BIT(21)
93
+/* Command register in STM32 sdmmc versions */
94
+#define MCI_CPSM_STM32_CMDTRANS		BIT(6)
95
+#define MCI_CPSM_STM32_CMDSTOP		BIT(7)
96
+#define MCI_CPSM_STM32_WAITRESP_MASK	GENMASK(9, 8)
97
+#define MCI_CPSM_STM32_NORSP		(0 << 8)
98
+#define MCI_CPSM_STM32_SRSP_CRC		(1 << 8)
99
+#define MCI_CPSM_STM32_SRSP		(2 << 8)
100
+#define MCI_CPSM_STM32_LRSP_CRC		(3 << 8)
101
+#define MCI_CPSM_STM32_ENABLE		BIT(12)
75102 
76103 #define MMCIRESPCMD		0x010
77104 #define MMCIRESPONSE0		0x014
....@@ -101,6 +128,11 @@
101128 /* Control register extensions in the Qualcomm versions */
102129 #define MCI_DPSM_QCOM_DATA_PEND	BIT(17)
103130 #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)
131
+/* Control register extensions in STM32 versions */
132
+#define MCI_DPSM_STM32_MODE_BLOCK	(0 << 2)
133
+#define MCI_DPSM_STM32_MODE_SDIO	(1 << 2)
134
+#define MCI_DPSM_STM32_MODE_STREAM	(2 << 2)
135
+#define MCI_DPSM_STM32_MODE_BLOCK_STOP	(3 << 2)
104136 
105137 #define MMCIDATACNT		0x030
106138 #define MMCISTATUS		0x034
....@@ -130,6 +162,10 @@
130162 #define MCI_ST_SDIOIT		(1 << 22)
131163 #define MCI_ST_CEATAEND		(1 << 23)
132164 #define MCI_ST_CARDBUSY		(1 << 24)
165
+/* Extended status bits for the STM32 variants */
166
+#define MCI_STM32_BUSYD0	BIT(20)
167
+#define MCI_STM32_BUSYD0END	BIT(21)
168
+#define MCI_STM32_VSWEND	BIT(25)
133169 
134170 #define MMCICLEAR		0x038
135171 #define MCI_CMDCRCFAILCLR	(1 << 0)
....@@ -147,6 +183,9 @@
147183 #define MCI_ST_SDIOITC		(1 << 22)
148184 #define MCI_ST_CEATAENDC	(1 << 23)
149185 #define MCI_ST_BUSYENDC		(1 << 24)
186
+/* Extended clear bits for the STM32 variants */
187
+#define MCI_STM32_VSWENDC	BIT(25)
188
+#define MCI_STM32_CKSTOPC	BIT(26)
150189 
151190 #define MMCIMASK0		0x03c
152191 #define MCI_CMDCRCFAILMASK	(1 << 0)
....@@ -175,10 +214,31 @@
175214 #define MCI_ST_SDIOITMASK	(1 << 22)
176215 #define MCI_ST_CEATAENDMASK	(1 << 23)
177216 #define MCI_ST_BUSYENDMASK	(1 << 24)
217
+/* Extended status bits for the STM32 variants */
218
+#define MCI_STM32_BUSYD0ENDMASK	BIT(21)
178219 
179220 #define MMCIMASK1		0x040
180221 #define MMCIFIFOCNT		0x048
181222 #define MMCIFIFO		0x080 /* to 0x0bc */
223
+
224
+/* STM32 sdmmc registers for IDMA (Internal DMA) */
225
+#define MMCI_STM32_IDMACTRLR	0x050
226
+#define MMCI_STM32_IDMAEN	BIT(0)
227
+#define MMCI_STM32_IDMALLIEN	BIT(1)
228
+
229
+#define MMCI_STM32_IDMABSIZER		0x054
230
+#define MMCI_STM32_IDMABNDT_SHIFT	5
231
+#define MMCI_STM32_IDMABNDT_MASK	GENMASK(12, 5)
232
+
233
+#define MMCI_STM32_IDMABASE0R	0x058
234
+
235
+#define MMCI_STM32_IDMALAR	0x64
236
+#define MMCI_STM32_IDMALA_MASK	GENMASK(13, 0)
237
+#define MMCI_STM32_ABR		BIT(29)
238
+#define MMCI_STM32_ULS		BIT(30)
239
+#define MMCI_STM32_ULA		BIT(31)
240
+
241
+#define MMCI_STM32_IDMABAR	0x68
182242 
183243 #define MCI_IRQENABLE	\
184244 	(MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \
....@@ -186,9 +246,12 @@
186246 	MCI_CMDRESPENDMASK | MCI_CMDSENTMASK)
187247 
188248 /* These interrupts are directed to IRQ1 when two IRQ lines are available */
189
-#define MCI_IRQ1MASK \
249
+#define MCI_IRQ_PIO_MASK \
190250 	(MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
191251 	 MCI_TXFIFOHALFEMPTYMASK)
252
+
253
+#define MCI_IRQ_PIO_STM32_MASK \
254
+	(MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK)
192255 
193256 #define NR_SG		128
194257 
....@@ -204,6 +267,11 @@
204267  * @clkreg_enable: enable value for MMCICLOCK register
205268  * @clkreg_8bit_bus_enable: enable value for 8 bit bus
206269  * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
270
+ * @cmdreg_cpsm_enable: enable value for CPSM
271
+ * @cmdreg_lrsp_crc: enable value for long response with crc
272
+ * @cmdreg_srsp_crc: enable value for short response with crc
273
+ * @cmdreg_srsp: enable value for short response without crc
274
+ * @cmdreg_stop: enable value for stop and abort transmission
207275  * @datalength_bits: number of bits in the MMCIDATALENGTH register
208276  * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
209277  *	      is asserted (likewise for RX)
....@@ -212,16 +280,24 @@
212280  * @data_cmd_enable: enable value for data commands.
213281  * @st_sdio: enable ST specific SDIO logic
214282  * @st_clkdiv: true if using a ST-specific clock divider algorithm
283
+ * @stm32_clkdiv: true if using a STM32-specific clock divider algorithm
215284  * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
216
- * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
217
- * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
218
- *		     register
219285  * @datactrl_mask_sdio: SDIO enable mask in datactrl register
286
+ * @datactrl_blocksz: block size in power of two
287
+ * @datactrl_any_blocksz: true if block any block sizes are accepted by
288
+ *		  hardware, such as with some SDIO traffic that send
289
+ *		  odd packets.
290
+ * @dma_power_of_2: DMA only works with blocks that are a power of 2.
291
+ * @datactrl_first: true if data must be setup before send command
292
+ * @datacnt_useless: true if you could not use datacnt register to read
293
+ *		     remaining data
220294  * @pwrreg_powerup: power up value for MMCIPOWER register
221295  * @f_max: maximum clk frequency supported by the controller.
222296  * @signal_direction: input/out direction of bus signals can be indicated
223297  * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
224298  * @busy_detect: true if the variant supports busy detection on DAT0.
299
+ * @busy_timeout: true if the variant starts data timer when the DPSM
300
+ *		  enter in Wait_R or Busy state.
225301  * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
226302  * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
227303  *		      indicating that the card is busy
....@@ -233,53 +309,80 @@
233309  * @qcom_dml: enables qcom specific dma glue for dma transfers.
234310  * @reversed_irq_handling: handle data irq before cmd irq.
235311  * @mmcimask1: true if variant have a MMCIMASK1 register.
312
+ * @irq_pio_mask: bitmask used to manage interrupt pio transfert in mmcimask
313
+ *		  register
236314  * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS
237315  *	       register.
238316  * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
317
+ * @dma_lli: true if variant has dma link list feature.
318
+ * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
239319  */
240320 struct variant_data {
241321 	unsigned int		clkreg;
242322 	unsigned int		clkreg_enable;
243323 	unsigned int		clkreg_8bit_bus_enable;
244324 	unsigned int		clkreg_neg_edge_enable;
325
+	unsigned int		cmdreg_cpsm_enable;
326
+	unsigned int		cmdreg_lrsp_crc;
327
+	unsigned int		cmdreg_srsp_crc;
328
+	unsigned int		cmdreg_srsp;
329
+	unsigned int		cmdreg_stop;
245330 	unsigned int		datalength_bits;
246331 	unsigned int		fifosize;
247332 	unsigned int		fifohalfsize;
248333 	unsigned int		data_cmd_enable;
249334 	unsigned int		datactrl_mask_ddrmode;
250335 	unsigned int		datactrl_mask_sdio;
251
-	bool			st_sdio;
252
-	bool			st_clkdiv;
253
-	bool			blksz_datactrl16;
254
-	bool			blksz_datactrl4;
336
+	unsigned int		datactrl_blocksz;
337
+	u8			datactrl_any_blocksz:1;
338
+	u8			dma_power_of_2:1;
339
+	u8			datactrl_first:1;
340
+	u8			datacnt_useless:1;
341
+	u8			st_sdio:1;
342
+	u8			st_clkdiv:1;
343
+	u8			stm32_clkdiv:1;
255344 	u32			pwrreg_powerup;
256345 	u32			f_max;
257
-	bool			signal_direction;
258
-	bool			pwrreg_clkgate;
259
-	bool			busy_detect;
346
+	u8			signal_direction:1;
347
+	u8			pwrreg_clkgate:1;
348
+	u8			busy_detect:1;
349
+	u8			busy_timeout:1;
260350 	u32			busy_dpsm_flag;
261351 	u32			busy_detect_flag;
262352 	u32			busy_detect_mask;
263
-	bool			pwrreg_nopower;
264
-	bool			explicit_mclk_control;
265
-	bool			qcom_fifo;
266
-	bool			qcom_dml;
267
-	bool			reversed_irq_handling;
268
-	bool			mmcimask1;
353
+	u8			pwrreg_nopower:1;
354
+	u8			explicit_mclk_control:1;
355
+	u8			qcom_fifo:1;
356
+	u8			qcom_dml:1;
357
+	u8			reversed_irq_handling:1;
358
+	u8			mmcimask1:1;
359
+	unsigned int		irq_pio_mask;
269360 	u32			start_err;
270361 	u32			opendrain;
362
+	u8			dma_lli:1;
363
+	u32			stm32_idmabsize_mask;
271364 	void (*init)(struct mmci_host *host);
272365 };
273366 
274367 /* mmci variant callbacks */
275368 struct mmci_host_ops {
276
-	void (*dma_setup)(struct mmci_host *host);
277
-};
278
-
279
-struct mmci_host_next {
280
-	struct dma_async_tx_descriptor	*dma_desc;
281
-	struct dma_chan			*dma_chan;
282
-	s32				cookie;
369
+	int (*validate_data)(struct mmci_host *host, struct mmc_data *data);
370
+	int (*prep_data)(struct mmci_host *host, struct mmc_data *data,
371
+			 bool next);
372
+	void (*unprep_data)(struct mmci_host *host, struct mmc_data *data,
373
+			    int err);
374
+	u32 (*get_datactrl_cfg)(struct mmci_host *host);
375
+	void (*get_next_data)(struct mmci_host *host, struct mmc_data *data);
376
+	int (*dma_setup)(struct mmci_host *host);
377
+	void (*dma_release)(struct mmci_host *host);
378
+	int (*dma_start)(struct mmci_host *host, unsigned int *datactrl);
379
+	void (*dma_finalize)(struct mmci_host *host, struct mmc_data *data);
380
+	void (*dma_error)(struct mmci_host *host);
381
+	void (*set_clkreg)(struct mmci_host *host, unsigned int desired);
382
+	void (*set_pwrreg)(struct mmci_host *host, unsigned int pwr);
383
+	bool (*busy_complete)(struct mmci_host *host, u32 status, u32 err_msk);
384
+	void (*pre_sig_volt_switch)(struct mmci_host *host);
385
+	int (*post_sig_volt_switch)(struct mmci_host *host, struct mmc_ios *ios);
283386 };
284387 
285388 struct mmci_host {
....@@ -287,10 +390,13 @@
287390 	void __iomem		*base;
288391 	struct mmc_request	*mrq;
289392 	struct mmc_command	*cmd;
393
+	struct mmc_command	stop_abort;
290394 	struct mmc_data		*data;
291395 	struct mmc_host		*mmc;
292396 	struct clk		*clk;
293
-	bool			singleirq;
397
+	u8			singleirq:1;
398
+
399
+	struct reset_control	*rst;
294400 
295401 	spinlock_t		lock;
296402 
....@@ -301,15 +407,17 @@
301407 	u32			pwr_reg;
302408 	u32			pwr_reg_add;
303409 	u32			clk_reg;
410
+	u32			clk_reg_add;
304411 	u32			datactrl_reg;
305412 	u32			busy_status;
306413 	u32			mask1_reg;
307
-	bool			vqmmc_enabled;
414
+	u8			vqmmc_enabled:1;
308415 	struct mmci_platform_data *plat;
416
+	struct mmc_host_ops	*mmc_ops;
309417 	struct mmci_host_ops	*ops;
310418 	struct variant_data	*variant;
419
+	void			*variant_priv;
311420 	struct pinctrl		*pinctrl;
312
-	struct pinctrl_state	*pins_default;
313421 	struct pinctrl_state	*pins_opendrain;
314422 
315423 	u8			hw_designer;
....@@ -317,24 +425,51 @@
317425 
318426 	struct timer_list	timer;
319427 	unsigned int		oldstat;
428
+	u32			irq_action;
320429 
321430 	/* pio stuff */
322431 	struct sg_mapping_iter	sg_miter;
323432 	unsigned int		size;
324433 	int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain);
325434 
326
-#ifdef CONFIG_DMA_ENGINE
327
-	/* DMA stuff */
328
-	struct dma_chan		*dma_current;
329
-	struct dma_chan		*dma_rx_channel;
330
-	struct dma_chan		*dma_tx_channel;
331
-	struct dma_async_tx_descriptor	*dma_desc_current;
332
-	struct mmci_host_next	next_data;
333
-	bool			dma_in_progress;
435
+	u8			use_dma:1;
436
+	u8			dma_in_progress:1;
437
+	void			*dma_priv;
334438 
335
-#define dma_inprogress(host)	((host)->dma_in_progress)
336
-#else
337
-#define dma_inprogress(host)	(0)
338
-#endif
439
+	s32			next_cookie;
339440 };
340441 
442
+#define dma_inprogress(host)	((host)->dma_in_progress)
443
+
444
+void mmci_write_clkreg(struct mmci_host *host, u32 clk);
445
+void mmci_write_pwrreg(struct mmci_host *host, u32 pwr);
446
+
447
+static inline u32 mmci_dctrl_blksz(struct mmci_host *host)
448
+{
449
+	return (ffs(host->data->blksz) - 1) << 4;
450
+}
451
+
452
+#ifdef CONFIG_DMA_ENGINE
453
+int mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
454
+			bool next);
455
+void mmci_dmae_unprep_data(struct mmci_host *host, struct mmc_data *data,
456
+			   int err);
457
+void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data);
458
+int mmci_dmae_setup(struct mmci_host *host);
459
+void mmci_dmae_release(struct mmci_host *host);
460
+int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl);
461
+void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data);
462
+void mmci_dmae_error(struct mmci_host *host);
463
+#endif
464
+
465
+#ifdef CONFIG_MMC_QCOM_DML
466
+void qcom_variant_init(struct mmci_host *host);
467
+#else
468
+static inline void qcom_variant_init(struct mmci_host *host) {}
469
+#endif
470
+
471
+#ifdef CONFIG_MMC_STM32_SDMMC
472
+void sdmmc_variant_init(struct mmci_host *host);
473
+#else
474
+static inline void sdmmc_variant_init(struct mmci_host *host) {}
475
+#endif