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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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| 1 | 2 | /* |
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| 2 | 3 | * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright (C) 2012, Samsung Electronics Co., Ltd. |
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| 5 | | - * |
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| 6 | | - * This program is free software; you can redistribute it and/or modify |
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| 7 | | - * it under the terms of the GNU General Public License as published by |
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| 8 | | - * the Free Software Foundation; either version 2 of the License, or |
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| 9 | | - * (at your option) any later version. |
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| 10 | 6 | */ |
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| 11 | 7 | |
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| 12 | 8 | #include <linux/module.h> |
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| .. | .. |
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| 180 | 176 | #ifdef CONFIG_PM_SLEEP |
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| 181 | 177 | /** |
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| 182 | 178 | * dw_mci_exynos_suspend_noirq - Exynos-specific suspend code |
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| 179 | + * @dev: Device to suspend (this device) |
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| 183 | 180 | * |
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| 184 | 181 | * This ensures that device will be in runtime active state in |
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| 185 | 182 | * dw_mci_exynos_resume_noirq after calling pm_runtime_force_resume() |
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| .. | .. |
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| 192 | 189 | |
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| 193 | 190 | /** |
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| 194 | 191 | * dw_mci_exynos_resume_noirq - Exynos-specific resume code |
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| 192 | + * @dev: Device to resume (this device) |
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| 195 | 193 | * |
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| 196 | 194 | * On exynos5420 there is a silicon errata that will sometimes leave the |
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| 197 | 195 | * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate |
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| .. | .. |
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| 253 | 251 | if (timing == MMC_TIMING_MMC_HS400) { |
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| 254 | 252 | dqs |= DATA_STROBE_EN; |
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| 255 | 253 | strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay); |
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| 254 | + } else if (timing == MMC_TIMING_UHS_SDR104) { |
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| 255 | + dqs &= 0xffffff00; |
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| 256 | 256 | } else { |
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| 257 | 257 | dqs &= ~DATA_STROBE_EN; |
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| 258 | 258 | } |
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| .. | .. |
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| 311 | 311 | /* Should be double rate for DDR mode */ |
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| 312 | 312 | if (ios->bus_width == MMC_BUS_WIDTH_8) |
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| 313 | 313 | wanted <<= 1; |
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| 314 | + break; |
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| 315 | + case MMC_TIMING_UHS_SDR104: |
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| 316 | + case MMC_TIMING_UHS_SDR50: |
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| 317 | + clksel = (priv->sdr_timing & 0xfff8ffff) | |
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| 318 | + (priv->ciu_div << 16); |
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| 319 | + break; |
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| 320 | + case MMC_TIMING_UHS_DDR50: |
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| 321 | + clksel = (priv->ddr_timing & 0xfff8ffff) | |
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| 322 | + (priv->ciu_div << 16); |
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| 314 | 323 | break; |
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| 315 | 324 | default: |
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| 316 | 325 | clksel = priv->sdr_timing; |
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| .. | .. |
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| 477 | 486 | struct dw_mci_exynos_priv_data *priv = host->priv; |
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| 478 | 487 | struct mmc_host *mmc = slot->mmc; |
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| 479 | 488 | u8 start_smpl, smpl, candiates = 0; |
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| 480 | | - s8 found = -1; |
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| 489 | + s8 found; |
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| 481 | 490 | int ret = 0; |
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| 482 | 491 | |
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| 483 | 492 | start_smpl = dw_mci_exynos_get_clksmpl(host); |
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| .. | .. |
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| 597 | 606 | .remove = dw_mci_exynos_remove, |
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| 598 | 607 | .driver = { |
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| 599 | 608 | .name = "dwmmc_exynos", |
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| 609 | + .probe_type = PROBE_PREFER_ASYNCHRONOUS, |
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| 600 | 610 | .of_match_table = dw_mci_exynos_match, |
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| 601 | 611 | .pm = &dw_mci_exynos_pmops, |
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| 602 | 612 | }, |
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