enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/memory/ti-emif-sram-pm.S
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@@ -14,12 +14,12 @@
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  * GNU General Public License for more details.
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  */
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-#include <generated/ti-emif-asm-offsets.h>
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 #include <linux/linkage.h>
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 #include <asm/assembler.h>
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 #include <asm/memory.h>
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 #include "emif.h"
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+#include "ti-emif-asm-offsets.h"
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 #define EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES	0x00a0
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 #define EMIF_POWER_MGMT_SR_TIMER_MASK			0x00f0
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@@ -27,6 +27,7 @@
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 #define EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK		0x0700
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 #define EMIF_SDCFG_TYPE_DDR2				0x2 << SDRAM_TYPE_SHIFT
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+#define EMIF_SDCFG_TYPE_DDR3				0x3 << SDRAM_TYPE_SHIFT
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 #define EMIF_STATUS_READY				0x4
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 #define AM43XX_EMIF_PHY_CTRL_REG_COUNT                  0x120
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@@ -245,6 +246,46 @@
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 ENDPROC(ti_emif_restore_context)
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 /*
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+ * void ti_emif_run_hw_leveling(void)
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+ *
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+ * Used during resume to run hardware leveling again and restore the
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+ * configuration of the EMIF PHY, only for DDR3.
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+ */
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+ENTRY(ti_emif_run_hw_leveling)
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+	adr	r4, ti_emif_pm_sram_data
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+	ldr	r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
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+
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+	ldr	r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
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+	orr	r3, r3, #RDWRLVLFULL_START
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+	ldr	r2, [r0, #EMIF_SDRAM_CONFIG]
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+	and	r2, r2, #SDRAM_TYPE_MASK
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+	cmp	r2, #EMIF_SDCFG_TYPE_DDR3
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+	bne	skip_hwlvl
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+
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+	str	r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
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+
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+	/*
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+	 * If EMIF registers are touched during initial stage of HW
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+	 * leveling sequence there will be an L3 NOC timeout error issued
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+	 * as the EMIF will not respond, which is not fatal, but it is
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+	 * avoidable. This small wait loop is enough time for this condition
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+	 * to clear, even at worst case of CPU running at max speed of 1Ghz.
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+	 */
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+	mov	r2, #0x2000
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+1:
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+	subs	r2, r2, #0x1
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+	bne	1b
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+
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+	/* Bit clears when operation is complete */
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+2:	ldr     r1, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
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+	tst     r1, #RDWRLVLFULL_START
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+	bne     2b
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+
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+skip_hwlvl:
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+	mov	pc, lr
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+ENDPROC(ti_emif_run_hw_leveling)
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+
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+/*
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  * void ti_emif_enter_sr(void)
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  *
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  * Programs the EMIF to tell the SDRAM to enter into self-refresh