enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/media/platform/rockchip/isp/common.c
..
..
@@ -18,7 +18,25 @@
18
18
 	*flag = SW_REG_CACHE;
19
19
 	if (dev->hw_dev->is_single || is_direct) {
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20
 		*flag = SW_REG_CACHE_SYNC;
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+		if (dev->isp_ver == ISP_V32 && reg <= 0x200)
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+			rv1106_sdmmc_get_lock();
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23
 		writel(val, dev->hw_dev->base_addr + reg);
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+		if (dev->isp_ver == ISP_V32 && reg <= 0x200)
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+			rv1106_sdmmc_put_lock();
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+	}
27
+}
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+
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+void rkisp_next_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct)
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+{
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+	u32 offset = RKISP_ISP_SW_MAX_SIZE + reg;
32
+	u32 *mem = dev->sw_base_addr + offset;
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+	u32 *flag = dev->sw_base_addr + offset + RKISP_ISP_SW_REG_SIZE;
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+
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+	*mem = val;
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+	*flag = SW_REG_CACHE;
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+	if (dev->hw_dev->is_single || is_direct) {
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+		*flag = SW_REG_CACHE_SYNC;
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+		writel(val, dev->hw_dev->base_next_addr + reg);
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40
 	}
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41
 }
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42
 
..
..
@@ -33,9 +51,15 @@
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 	return val;
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 }
35
53
 
36
-u32 rkisp_read_reg_cache(struct rkisp_device *dev, u32 reg)
54
+u32 rkisp_next_read(struct rkisp_device *dev, u32 reg, bool is_direct)
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55
 {
38
-	return *(u32 *)(dev->sw_base_addr + reg);
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+	u32 val;
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+
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+	if (dev->hw_dev->is_single || is_direct)
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+		val = readl(dev->hw_dev->base_next_addr + reg);
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+	else
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+		val = *(u32 *)(dev->sw_base_addr + RKISP_ISP_SW_MAX_SIZE + reg);
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+	return val;
39
63
 }
40
64
 
41
65
 void rkisp_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct)
..
..
@@ -45,6 +69,13 @@
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 	rkisp_write(dev, reg, val | tmp, is_direct);
46
70
 }
47
71
 
72
+void rkisp_next_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct)
73
+{
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+	u32 tmp = rkisp_next_read(dev, reg, is_direct) & ~mask;
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+
76
+	rkisp_next_write(dev, reg, val | tmp, is_direct);
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+}
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+
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 void rkisp_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, bool is_direct)
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 {
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81
 	u32 tmp = rkisp_read(dev, reg, is_direct);
..
..
@@ -52,9 +83,70 @@
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83
 	rkisp_write(dev, reg, tmp & ~mask, is_direct);
53
84
 }
54
85
 
86
+void rkisp_next_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, bool is_direct)
87
+{
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+	u32 tmp = rkisp_next_read(dev, reg, is_direct);
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+
90
+	rkisp_next_write(dev, reg, tmp & ~mask, is_direct);
91
+}
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+
93
+void rkisp_write_reg_cache(struct rkisp_device *dev, u32 reg, u32 val)
94
+{
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+	u32 *mem = dev->sw_base_addr + reg;
96
+
97
+	*mem = val;
98
+}
99
+
100
+void rkisp_next_write_reg_cache(struct rkisp_device *dev, u32 reg, u32 val)
101
+{
102
+	u32 offset = RKISP_ISP_SW_MAX_SIZE + reg;
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+	u32 *mem = dev->sw_base_addr + offset;
104
+
105
+	*mem = val;
106
+}
107
+
108
+u32 rkisp_read_reg_cache(struct rkisp_device *dev, u32 reg)
109
+{
110
+	return *(u32 *)(dev->sw_base_addr + reg);
111
+}
112
+
113
+u32 rkisp_next_read_reg_cache(struct rkisp_device *dev, u32 reg)
114
+{
115
+	return *(u32 *)(dev->sw_base_addr + RKISP_ISP_SW_MAX_SIZE + reg);
116
+}
117
+
118
+void rkisp_set_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val)
119
+{
120
+	u32 tmp = rkisp_read_reg_cache(dev, reg) & ~mask;
121
+
122
+	rkisp_write_reg_cache(dev, reg, val | tmp);
123
+}
124
+
125
+void rkisp_next_set_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val)
126
+{
127
+	u32 tmp = rkisp_next_read_reg_cache(dev, reg) & ~mask;
128
+
129
+	rkisp_next_write_reg_cache(dev, reg, val | tmp);
130
+}
131
+
132
+void rkisp_clear_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask)
133
+{
134
+	u32 tmp = rkisp_read_reg_cache(dev, reg);
135
+
136
+	rkisp_write_reg_cache(dev, reg, tmp & ~mask);
137
+}
138
+
139
+void rkisp_next_clear_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask)
140
+{
141
+	u32 tmp = rkisp_next_read_reg_cache(dev, reg);
142
+
143
+	rkisp_next_write_reg_cache(dev, reg, tmp & ~mask);
144
+}
145
+
55
146
 void rkisp_update_regs(struct rkisp_device *dev, u32 start, u32 end)
56
147
 {
57
-	void __iomem *base = dev->hw_dev->base_addr;
148
+	struct rkisp_hw_dev *hw = dev->hw_dev;
149
+	void __iomem *base = hw->base_addr;
58
150
 	u32 i;
59
151
 
60
152
 	if (end > RKISP_ISP_SW_REG_SIZE - 4) {
..
..
@@ -65,8 +157,30 @@
65
157
 		u32 *val = dev->sw_base_addr + i;
66
158
 		u32 *flag = dev->sw_base_addr + i + RKISP_ISP_SW_REG_SIZE;
67
159
 
68
-		if (*flag == SW_REG_CACHE)
160
+		if (dev->procfs.mode & RKISP_PROCFS_FIL_SW) {
161
+			if (!((i >= ISP3X_ISP_ACQ_H_OFFS && i <= ISP3X_ISP_ACQ_V_SIZE) ||
162
+			      (i >= ISP3X_ISP_OUT_H_OFFS && i <= ISP3X_ISP_OUT_V_SIZE) ||
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+			      (i >= ISP3X_DUAL_CROP_BASE && i < ISP3X_DUAL_CROP_FBC_V_SIZE_SHD) ||
164
+			      (i >= ISP3X_MAIN_RESIZE_BASE && i < ISP3X_CSI2RX_VERSION) ||
165
+			      (i >= CIF_ISP_IS_BASE && i < CIF_ISP_IS_V_SIZE_SHD)))
166
+				continue;
167
+		}
168
+
169
+		if (*flag == SW_REG_CACHE) {
170
+			if ((i == ISP3X_MAIN_RESIZE_CTRL ||
171
+			     i == ISP32_BP_RESIZE_CTRL ||
172
+			     i == ISP3X_SELF_RESIZE_CTRL) && *val == 0)
173
+				*val = CIF_RSZ_CTRL_CFG_UPD;
69
174
 			writel(*val, base + i);
175
+			if (hw->is_unite) {
176
+				val = dev->sw_base_addr + i + RKISP_ISP_SW_MAX_SIZE;
177
+				if ((i == ISP3X_MAIN_RESIZE_CTRL ||
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+				     i == ISP32_BP_RESIZE_CTRL ||
179
+				     i == ISP3X_SELF_RESIZE_CTRL) && *val == 0)
180
+					*val = CIF_RSZ_CTRL_CFG_UPD;
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+				writel(*val, hw->base_next_addr + i);
182
+			}
183
+		}
70
184
 	}
71
185
 }
72
186
 
..
..
@@ -78,6 +192,8 @@
78
192
 	struct sg_table	 *sg_tbl;
79
193
 	void *mem_priv;
80
194
 	int ret = 0;
195
+
196
+	mutex_lock(&dev->buf_lock);
81
197
 
82
198
 	if (!buf->size) {
83
199
 		ret = -EINVAL;
..
..
@@ -119,8 +235,10 @@
119
235
 	v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
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236
 		 "%s buf:0x%x~0x%x size:%d\n", __func__,
121
237
 		 (u32)buf->dma_addr, (u32)buf->dma_addr + buf->size, buf->size);
238
+	mutex_unlock(&dev->buf_lock);
122
239
 	return ret;
123
240
 err:
241
+	mutex_unlock(&dev->buf_lock);
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242
 	dev_err(dev->dev, "%s failed ret:%d\n", __func__, ret);
125
243
 	return ret;
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244
 }
..
..
@@ -130,6 +248,7 @@
130
248
 {
131
249
 	const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
132
250
 
251
+	mutex_lock(&dev->buf_lock);
133
252
 	if (buf && buf->mem_priv) {
134
253
 		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
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254
 			 "%s buf:0x%x~0x%x\n", __func__,
..
..
@@ -145,6 +264,7 @@
145
264
 		buf->is_need_vaddr = false;
146
265
 		buf->is_need_dmafd = false;
147
266
 	}
267
+	mutex_unlock(&dev->buf_lock);
148
268
 }
149
269
 
150
270
 void rkisp_prepare_buffer(struct rkisp_device *dev,
..
..
@@ -190,8 +310,6 @@
190
310
 		return -EINVAL;
191
311
 	}
192
312
 
193
-	if (hw->dev_num)
194
-		hw->is_single = false;
195
313
 	isp->dev_id = hw->dev_num;
196
314
 	hw->isp[hw->dev_num] = isp;
197
315
 	hw->dev_num++;
..
..
@@ -269,7 +387,7 @@
269
387
 	struct rkisp_dummy_buffer *dummy_buf = &hw->dummy_buf;
270
388
 	struct rkisp_stream *stream;
271
389
 	struct rkisp_device *isp;
272
-	u32 i, j, size = 0;
390
+	u32 i, j, val, size = 0;
273
391
 	int ret = 0;
274
392
 
275
393
 	if (dummy_buf->mem_priv)
..
..
@@ -279,13 +397,17 @@
279
397
 		size = hw->max_in.w * hw->max_in.h * 2;
280
398
 	for (i = 0; i < hw->dev_num; i++) {
281
399
 		isp = hw->isp[i];
400
+		if (!isp || (isp && !isp->is_hw_link))
401
+			continue;
282
402
 		for (j = 0; j < RKISP_MAX_STREAM; j++) {
283
403
 			stream = &isp->cap_dev.stream[j];
284
404
 			if (!stream->linked)
285
405
 				continue;
286
-			size = max(size,
287
-				   stream->out_fmt.plane_fmt[0].bytesperline *
288
-				   stream->out_fmt.height);
406
+			val = stream->out_isp_fmt.fmt_type == FMT_FBC ?
407
+				stream->out_fmt.plane_fmt[1].sizeimage :
408
+				stream->out_fmt.plane_fmt[0].bytesperline *
409
+				stream->out_fmt.height;
410
+			size = max(size, val);
289
411
 		}
290
412
 	}
291
413
 	if (size == 0)