~hc/RK356X_SDK_RELEASE.git

..	..	@@ -15,9 +15,337 @@
15	15
16	16	#define CIF_ISP_REQ_BUFS_MIN 0
17	17
18		-static int mi_frame_end(struct rkisp_stream *stream);
	18	+static int mi_frame_end(struct rkisp_stream *stream, u32 state);
19	19	static void rkisp_buf_queue(struct vb2_buffer *vb);
20	20
	21	+static const struct capture_fmt mp_fmts[] = {
	22	+ /* yuv422 */
	23	+ {
	24	+ .fourcc = V4L2_PIX_FMT_UYVY,
	25	+ .fmt_type = FMT_YUV,
	26	+ .bpp = { 16 },
	27	+ .cplanes = 1,
	28	+ .mplanes = 1,
	29	+ .uv_swap = 0,
	30	+ .write_format = MI_CTRL_MP_WRITE_YUVINT,
	31	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	32	+ }, {
	33	+ .fourcc = V4L2_PIX_FMT_YUV422P,
	34	+ .fmt_type = FMT_YUV,
	35	+ .bpp = { 8, 4, 4 },
	36	+ .cplanes = 3,
	37	+ .mplanes = 1,
	38	+ .uv_swap = 0,
	39	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	40	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	41	+ }, {
	42	+ .fourcc = V4L2_PIX_FMT_NV16,
	43	+ .fmt_type = FMT_YUV,
	44	+ .bpp = { 8, 16 },
	45	+ .cplanes = 2,
	46	+ .mplanes = 1,
	47	+ .uv_swap = 0,
	48	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	49	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	50	+ }, {
	51	+ .fourcc = V4L2_PIX_FMT_NV61,
	52	+ .fmt_type = FMT_YUV,
	53	+ .bpp = { 8, 16 },
	54	+ .cplanes = 2,
	55	+ .mplanes = 1,
	56	+ .uv_swap = 1,
	57	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	58	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	59	+ }, {
	60	+ .fourcc = V4L2_PIX_FMT_YUV422M,
	61	+ .fmt_type = FMT_YUV,
	62	+ .bpp = { 8, 8, 8 },
	63	+ .cplanes = 3,
	64	+ .mplanes = 3,
	65	+ .uv_swap = 0,
	66	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	67	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	68	+ },
	69	+ /* yuv420 */
	70	+ {
	71	+ .fourcc = V4L2_PIX_FMT_NV21,
	72	+ .fmt_type = FMT_YUV,
	73	+ .bpp = { 8, 16 },
	74	+ .cplanes = 2,
	75	+ .mplanes = 1,
	76	+ .uv_swap = 1,
	77	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	78	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	79	+ }, {
	80	+ .fourcc = V4L2_PIX_FMT_NV12,
	81	+ .fmt_type = FMT_YUV,
	82	+ .bpp = { 8, 16 },
	83	+ .cplanes = 2,
	84	+ .mplanes = 1,
	85	+ .uv_swap = 0,
	86	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	87	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	88	+ }, {
	89	+ .fourcc = V4L2_PIX_FMT_NV21M,
	90	+ .fmt_type = FMT_YUV,
	91	+ .bpp = { 8, 16 },
	92	+ .cplanes = 2,
	93	+ .mplanes = 2,
	94	+ .uv_swap = 1,
	95	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	96	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	97	+ }, {
	98	+ .fourcc = V4L2_PIX_FMT_NV12M,
	99	+ .fmt_type = FMT_YUV,
	100	+ .bpp = { 8, 16 },
	101	+ .cplanes = 2,
	102	+ .mplanes = 2,
	103	+ .uv_swap = 0,
	104	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	105	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	106	+ }, {
	107	+ .fourcc = V4L2_PIX_FMT_YUV420,
	108	+ .fmt_type = FMT_YUV,
	109	+ .bpp = { 8, 8, 8 },
	110	+ .cplanes = 3,
	111	+ .mplanes = 1,
	112	+ .uv_swap = 0,
	113	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	114	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	115	+ },
	116	+ /* yuv444 */
	117	+ {
	118	+ .fourcc = V4L2_PIX_FMT_YUV444M,
	119	+ .fmt_type = FMT_YUV,
	120	+ .bpp = { 8, 8, 8 },
	121	+ .cplanes = 3,
	122	+ .mplanes = 3,
	123	+ .uv_swap = 0,
	124	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	125	+ .output_format = 0,
	126	+ },
	127	+ /* raw */
	128	+ {
	129	+ .fourcc = V4L2_PIX_FMT_SRGGB8,
	130	+ .fmt_type = FMT_BAYER,
	131	+ .bpp = { 8 },
	132	+ .mplanes = 1,
	133	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	134	+ .output_format = 0,
	135	+ }, {
	136	+ .fourcc = V4L2_PIX_FMT_SGRBG8,
	137	+ .fmt_type = FMT_BAYER,
	138	+ .bpp = { 8 },
	139	+ .mplanes = 1,
	140	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	141	+ .output_format = 0,
	142	+ }, {
	143	+ .fourcc = V4L2_PIX_FMT_SGBRG8,
	144	+ .fmt_type = FMT_BAYER,
	145	+ .bpp = { 8 },
	146	+ .mplanes = 1,
	147	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	148	+ .output_format = 0,
	149	+ }, {
	150	+ .fourcc = V4L2_PIX_FMT_SBGGR8,
	151	+ .fmt_type = FMT_BAYER,
	152	+ .bpp = { 8 },
	153	+ .mplanes = 1,
	154	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	155	+ .output_format = 0,
	156	+ }, {
	157	+ .fourcc = V4L2_PIX_FMT_SRGGB10,
	158	+ .fmt_type = FMT_BAYER,
	159	+ .bpp = { 10 },
	160	+ .mplanes = 1,
	161	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	162	+ .output_format = 0,
	163	+ }, {
	164	+ .fourcc = V4L2_PIX_FMT_SGRBG10,
	165	+ .fmt_type = FMT_BAYER,
	166	+ .bpp = { 10 },
	167	+ .mplanes = 1,
	168	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	169	+ .output_format = 0,
	170	+ }, {
	171	+ .fourcc = V4L2_PIX_FMT_SGBRG10,
	172	+ .fmt_type = FMT_BAYER,
	173	+ .bpp = { 10 },
	174	+ .mplanes = 1,
	175	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	176	+ .output_format = 0,
	177	+ }, {
	178	+ .fourcc = V4L2_PIX_FMT_SBGGR10,
	179	+ .fmt_type = FMT_BAYER,
	180	+ .bpp = { 10 },
	181	+ .mplanes = 1,
	182	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	183	+ .output_format = 0,
	184	+ }, {
	185	+ .fourcc = V4L2_PIX_FMT_SRGGB12,
	186	+ .fmt_type = FMT_BAYER,
	187	+ .bpp = { 12 },
	188	+ .mplanes = 1,
	189	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	190	+ .output_format = 0,
	191	+ }, {
	192	+ .fourcc = V4L2_PIX_FMT_SGRBG12,
	193	+ .fmt_type = FMT_BAYER,
	194	+ .bpp = { 12 },
	195	+ .mplanes = 1,
	196	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	197	+ .output_format = 0,
	198	+ }, {
	199	+ .fourcc = V4L2_PIX_FMT_SGBRG12,
	200	+ .fmt_type = FMT_BAYER,
	201	+ .bpp = { 12 },
	202	+ .mplanes = 1,
	203	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	204	+ .output_format = 0,
	205	+ }, {
	206	+ .fourcc = V4L2_PIX_FMT_SBGGR12,
	207	+ .fmt_type = FMT_BAYER,
	208	+ .bpp = { 12 },
	209	+ .mplanes = 1,
	210	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	211	+ .output_format = 0,
	212	+ },
	213	+};
	214	+
	215	+static const struct capture_fmt sp_fmts[] = {
	216	+ /* yuv422 */
	217	+ {
	218	+ .fourcc = V4L2_PIX_FMT_UYVY,
	219	+ .fmt_type = FMT_YUV,
	220	+ .bpp = { 16 },
	221	+ .cplanes = 1,
	222	+ .mplanes = 1,
	223	+ .uv_swap = 0,
	224	+ .write_format = MI_CTRL_SP_WRITE_INT,
	225	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	226	+ }, {
	227	+ .fourcc = V4L2_PIX_FMT_YUV422P,
	228	+ .fmt_type = FMT_YUV,
	229	+ .bpp = { 8, 8, 8 },
	230	+ .cplanes = 3,
	231	+ .mplanes = 1,
	232	+ .uv_swap = 0,
	233	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	234	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	235	+ }, {
	236	+ .fourcc = V4L2_PIX_FMT_NV16,
	237	+ .fmt_type = FMT_YUV,
	238	+ .bpp = { 8, 16 },
	239	+ .cplanes = 2,
	240	+ .mplanes = 1,
	241	+ .uv_swap = 0,
	242	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	243	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	244	+ }, {
	245	+ .fourcc = V4L2_PIX_FMT_NV61,
	246	+ .fmt_type = FMT_YUV,
	247	+ .bpp = { 8, 16 },
	248	+ .cplanes = 2,
	249	+ .mplanes = 1,
	250	+ .uv_swap = 1,
	251	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	252	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	253	+ }, {
	254	+ .fourcc = V4L2_PIX_FMT_YUV422M,
	255	+ .fmt_type = FMT_YUV,
	256	+ .bpp = { 8, 8, 8 },
	257	+ .cplanes = 3,
	258	+ .mplanes = 3,
	259	+ .uv_swap = 0,
	260	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	261	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	262	+ },
	263	+ /* yuv420 */
	264	+ {
	265	+ .fourcc = V4L2_PIX_FMT_NV21,
	266	+ .fmt_type = FMT_YUV,
	267	+ .bpp = { 8, 16 },
	268	+ .cplanes = 2,
	269	+ .mplanes = 1,
	270	+ .uv_swap = 1,
	271	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	272	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	273	+ }, {
	274	+ .fourcc = V4L2_PIX_FMT_NV12,
	275	+ .fmt_type = FMT_YUV,
	276	+ .bpp = { 8, 16 },
	277	+ .cplanes = 2,
	278	+ .mplanes = 1,
	279	+ .uv_swap = 0,
	280	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	281	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	282	+ }, {
	283	+ .fourcc = V4L2_PIX_FMT_NV21M,
	284	+ .fmt_type = FMT_YUV,
	285	+ .bpp = { 8, 16 },
	286	+ .cplanes = 2,
	287	+ .mplanes = 2,
	288	+ .uv_swap = 1,
	289	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	290	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	291	+ }, {
	292	+ .fourcc = V4L2_PIX_FMT_NV12M,
	293	+ .fmt_type = FMT_YUV,
	294	+ .bpp = { 8, 16 },
	295	+ .cplanes = 2,
	296	+ .mplanes = 2,
	297	+ .uv_swap = 0,
	298	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	299	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	300	+ }, {
	301	+ .fourcc = V4L2_PIX_FMT_YUV420,
	302	+ .fmt_type = FMT_YUV,
	303	+ .bpp = { 8, 8, 8 },
	304	+ .cplanes = 3,
	305	+ .mplanes = 1,
	306	+ .uv_swap = 0,
	307	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	308	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	309	+ },
	310	+ /* yuv444 */
	311	+ {
	312	+ .fourcc = V4L2_PIX_FMT_YUV444M,
	313	+ .fmt_type = FMT_YUV,
	314	+ .bpp = { 8, 8, 8 },
	315	+ .cplanes = 3,
	316	+ .mplanes = 3,
	317	+ .uv_swap = 0,
	318	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	319	+ .output_format = MI_CTRL_SP_OUTPUT_YUV444,
	320	+ },
	321	+ /* yuv400 */
	322	+ {
	323	+ .fourcc = V4L2_PIX_FMT_GREY,
	324	+ .fmt_type = FMT_YUV,
	325	+ .bpp = { 8 },
	326	+ .cplanes = 1,
	327	+ .mplanes = 1,
	328	+ .uv_swap = 0,
	329	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	330	+ .output_format = MI_CTRL_SP_OUTPUT_YUV400,
	331	+ },
	332	+ /* rgb */
	333	+ {
	334	+ .fourcc = V4L2_PIX_FMT_XBGR32,
	335	+ .fmt_type = FMT_RGB,
	336	+ .bpp = { 32 },
	337	+ .mplanes = 1,
	338	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	339	+ .output_format = MI_CTRL_SP_OUTPUT_RGB888,
	340	+ }, {
	341	+ .fourcc = V4L2_PIX_FMT_RGB565,
	342	+ .fmt_type = FMT_RGB,
	343	+ .bpp = { 16 },
	344	+ .mplanes = 1,
	345	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	346	+ .output_format = MI_CTRL_SP_OUTPUT_RGB565,
	347	+ },
	348	+};
21	349	static const struct capture_fmt dmatx_fmts[] = {
22	350	/* raw */
23	351	{
..	..	@@ -392,7 +720,7 @@
392	720	stream->out_isp_fmt.write_format, false);
393	721	mi_frame_end_int_enable(stream);
394	722	/* set up first buffer */
395		- mi_frame_end(stream);
	723	+ mi_frame_end(stream, FRAME_INIT);
396	724	return 0;
397	725	}
398	726
..	..	@@ -466,7 +794,7 @@
466	794	CIF_MI_SP_AUTOUPDATE_ENABLE, false);
467	795	mi_frame_end_int_enable(stream);
468	796	/* set up first buffer */
469		- mi_frame_end(stream);
	797	+ mi_frame_end(stream, FRAME_INIT);
470	798	return 0;
471	799	}
472	800
..	..	@@ -483,7 +811,7 @@
483	811
484	812	if (!dev->active_sensor \|\|
485	813	(dev->active_sensor &&
486		- dev->active_sensor->mbus.type != V4L2_MBUS_CSI2)) {
	814	+ dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
487	815	v4l2_err(&dev->v4l2_dev,
488	816	"only mipi sensor support rawwr3\n");
489	817	return -EINVAL;
..	..	@@ -495,7 +823,7 @@
495	823	stream->out_fmt.height);
496	824	raw_wr_set_pic_offs(stream, 0);
497	825	mi_set_y_size(stream, in_size);
498		- mi_frame_end(stream);
	826	+ mi_frame_end(stream, FRAME_INIT);
499	827	mi_frame_end_int_enable(stream);
500	828	mi_wr_ctrl2(base, SW_RAW3_WR_AUTOUPD);
501	829	mi_raw_length(stream);
..	..	@@ -526,7 +854,7 @@
526	854
527	855	if (!dev->active_sensor \|\|
528	856	(dev->active_sensor &&
529		- dev->active_sensor->mbus.type != V4L2_MBUS_CSI2)) {
	857	+ dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
530	858	v4l2_err(&dev->v4l2_dev,
531	859	"only mipi sensor support rawwr2 path\n");
532	860	return -EINVAL;
..	..	@@ -541,7 +869,7 @@
541	869	stream->out_fmt.height);
542	870	raw_wr_set_pic_offs(stream, 0);
543	871	mi_set_y_size(stream, in_size);
544		- mi_frame_end(stream);
	872	+ mi_frame_end(stream, FRAME_INIT);
545	873	mi_frame_end_int_enable(stream);
546	874	mi_wr_ctrl2(base, SW_RAW1_WR_AUTOUPD);
547	875	mi_raw_length(stream);
..	..	@@ -571,7 +899,7 @@
571	899
572	900	if (!dev->active_sensor \|\|
573	901	(dev->active_sensor &&
574		- dev->active_sensor->mbus.type != V4L2_MBUS_CSI2)) {
	902	+ dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
575	903	if (stream->id == RKISP_STREAM_DMATX0)
576	904	v4l2_err(&dev->v4l2_dev,
577	905	"only mipi sensor support rawwr0 path\n");
..	..	@@ -587,7 +915,7 @@
587	915	stream->out_fmt.height);
588	916	raw_wr_set_pic_offs(stream, 0);
589	917	mi_set_y_size(stream, in_size);
590		- mi_frame_end(stream);
	918	+ mi_frame_end(stream, FRAME_INIT);
591	919	mi_frame_end_int_enable(stream);
592	920	mi_wr_ctrl2(base, SW_RAW0_WR_AUTOUPD);
593	921	mi_raw_length(stream);
..	..	@@ -618,8 +946,15 @@
618	946
619	947	static void sp_enable_mi(struct rkisp_stream *stream)
620	948	{
621		- rkisp_set_bits(stream->ispdev, CIF_MI_CTRL, 0,
622		- CIF_MI_CTRL_SP_ENABLE, false);
	949	+ struct rkisp_device *dev = stream->ispdev;
	950	+ struct capture_fmt *fmt = &stream->out_isp_fmt;
	951	+ u32 val = CIF_MI_CTRL_SP_ENABLE;
	952	+ u32 mask = CIF_MI_SP_Y_FULL_YUV2RGB \| CIF_MI_SP_CBCR_FULL_YUV2RGB;
	953	+
	954	+ if (fmt->fmt_type == FMT_RGB &&
	955	+ dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
	956	+ val \|= mask;
	957	+ rkisp_set_bits(stream->ispdev, CIF_MI_CTRL, mask, val, false);
623	958	}
624	959
625	960	static void dmatx_enable_mi(struct rkisp_stream *stream)
..	..	@@ -739,7 +1074,7 @@
739	1074	.enable_mi = mp_enable_mi,
740	1075	.disable_mi = mp_disable_mi,
741	1076	.stop_mi = mp_stop_mi,
742		- .set_data_path = mp_set_data_path,
	1077	+ .set_data_path = stream_data_path,
743	1078	.is_stream_stopped = mp_is_stream_stopped,
744	1079	.update_mi = update_mi,
745	1080	.frame_end = mi_frame_end,
..	..	@@ -750,7 +1085,7 @@
750	1085	.enable_mi = sp_enable_mi,
751	1086	.disable_mi = sp_disable_mi,
752	1087	.stop_mi = sp_stop_mi,
753		- .set_data_path = sp_set_data_path,
	1088	+ .set_data_path = stream_data_path,
754	1089	.is_stream_stopped = sp_is_stream_stopped,
755	1090	.update_mi = update_mi,
756	1091	.frame_end = mi_frame_end,
..	..	@@ -797,7 +1132,7 @@
797	1132	return;
798	1133
799	1134	if (isp_dev->hdr.op_mode == HDR_RDBK_FRAME1) {
800		- vb2_buffer_done(&cap->rdbk_buf[RDBK_S]->vb.vb2_buf, VB2_BUF_STATE_DONE);
	1135	+ rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
801	1136	cap->rdbk_buf[RDBK_S] = NULL;
802	1137	return;
803	1138	}
..	..	@@ -834,12 +1169,9 @@
834	1169	goto RDBK_FRM_UNMATCH;
835	1170	}
836	1171
837		- cap->rdbk_buf[RDBK_S]->vb.sequence =
838		- cap->rdbk_buf[RDBK_L]->vb.sequence;
839		- vb2_buffer_done(&cap->rdbk_buf[RDBK_L]->vb.vb2_buf,
840		- VB2_BUF_STATE_DONE);
841		- vb2_buffer_done(&cap->rdbk_buf[RDBK_S]->vb.vb2_buf,
842		- VB2_BUF_STATE_DONE);
	1172	+ cap->rdbk_buf[RDBK_S]->vb.sequence = cap->rdbk_buf[RDBK_L]->vb.sequence;
	1173	+ rkisp_stream_buf_done(&cap->stream[RKISP_STREAM_DMATX0], cap->rdbk_buf[RDBK_L]);
	1174	+ rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
843	1175	} else {
844	1176	v4l2_err(&isp_dev->v4l2_dev, "lost long frames\n");
845	1177	goto RDBK_FRM_UNMATCH;
..	..	@@ -865,7 +1197,7 @@
865	1197	* is processing and we should set up buffer for next-next frame,
866	1198	* otherwise it will overflow.
867	1199	*/
868		-static int mi_frame_end(struct rkisp_stream *stream)
	1200	+static int mi_frame_end(struct rkisp_stream *stream, u32 state)
869	1201	{
870	1202	struct rkisp_device *dev = stream->ispdev;
871	1203	struct rkisp_capture_device *cap = &dev->cap_dev;
..	..	@@ -936,7 +1268,7 @@
936	1268	rdbk_frame_end(stream);
937	1269	}
938	1270	} else {
939		- vb2_buffer_done(vb2_buf, VB2_BUF_STATE_DONE);
	1271	+ rkisp_stream_buf_done(stream, stream->curr_buf);
940	1272	}
941	1273
942	1274	stream->curr_buf = NULL;
..	..	@@ -993,7 +1325,9 @@
993	1325	{
994	1326	struct rkisp_device *dev = stream->ispdev;
995	1327	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
	1328	+ unsigned long lock_flags = 0;
996	1329	int ret = 0;
	1330	+ bool is_wait = dev->hw_dev->is_shutdown ? false : true;
997	1331
998	1332	if (!dev->dmarx_dev.trigger &&
999	1333	(is_rdbk_stream(stream) \|\| is_hdr_stream(stream))) {
..	..	@@ -1006,11 +1340,20 @@
1006	1340	stream->id != RKISP_STREAM_SP) \|\| dev->hw_dev->is_single)
1007	1341	stream->ops->stop_mi(stream);
1008	1342
1009		- if (stream->id == RKISP_STREAM_MP \|\| stream->id == RKISP_STREAM_SP)
	1343	+ if (stream->id == RKISP_STREAM_MP \|\| stream->id == RKISP_STREAM_SP) {
1010	1344	hdr_stop_dmatx(dev);
1011		-
1012		- if (dev->isp_state & ISP_START &&
1013		- !stream->ops->is_stream_stopped(dev->base_addr)) {
	1345	+ if (IS_HDR_RDBK(dev->rd_mode) && !dev->hw_dev->is_single) {
	1346	+ spin_lock_irqsave(&dev->hw_dev->rdbk_lock, lock_flags);
	1347	+ if (dev->hw_dev->cur_dev_id != dev->dev_id \|\| dev->hw_dev->is_idle) {
	1348	+ is_wait = false;
	1349	+ stream->ops->disable_mi(stream);
	1350	+ }
	1351	+ if (atomic_read(&dev->cap_dev.refcnt) == 1 && !is_wait)
	1352	+ dev->isp_state = ISP_STOP;
	1353	+ spin_unlock_irqrestore(&dev->hw_dev->rdbk_lock, lock_flags);
	1354	+ }
	1355	+ }
	1356	+ if (is_wait && !stream->ops->is_stream_stopped(stream)) {
1014	1357	ret = wait_event_timeout(stream->done,
1015	1358	!stream->streaming,
1016	1359	msecs_to_jiffies(500));
..	..	@@ -1044,19 +1387,11 @@
1044	1387	*/
1045	1388	static int rkisp_start(struct rkisp_stream *stream)
1046	1389	{
1047		- void __iomem *base = stream->ispdev->base_addr;
1048	1390	struct rkisp_device *dev = stream->ispdev;
1049		- bool is_update = false;
1050	1391	int ret;
1051	1392
1052		- if (stream->id == RKISP_STREAM_MP \|\| stream->id == RKISP_STREAM_SP) {
1053		- is_update = (stream->id == RKISP_STREAM_MP) ?
1054		- !dev->cap_dev.stream[RKISP_STREAM_SP].streaming :
1055		- !dev->cap_dev.stream[RKISP_STREAM_MP].streaming;
1056		- }
1057		-
1058	1393	if (stream->ops->set_data_path)
1059		- stream->ops->set_data_path(base);
	1394	+ stream->ops->set_data_path(stream);
1060	1395	ret = stream->ops->config_mi(stream);
1061	1396	if (ret)
1062	1397	return ret;
..	..	@@ -1064,9 +1399,6 @@
1064	1399	stream->ops->enable_mi(stream);
1065	1400	if (stream->id == RKISP_STREAM_MP \|\| stream->id == RKISP_STREAM_SP)
1066	1401	hdr_config_dmatx(dev);
1067		- if (is_update)
1068		- dev->irq_ends_mask \|=
1069		- (stream->id == RKISP_STREAM_MP) ? ISP_FRAME_MP : ISP_FRAME_SP;
1070	1402	stream->streaming = true;
1071	1403
1072	1404	return 0;
..	..	@@ -1214,6 +1546,12 @@
1214	1546	list_del(&buf->queue);
1215	1547	vb2_buffer_done(&buf->vb.vb2_buf, state);
1216	1548	}
	1549	+ while (!list_empty(&stream->buf_done_list)) {
	1550	+ buf = list_first_entry(&stream->buf_done_list,
	1551	+ struct rkisp_buffer, queue);
	1552	+ list_del(&buf->queue);
	1553	+ vb2_buffer_done(&buf->vb.vb2_buf, state);
	1554	+ }
1217	1555	spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1218	1556	}
1219	1557
..	..	@@ -1252,7 +1590,7 @@
1252	1590	v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
1253	1591	rkisp_destroy_dummy_buf(stream);
1254	1592	atomic_dec(&dev->cap_dev.refcnt);
1255		-
	1593	+ tasklet_disable(&stream->buf_done_tasklet);
1256	1594	end:
1257	1595	mutex_unlock(&dev->hw_dev->dev_lock);
1258	1596	}
..	..	@@ -1378,7 +1716,7 @@
1378	1716	goto pipe_stream_off;
1379	1717	}
1380	1718	}
1381		-
	1719	+ tasklet_enable(&stream->buf_done_tasklet);
1382	1720	mutex_unlock(&dev->hw_dev->dev_lock);
1383	1721	return 0;
1384	1722
..	..	@@ -1445,7 +1783,7 @@
1445	1783	INIT_LIST_HEAD(&stream->buf_queue);
1446	1784	init_waitqueue_head(&stream->done);
1447	1785	spin_lock_init(&stream->vbq_lock);
1448		- stream->linked = MEDIA_LNK_FL_ENABLED;
	1786	+ stream->linked = true;
1449	1787
1450	1788	switch (id) {
1451	1789	case RKISP_STREAM_SP:
..	..	@@ -1453,6 +1791,8 @@
1453	1791	sizeof(vdev->name));
1454	1792	stream->ops = &rkisp_sp_streams_ops;
1455	1793	stream->config = &rkisp_sp_stream_config;
	1794	+ stream->config->fmts = sp_fmts;
	1795	+ stream->config->fmt_size = ARRAY_SIZE(sp_fmts);
1456	1796	break;
1457	1797	case RKISP_STREAM_DMATX0:
1458	1798	strlcpy(vdev->name, DMATX0_VDEV_NAME,
..	..	@@ -1477,6 +1817,8 @@
1477	1817	sizeof(vdev->name));
1478	1818	stream->ops = &rkisp_mp_streams_ops;
1479	1819	stream->config = &rkisp_mp_stream_config;
	1820	+ stream->config->fmts = mp_fmts;
	1821	+ stream->config->fmt_size = ARRAY_SIZE(mp_fmts);
1480	1822	}
1481	1823
1482	1824	node = vdev_to_node(vdev);
..	..	@@ -1588,7 +1930,7 @@
1588	1930	stream->streaming = false;
1589	1931	stream->ops->disable_mi(stream);
1590	1932	wake_up(&stream->done);
1591		- } else if (stream->ops->is_stream_stopped(dev->base_addr)) {
	1933	+ } else if (stream->ops->is_stream_stopped(stream)) {
1592	1934	stream->stopping = false;
1593	1935	stream->streaming = false;
1594	1936	wake_up(&stream->done);
..	..	@@ -1598,7 +1940,7 @@
1598	1940	end_tx2 = false;
1599	1941	}
1600	1942	} else {
1601		- mi_frame_end(stream);
	1943	+ mi_frame_end(stream, FRAME_IRQ);
1602	1944	if (dev->dmarx_dev.trigger == T_AUTO &&
1603	1945	((dev->hdr.op_mode == HDR_RDBK_FRAME1 && end_tx2) \|\|
1604	1946	(dev->hdr.op_mode == HDR_RDBK_FRAME2 && end_tx2 && end_tx0))) {
..	..	@@ -1613,16 +1955,12 @@
1613	1955	stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
1614	1956	if (!stream->streaming)
1615	1957	dev->irq_ends_mask &= ~ISP_FRAME_MP;
1616		- else
1617		- dev->irq_ends_mask \|= ISP_FRAME_MP;
1618	1958	rkisp_check_idle(dev, ISP_FRAME_MP);
1619	1959	}
1620	1960	if (mis_val & CIF_MI_SP_FRAME) {
1621	1961	stream = &dev->cap_dev.stream[RKISP_STREAM_SP];
1622	1962	if (!stream->streaming)
1623	1963	dev->irq_ends_mask &= ~ISP_FRAME_SP;
1624		- else
1625		- dev->irq_ends_mask \|= ISP_FRAME_SP;
1626	1964	rkisp_check_idle(dev, ISP_FRAME_SP);
1627	1965	}
1628	1966	}