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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/irqchip/irq-mips-gic.c
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@@ -46,17 +46,19 @@
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46
 
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 void __iomem *mips_gic_base;
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-DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
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+static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
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 static DEFINE_SPINLOCK(gic_lock);
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 static struct irq_domain *gic_irq_domain;
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-static struct irq_domain *gic_ipi_domain;
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 static int gic_shared_intrs;
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 static unsigned int gic_cpu_pin;
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 static unsigned int timer_cpu_pin;
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 static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
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+
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+#ifdef CONFIG_GENERIC_IRQ_IPI
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 static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
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 static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
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+#endif /* CONFIG_GENERIC_IRQ_IPI */
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62
 
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 static struct gic_all_vpes_chip_data {
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 	u32	map;
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@@ -459,9 +461,11 @@
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 	u32 map;
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 	if (hwirq >= GIC_SHARED_HWIRQ_BASE) {
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+#ifdef CONFIG_GENERIC_IRQ_IPI
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 		/* verify that shared irqs don't conflict with an IPI irq */
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 		if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv))
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 			return -EBUSY;
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+#endif /* CONFIG_GENERIC_IRQ_IPI */
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 		err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
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 						    &gic_level_irq_controller,
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@@ -480,7 +484,7 @@
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 	case GIC_LOCAL_INT_TIMER:
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 		/* CONFIG_MIPS_CMP workaround (see __gic_init) */
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 		map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
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-		/* fall-through */
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+		fallthrough;
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 	case GIC_LOCAL_INT_PERFCTR:
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 	case GIC_LOCAL_INT_FDC:
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 		/*
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@@ -550,6 +554,8 @@
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 	.map = gic_irq_domain_map,
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 };
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+#ifdef CONFIG_GENERIC_IRQ_IPI
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+
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 static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
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 				const u32 *intspec, unsigned int intsize,
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 				irq_hw_number_t *out_hwirq,
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@@ -617,8 +623,8 @@
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 	return ret;
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 }
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-void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
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-			 unsigned int nr_irqs)
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+static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
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+				unsigned int nr_irqs)
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 {
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 	irq_hw_number_t base_hwirq;
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 	struct irq_data *data;
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@@ -631,8 +637,8 @@
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 	bitmap_set(ipi_available, base_hwirq, nr_irqs);
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 }
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-int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
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-			 enum irq_domain_bus_token bus_token)
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+static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
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+				enum irq_domain_bus_token bus_token)
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 {
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 	bool is_ipi;
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@@ -653,6 +659,48 @@
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 	.match = gic_ipi_domain_match,
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 };
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+static int gic_register_ipi_domain(struct device_node *node)
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+{
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+	struct irq_domain *gic_ipi_domain;
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+	unsigned int v[2], num_ipis;
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+
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+	gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
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+						  IRQ_DOMAIN_FLAG_IPI_PER_CPU,
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+						  GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
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+						  node, &gic_ipi_domain_ops, NULL);
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+	if (!gic_ipi_domain) {
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+		pr_err("Failed to add IPI domain");
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+		return -ENXIO;
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+	}
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+
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+	irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
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+
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+	if (node &&
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+	    !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
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+		bitmap_set(ipi_resrv, v[0], v[1]);
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+	} else {
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+		/*
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+		 * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
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+		 * meeting the requirements of arch/mips SMP.
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+		 */
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+		num_ipis = 2 * num_possible_cpus();
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+		bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
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+	}
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+
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+	bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
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+
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+	return 0;
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+}
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+
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+#else /* !CONFIG_GENERIC_IRQ_IPI */
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+
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+static inline int gic_register_ipi_domain(struct device_node *node)
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+{
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+	return 0;
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+}
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+
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+#endif /* !CONFIG_GENERIC_IRQ_IPI */
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+
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 static int gic_cpu_startup(unsigned int cpu)
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 {
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 	/* Enable or disable EIC */
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@@ -671,11 +719,12 @@
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 static int __init gic_of_init(struct device_node *node,
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 			      struct device_node *parent)
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 {
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-	unsigned int cpu_vec, i, gicconfig, v[2], num_ipis;
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+	unsigned int cpu_vec, i, gicconfig;
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 	unsigned long reserved;
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 	phys_addr_t gic_base;
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 	struct resource res;
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 	size_t gic_len;
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+	int ret;
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 	/* Find the first available CPU vector. */
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 	i = 0;
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@@ -716,7 +765,11 @@
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 		__sync();
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 	}
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-	mips_gic_base = ioremap_nocache(gic_base, gic_len);
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+	mips_gic_base = ioremap(gic_base, gic_len);
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+	if (!mips_gic_base) {
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+		pr_err("Failed to ioremap gic_base\n");
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+		return -ENOMEM;
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+	}
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 	gicconfig = read_gic_config();
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 	gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS;
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@@ -764,30 +817,9 @@
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 		return -ENXIO;
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 	}
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-	gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
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-						  IRQ_DOMAIN_FLAG_IPI_PER_CPU,
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-						  GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
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-						  node, &gic_ipi_domain_ops, NULL);
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-	if (!gic_ipi_domain) {
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-		pr_err("Failed to add IPI domain");
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-		return -ENXIO;
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-	}
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-
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-	irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
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-
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-	if (node &&
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-	    !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
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-		bitmap_set(ipi_resrv, v[0], v[1]);
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-	} else {
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-		/*
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-		 * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
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-		 * meeting the requirements of arch/mips SMP.
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-		 */
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-		num_ipis = 2 * num_possible_cpus();
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-		bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
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-	}
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-
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-	bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
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+	ret = gic_register_ipi_domain(node);
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+	if (ret)
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+		return ret;
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 	board_bind_eic_interrupt = &gic_bind_eic_interrupt;
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