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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/irqchip/irq-gic.c
....@@ -1,9 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
74  *
85  * Interrupt architecture for the GIC:
96  *
....@@ -86,9 +83,6 @@
8683 #endif
8784 	struct irq_domain *domain;
8885 	unsigned int gic_irqs;
89
-#ifdef CONFIG_GIC_NON_BANKED
90
-	void __iomem *(*get_base)(union gic_base *);
91
-#endif
9286 };
9387 
9488 #ifdef CONFIG_BL_SWITCHER
....@@ -113,6 +107,8 @@
113107 
114108 #endif
115109 
110
+static DEFINE_STATIC_KEY_FALSE(needs_rmw_access);
111
+
116112 /*
117113  * The GIC mapping of CPU interfaces does not necessarily match
118114  * the logical CPU numbering.  Let's use a mapping as returned
....@@ -127,36 +123,30 @@
127123 
128124 static struct gic_kvm_info gic_v2_kvm_info;
129125 
126
+static DEFINE_PER_CPU(u32, sgi_intid);
127
+
130128 #ifdef CONFIG_GIC_NON_BANKED
131
-static void __iomem *gic_get_percpu_base(union gic_base *base)
129
+static DEFINE_STATIC_KEY_FALSE(frankengic_key);
130
+
131
+static void enable_frankengic(void)
132132 {
133
-	return raw_cpu_read(*base->percpu_base);
133
+	static_branch_enable(&frankengic_key);
134134 }
135135 
136
-static void __iomem *gic_get_common_base(union gic_base *base)
136
+static inline void __iomem *__get_base(union gic_base *base)
137137 {
138
+	if (static_branch_unlikely(&frankengic_key))
139
+		return raw_cpu_read(*base->percpu_base);
140
+
138141 	return base->common_base;
139142 }
140143 
141
-static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
142
-{
143
-	return data->get_base(&data->dist_base);
144
-}
145
-
146
-static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
147
-{
148
-	return data->get_base(&data->cpu_base);
149
-}
150
-
151
-static inline void gic_set_base_accessor(struct gic_chip_data *data,
152
-					 void __iomem *(*f)(union gic_base *))
153
-{
154
-	data->get_base = f;
155
-}
144
+#define gic_data_dist_base(d)	__get_base(&(d)->dist_base)
145
+#define gic_data_cpu_base(d)	__get_base(&(d)->cpu_base)
156146 #else
157147 #define gic_data_dist_base(d)	((d)->dist_base.common_base)
158148 #define gic_data_cpu_base(d)	((d)->cpu_base.common_base)
159
-#define gic_set_base_accessor(d, f)
149
+#define enable_frankengic()	do { } while(0)
160150 #endif
161151 
162152 static inline void __iomem *gic_dist_base(struct irq_data *d)
....@@ -227,27 +217,28 @@
227217 	gic_poke_irq(d, GIC_DIST_ENABLE_SET);
228218 }
229219 
230
-#ifdef CONFIG_ARCH_ROCKCHIP
231
-static int gic_retrigger(struct irq_data *d)
232
-{
233
-	gic_poke_irq(d, GIC_DIST_PENDING_SET);
234
-	/* the genirq layer expects 0 if we can't retrigger in hardware */
235
-	return 0;
236
-}
237
-#endif
238
-
239220 static void gic_eoi_irq(struct irq_data *d)
240221 {
241
-	writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
222
+	u32 hwirq = gic_irq(d);
223
+
224
+	if (hwirq < 16)
225
+		hwirq = this_cpu_read(sgi_intid);
226
+
227
+	writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI);
242228 }
243229 
244230 static void gic_eoimode1_eoi_irq(struct irq_data *d)
245231 {
232
+	u32 hwirq = gic_irq(d);
233
+
246234 	/* Do not deactivate an IRQ forwarded to a vcpu. */
247235 	if (irqd_is_forwarded_to_vcpu(d))
248236 		return;
249237 
250
-	writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
238
+	if (hwirq < 16)
239
+		hwirq = this_cpu_read(sgi_intid);
240
+
241
+	writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
251242 }
252243 
253244 static int gic_irq_set_irqchip_state(struct irq_data *d,
....@@ -303,23 +294,31 @@
303294 {
304295 	void __iomem *base = gic_dist_base(d);
305296 	unsigned int gicirq = gic_irq(d);
297
+	int ret;
306298 
307299 	/* Interrupt configuration for SGIs can't be changed */
308300 	if (gicirq < 16)
309
-		return -EINVAL;
301
+		return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
310302 
311303 	/* SPIs have restrictions on the supported types */
312304 	if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
313305 			    type != IRQ_TYPE_EDGE_RISING)
314306 		return -EINVAL;
315307 
316
-	return gic_configure_irq(gicirq, type, base, NULL);
308
+	ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
309
+	if (ret && gicirq < 32) {
310
+		/* Misconfigured PPIs are usually not fatal */
311
+		pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);
312
+		ret = 0;
313
+	}
314
+
315
+	return ret;
317316 }
318317 
319318 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
320319 {
321320 	/* Only interrupts on the primary GIC can be forwarded to a vcpu. */
322
-	if (cascading_gic_irq(d))
321
+	if (cascading_gic_irq(d) || gic_irq(d) < 16)
323322 		return -EINVAL;
324323 
325324 	if (vcpu)
....@@ -329,27 +328,10 @@
329328 	return 0;
330329 }
331330 
332
-#ifdef CONFIG_SMP
333
-static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
334
-			    bool force)
331
+static int gic_retrigger(struct irq_data *data)
335332 {
336
-	void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
337
-	unsigned int cpu;
338
-
339
-	if (!force)
340
-		cpu = cpumask_any_and(mask_val, cpu_online_mask);
341
-	else
342
-		cpu = cpumask_first(mask_val);
343
-
344
-	if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
345
-		return -EINVAL;
346
-
347
-	writeb_relaxed(gic_cpu_map[cpu], reg);
348
-	irq_data_update_effective_affinity(d, cpumask_of(cpu));
349
-
350
-	return IRQ_SET_MASK_OK_DONE;
333
+	return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
351334 }
352
-#endif
353335 
354336 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
355337 {
....@@ -358,34 +340,40 @@
358340 	void __iomem *cpu_base = gic_data_cpu_base(gic);
359341 
360342 	do {
343
+#ifdef CONFIG_FIQ_GLUE
344
+		irqstat = readl_relaxed(cpu_base + GIC_CPU_ALIAS_INTACK);
345
+#else
361346 		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
347
+#endif
362348 		irqnr = irqstat & GICC_IAR_INT_ID_MASK;
363349 
364
-		if (likely(irqnr > 15 && irqnr < 1020)) {
365
-			if (static_branch_likely(&supports_deactivate_key))
366
-				writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
367
-			isb();
368
-			handle_domain_irq(gic->domain, irqnr, regs);
369
-			continue;
370
-		}
371
-		if (irqnr < 16) {
350
+		if (unlikely(irqnr >= 1020))
351
+			break;
352
+
353
+		if (static_branch_likely(&supports_deactivate_key))
372354 			writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
373
-			if (static_branch_likely(&supports_deactivate_key))
374
-				writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
375
-#ifdef CONFIG_SMP
376
-			/*
377
-			 * Ensure any shared data written by the CPU sending
378
-			 * the IPI is read after we've read the ACK register
379
-			 * on the GIC.
380
-			 *
381
-			 * Pairs with the write barrier in gic_raise_softirq
382
-			 */
355
+		isb();
356
+
357
+		/*
358
+		 * Ensure any shared data written by the CPU sending the IPI
359
+		 * is read after we've read the ACK register on the GIC.
360
+		 *
361
+		 * Pairs with the write barrier in gic_ipi_send_mask
362
+		 */
363
+		if (irqnr <= 15) {
383364 			smp_rmb();
384
-			handle_IPI(irqnr, regs);
385
-#endif
386
-			continue;
365
+
366
+			/*
367
+			 * The GIC encodes the source CPU in GICC_IAR,
368
+			 * leading to the deactivation to fail if not
369
+			 * written back as is to GICC_EOI.  Stash the INTID
370
+			 * away for gic_eoi_irq() to write back.  This only
371
+			 * works because we don't nest SGIs...
372
+			 */
373
+			this_cpu_write(sgi_intid, irqstat);
387374 		}
388
-		break;
375
+
376
+		handle_domain_irq(gic->domain, irqnr, regs);
389377 	} while (1);
390378 }
391379 
....@@ -397,9 +385,11 @@
397385 	unsigned long status;
398386 
399387 	chained_irq_enter(chip, desc);
400
-
388
+#ifdef CONFIG_FIQ_GLUE
389
+	status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_ALIAS_INTACK);
390
+#else
401391 	status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
402
-
392
+#endif
403393 	gic_irq = (status & GICC_IAR_INT_ID_MASK);
404394 	if (gic_irq == GICC_INT_SPURIOUS)
405395 		goto out;
....@@ -421,9 +411,7 @@
421411 	.irq_unmask		= gic_unmask_irq,
422412 	.irq_eoi		= gic_eoi_irq,
423413 	.irq_set_type		= gic_set_type,
424
-#ifdef CONFIG_ARCH_ROCKCHIP
425414 	.irq_retrigger          = gic_retrigger,
426
-#endif
427415 	.irq_get_irqchip_state	= gic_irq_get_irqchip_state,
428416 	.irq_set_irqchip_state	= gic_irq_set_irqchip_state,
429417 	.flags			= IRQCHIP_SET_TYPE_MASKED |
....@@ -483,7 +471,11 @@
483471 	bypass = readl(cpu_base + GIC_CPU_CTRL);
484472 	bypass &= GICC_DIS_BYPASS_MASK;
485473 
474
+#ifdef CONFIG_FIQ_GLUE
475
+	writel_relaxed(0x0f, cpu_base + GIC_CPU_CTRL);
476
+#else
486477 	writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
478
+#endif
487479 }
488480 
489481 
....@@ -507,7 +499,15 @@
507499 
508500 	gic_dist_config(base, gic_irqs, NULL);
509501 
502
+#ifdef CONFIG_FIQ_GLUE
503
+	/* set all the interrupt to non-secure state */
504
+	for (i = 0; i < gic_irqs; i += 32)
505
+		writel_relaxed(0xffffffff, base + GIC_DIST_IGROUP + i * 4 / 32);
506
+	dsb(sy);
507
+	writel_relaxed(3, base + GIC_DIST_CTRL);
508
+#else
510509 	writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
510
+#endif
511511 }
512512 
513513 static int gic_cpu_init(struct gic_chip_data *gic)
....@@ -542,7 +542,7 @@
542542 				gic_cpu_map[i] &= ~cpu_mask;
543543 	}
544544 
545
-	gic_cpu_config(dist_base, NULL);
545
+	gic_cpu_config(dist_base, 32, NULL);
546546 
547547 	writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
548548 	gic_cpu_if_up(gic);
....@@ -608,8 +608,8 @@
608608 /*
609609  * Restores the GIC distributor registers during resume or when coming out of
610610  * idle.  Must be called before enabling interrupts.  If a level interrupt
611
- * that occured while the GIC was suspended is still present, it will be
612
- * handled normally, but any edge interrupts that occured will not be seen by
611
+ * that occurred while the GIC was suspended is still present, it will be
612
+ * handled normally, but any edge interrupts that occurred will not be seen by
613613  * the GIC and need to be handled by the platform-specific wakeup source.
614614  */
615615 void gic_dist_restore(struct gic_chip_data *gic)
....@@ -655,7 +655,11 @@
655655 			dist_base + GIC_DIST_ACTIVE_SET + i * 4);
656656 	}
657657 
658
+#ifdef CONFIG_FIQ_GLUE
659
+	writel_relaxed(3, dist_base + GIC_DIST_CTRL);
660
+#else
658661 	writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
662
+#endif
659663 }
660664 
661665 void gic_cpu_save(struct gic_chip_data *gic)
....@@ -735,11 +739,6 @@
735739 	int i;
736740 
737741 	for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
738
-#ifdef CONFIG_GIC_NON_BANKED
739
-		/* Skip over unused GICs */
740
-		if (!gic_data[i].get_base)
741
-			continue;
742
-#endif
743742 		switch (cmd) {
744743 		case CPU_PM_ENTER:
745744 			gic_cpu_save(&gic_data[i]);
....@@ -801,15 +800,78 @@
801800 }
802801 #endif
803802 
803
+#ifdef CONFIG_FIQ_GLUE
804
+/*
805
+ *	ICDISR each bit   0 -- Secure   1--Non-Secure
806
+ */
807
+void gic_set_irq_secure(struct irq_data *d)
808
+{
809
+	u32 mask = 0;
810
+	void __iomem *base = gic_dist_base(d);
811
+
812
+	base += GIC_DIST_IGROUP + ((gic_irq(d) / 32) * 4);
813
+	mask = readl_relaxed(base);
814
+	mask &= ~(1 << (gic_irq(d) % 32));
815
+	writel_relaxed(mask, base);
816
+}
817
+
818
+void gic_set_irq_priority(struct irq_data *d, u8 pri)
819
+{
820
+	writeb_relaxed(pri, gic_dist_base(d) + GIC_DIST_PRI + gic_irq(d));
821
+}
822
+#endif
823
+
804824 #ifdef CONFIG_SMP
805
-static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
825
+static void rmw_writeb(u8 bval, void __iomem *addr)
826
+{
827
+	static DEFINE_RAW_SPINLOCK(rmw_lock);
828
+	unsigned long offset = (unsigned long)addr & 3UL;
829
+	unsigned long shift = offset * 8;
830
+	unsigned long flags;
831
+	u32 val;
832
+
833
+	raw_spin_lock_irqsave(&rmw_lock, flags);
834
+
835
+	addr -= offset;
836
+	val = readl_relaxed(addr);
837
+	val &= ~GENMASK(shift + 7, shift);
838
+	val |= bval << shift;
839
+	writel_relaxed(val, addr);
840
+
841
+	raw_spin_unlock_irqrestore(&rmw_lock, flags);
842
+}
843
+
844
+static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
845
+			    bool force)
846
+{
847
+	void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
848
+	unsigned int cpu;
849
+
850
+	if (!force)
851
+		cpu = cpumask_any_and(mask_val, cpu_online_mask);
852
+	else
853
+		cpu = cpumask_first(mask_val);
854
+
855
+	if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
856
+		return -EINVAL;
857
+
858
+	if (static_branch_unlikely(&needs_rmw_access))
859
+		rmw_writeb(gic_cpu_map[cpu], reg);
860
+	else
861
+		writeb_relaxed(gic_cpu_map[cpu], reg);
862
+	irq_data_update_effective_affinity(d, cpumask_of(cpu));
863
+
864
+	return IRQ_SET_MASK_OK_DONE;
865
+}
866
+
867
+static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
806868 {
807869 	int cpu;
808870 	unsigned long flags, map = 0;
809871 
810872 	if (unlikely(nr_cpu_ids == 1)) {
811873 		/* Only one CPU? let's do a self-IPI... */
812
-		writel_relaxed(2 << 24 | irq,
874
+		writel_relaxed(2 << 24 | d->hwirq,
813875 			       gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
814876 		return;
815877 	}
....@@ -827,10 +889,51 @@
827889 	dmb(ishst);
828890 
829891 	/* this always happens on GIC0 */
830
-	writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
831
-
892
+#ifdef CONFIG_FIQ_GLUE
893
+	/* enable non-secure SGI for GIC with security extensions */
894
+	writel_relaxed(map << 16 | d->hwirq | 0x8000,
895
+			gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
896
+#else
897
+	writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
898
+#endif
832899 	gic_unlock_irqrestore(flags);
833900 }
901
+
902
+static int gic_starting_cpu(unsigned int cpu)
903
+{
904
+	gic_cpu_init(&gic_data[0]);
905
+	if (IS_ENABLED(CONFIG_FIQ_GLUE)) {
906
+		/* set SGI to none secure state */
907
+		writel_relaxed(0xffffffff, gic_data_dist_base(&gic_data[0]) + GIC_DIST_IGROUP);
908
+		writel_relaxed(0xf, gic_data_cpu_base(&gic_data[0]) + GIC_CPU_CTRL);
909
+	}
910
+	return 0;
911
+}
912
+
913
+static __init void gic_smp_init(void)
914
+{
915
+	struct irq_fwspec sgi_fwspec = {
916
+		.fwnode		= gic_data[0].domain->fwnode,
917
+		.param_count	= 1,
918
+	};
919
+	int base_sgi;
920
+
921
+	cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
922
+				  "irqchip/arm/gic:starting",
923
+				  gic_starting_cpu, NULL);
924
+
925
+	base_sgi = __irq_domain_alloc_irqs(gic_data[0].domain, -1, 8,
926
+					   NUMA_NO_NODE, &sgi_fwspec,
927
+					   false, NULL);
928
+	if (WARN_ON(base_sgi <= 0))
929
+		return;
930
+
931
+	set_smp_ipi_range(base_sgi, 8);
932
+}
933
+#else
934
+#define gic_smp_init()		do { } while(0)
935
+#define gic_set_affinity	NULL
936
+#define gic_ipi_send_mask	NULL
834937 #endif
835938 
836939 #ifdef CONFIG_BL_SWITCHER
....@@ -903,7 +1006,7 @@
9031006 	gic_cpu_map[cpu] = 1 << new_cpu_id;
9041007 
9051008 	/*
906
-	 * Find all the peripheral interrupts targetting the current
1009
+	 * Find all the peripheral interrupts targeting the current
9071010 	 * CPU interface and migrate them to the new CPU interface.
9081011 	 * We skip DIST_TARGET 0 to 7 as they are read-only.
9091012 	 */
....@@ -976,18 +1079,30 @@
9761079 				irq_hw_number_t hw)
9771080 {
9781081 	struct gic_chip_data *gic = d->host_data;
1082
+	struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
9791083 
980
-	if (hw < 32) {
1084
+	switch (hw) {
1085
+	case 0 ... 15:
1086
+		irq_set_percpu_devid(irq);
1087
+		irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
1088
+				    handle_percpu_devid_fasteoi_ipi,
1089
+				    NULL, NULL);
1090
+		break;
1091
+	case 16 ... 31:
9811092 		irq_set_percpu_devid(irq);
9821093 		irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
9831094 				    handle_percpu_devid_irq, NULL, NULL);
984
-		irq_set_status_flags(irq, IRQ_NOAUTOEN);
985
-	} else {
1095
+		break;
1096
+	default:
9861097 		irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
9871098 				    handle_fasteoi_irq, NULL, NULL);
9881099 		irq_set_probe(irq);
989
-		irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
1100
+		irqd_set_single_target(irqd);
1101
+		break;
9901102 	}
1103
+
1104
+	/* Prevents SW retriggers which mess up the ACK/EOI ordering */
1105
+	irqd_set_handle_enforce_irqctx(irqd);
9911106 	return 0;
9921107 }
9931108 
....@@ -1000,19 +1115,26 @@
10001115 				    unsigned long *hwirq,
10011116 				    unsigned int *type)
10021117 {
1118
+	if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1119
+		*hwirq = fwspec->param[0];
1120
+		*type = IRQ_TYPE_EDGE_RISING;
1121
+		return 0;
1122
+	}
1123
+
10031124 	if (is_of_node(fwspec->fwnode)) {
10041125 		if (fwspec->param_count < 3)
10051126 			return -EINVAL;
10061127 
1007
-		/* Get the interrupt number and add 16 to skip over SGIs */
1008
-		*hwirq = fwspec->param[1] + 16;
1009
-
1010
-		/*
1011
-		 * For SPIs, we need to add 16 more to get the GIC irq
1012
-		 * ID number
1013
-		 */
1014
-		if (!fwspec->param[0])
1015
-			*hwirq += 16;
1128
+		switch (fwspec->param[0]) {
1129
+		case 0:			/* SPI */
1130
+			*hwirq = fwspec->param[1] + 32;
1131
+			break;
1132
+		case 1:			/* PPI */
1133
+			*hwirq = fwspec->param[1] + 16;
1134
+			break;
1135
+		default:
1136
+			return -EINVAL;
1137
+		}
10161138 
10171139 		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
10181140 
....@@ -1025,6 +1147,12 @@
10251147 		if(fwspec->param_count != 2)
10261148 			return -EINVAL;
10271149 
1150
+		if (fwspec->param[0] < 16) {
1151
+			pr_err(FW_BUG "Illegal GSI%d translation request\n",
1152
+			       fwspec->param[0]);
1153
+			return -EINVAL;
1154
+		}
1155
+
10281156 		*hwirq = fwspec->param[0];
10291157 		*type = fwspec->param[1];
10301158 
....@@ -1033,12 +1161,6 @@
10331161 	}
10341162 
10351163 	return -EINVAL;
1036
-}
1037
-
1038
-static int gic_starting_cpu(unsigned int cpu)
1039
-{
1040
-	gic_cpu_init(&gic_data[0]);
1041
-	return 0;
10421164 }
10431165 
10441166 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
....@@ -1085,22 +1207,18 @@
10851207 		gic->chip.irq_mask = gic_eoimode1_mask_irq;
10861208 		gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
10871209 		gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1088
-#ifdef CONFIG_ARCH_ROCKCHIP
1089
-		gic->chip.irq_retrigger = gic_retrigger;
1090
-#endif
10911210 	}
10921211 
1093
-#ifdef CONFIG_SMP
1094
-	if (gic == &gic_data[0])
1212
+	if (gic == &gic_data[0]) {
10951213 		gic->chip.irq_set_affinity = gic_set_affinity;
1096
-#endif
1214
+		gic->chip.ipi_send_mask = gic_ipi_send_mask;
1215
+	}
10971216 }
10981217 
1099
-static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
1218
+static int gic_init_bases(struct gic_chip_data *gic,
11001219 			  struct fwnode_handle *handle)
11011220 {
1102
-	irq_hw_number_t hwirq_base;
1103
-	int gic_irqs, irq_base, ret;
1221
+	int gic_irqs, ret;
11041222 
11051223 	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
11061224 		/* Frankein-GIC without banked registers... */
....@@ -1124,7 +1242,7 @@
11241242 				gic->raw_cpu_base + offset;
11251243 		}
11261244 
1127
-		gic_set_base_accessor(gic, gic_get_percpu_base);
1245
+		enable_frankengic();
11281246 	} else {
11291247 		/* Normal, sane GIC... */
11301248 		WARN(gic->percpu_offset,
....@@ -1132,7 +1250,6 @@
11321250 		     gic->percpu_offset);
11331251 		gic->dist_base.common_base = gic->raw_dist_base;
11341252 		gic->cpu_base.common_base = gic->raw_cpu_base;
1135
-		gic_set_base_accessor(gic, gic_get_common_base);
11361253 	}
11371254 
11381255 	/*
....@@ -1152,28 +1269,21 @@
11521269 	} else {		/* Legacy support */
11531270 		/*
11541271 		 * For primary GICs, skip over SGIs.
1155
-		 * For secondary GICs, skip over PPIs, too.
1272
+		 * No secondary GIC support whatsoever.
11561273 		 */
1157
-		if (gic == &gic_data[0] && (irq_start & 31) > 0) {
1158
-			hwirq_base = 16;
1159
-			if (irq_start != -1)
1160
-				irq_start = (irq_start & ~31) + 16;
1161
-		} else {
1162
-			hwirq_base = 32;
1163
-		}
1274
+		int irq_base;
11641275 
1165
-		gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1276
+		gic_irqs -= 16; /* calculate # of irqs to allocate */
11661277 
1167
-		irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1278
+		irq_base = irq_alloc_descs(16, 16, gic_irqs,
11681279 					   numa_node_id());
11691280 		if (irq_base < 0) {
1170
-			WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1171
-			     irq_start);
1172
-			irq_base = irq_start;
1281
+			WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");
1282
+			irq_base = 16;
11731283 		}
11741284 
11751285 		gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1176
-					hwirq_base, &gic_irq_domain_ops, gic);
1286
+						    16, &gic_irq_domain_ops, gic);
11771287 	}
11781288 
11791289 	if (WARN_ON(!gic->domain)) {
....@@ -1202,7 +1312,6 @@
12021312 }
12031313 
12041314 static int __init __gic_init_bases(struct gic_chip_data *gic,
1205
-				   int irq_start,
12061315 				   struct fwnode_handle *handle)
12071316 {
12081317 	char *name;
....@@ -1219,12 +1328,7 @@
12191328 		 */
12201329 		for (i = 0; i < NR_GIC_CPU_IF; i++)
12211330 			gic_cpu_map[i] = 0xff;
1222
-#ifdef CONFIG_SMP
1223
-		set_smp_cross_call(gic_raise_softirq);
1224
-#endif
1225
-		cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1226
-					  "irqchip/arm/gic:starting",
1227
-					  gic_starting_cpu, NULL);
1331
+
12281332 		set_handle_irq(gic_handle_irq);
12291333 		if (static_branch_likely(&supports_deactivate_key))
12301334 			pr_info("GIC: Using split EOI/Deactivate mode\n");
....@@ -1238,20 +1342,18 @@
12381342 		gic_init_chip(gic, NULL, name, false);
12391343 	}
12401344 
1241
-	ret = gic_init_bases(gic, irq_start, handle);
1345
+	ret = gic_init_bases(gic, handle);
12421346 	if (ret)
12431347 		kfree(name);
1348
+	else if (gic == &gic_data[0])
1349
+		gic_smp_init();
12441350 
12451351 	return ret;
12461352 }
12471353 
1248
-void __init gic_init(unsigned int gic_nr, int irq_start,
1249
-		     void __iomem *dist_base, void __iomem *cpu_base)
1354
+void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base)
12501355 {
12511356 	struct gic_chip_data *gic;
1252
-
1253
-	if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR))
1254
-		return;
12551357 
12561358 	/*
12571359 	 * Non-DT/ACPI systems won't run a hypervisor, so let's not
....@@ -1259,11 +1361,11 @@
12591361 	 */
12601362 	static_branch_disable(&supports_deactivate_key);
12611363 
1262
-	gic = &gic_data[gic_nr];
1364
+	gic = &gic_data[0];
12631365 	gic->raw_dist_base = dist_base;
12641366 	gic->raw_cpu_base = cpu_base;
12651367 
1266
-	__gic_init_bases(gic, irq_start, NULL);
1368
+	__gic_init_bases(gic, NULL);
12671369 }
12681370 
12691371 static void gic_teardown(struct gic_chip_data *gic)
....@@ -1365,6 +1467,30 @@
13651467 	return true;
13661468 }
13671469 
1470
+static bool gic_enable_rmw_access(void *data)
1471
+{
1472
+	/*
1473
+	 * The EMEV2 class of machines has a broken interconnect, and
1474
+	 * locks up on accesses that are less than 32bit. So far, only
1475
+	 * the affinity setting requires it.
1476
+	 */
1477
+	if (of_machine_is_compatible("renesas,emev2")) {
1478
+		static_branch_enable(&needs_rmw_access);
1479
+		return true;
1480
+	}
1481
+
1482
+	return false;
1483
+}
1484
+
1485
+static const struct gic_quirk gic_quirks[] = {
1486
+	{
1487
+		.desc		= "broken byte access",
1488
+		.compatible	= "arm,pl390",
1489
+		.init		= gic_enable_rmw_access,
1490
+	},
1491
+	{ },
1492
+};
1493
+
13681494 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
13691495 {
13701496 	if (!gic || !node)
....@@ -1380,6 +1506,8 @@
13801506 
13811507 	if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
13821508 		gic->percpu_offset = 0;
1509
+
1510
+	gic_enable_of_quirks(node, gic_quirks, gic);
13831511 
13841512 	return 0;
13851513 
....@@ -1406,7 +1534,7 @@
14061534 	if (ret)
14071535 		return ret;
14081536 
1409
-	ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode);
1537
+	ret = gic_init_bases(*gic, &dev->of_node->fwnode);
14101538 	if (ret) {
14111539 		gic_teardown(*gic);
14121540 		return ret;
....@@ -1466,7 +1594,7 @@
14661594 	if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
14671595 		static_branch_disable(&supports_deactivate_key);
14681596 
1469
-	ret = __gic_init_bases(gic, -1, &node->fwnode);
1597
+	ret = __gic_init_bases(gic, &node->fwnode);
14701598 	if (ret) {
14711599 		gic_teardown(gic);
14721600 		return ret;
....@@ -1515,7 +1643,7 @@
15151643 } acpi_data __initdata;
15161644 
15171645 static int __init
1518
-gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1646
+gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header,
15191647 			const unsigned long end)
15201648 {
15211649 	struct acpi_madt_generic_interrupt *processor;
....@@ -1547,7 +1675,7 @@
15471675 }
15481676 
15491677 /* The things you have to do to just *count* something... */
1550
-static int __init acpi_dummy_func(struct acpi_subtable_header *header,
1678
+static int __init acpi_dummy_func(union acpi_subtable_headers *header,
15511679 				  const unsigned long end)
15521680 {
15531681 	return 0;
....@@ -1608,7 +1736,7 @@
16081736 	gic_set_kvm_info(&gic_v2_kvm_info);
16091737 }
16101738 
1611
-static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
1739
+static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
16121740 				   const unsigned long end)
16131741 {
16141742 	struct acpi_madt_generic_distributor *dist;
....@@ -1650,14 +1778,14 @@
16501778 	/*
16511779 	 * Initialize GIC instance zero (no multi-GIC support).
16521780 	 */
1653
-	domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base);
1781
+	domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
16541782 	if (!domain_handle) {
16551783 		pr_err("Unable to allocate domain handle\n");
16561784 		gic_teardown(gic);
16571785 		return -ENOMEM;
16581786 	}
16591787 
1660
-	ret = __gic_init_bases(gic, -1, domain_handle);
1788
+	ret = __gic_init_bases(gic, domain_handle);
16611789 	if (ret) {
16621790 		pr_err("Failed to initialise GIC\n");
16631791 		irq_domain_free_fwnode(domain_handle);