enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/irqchip/irq-gic-common.c
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@@ -1,17 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2002 ARM Limited, All Rights Reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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5
 
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 #include <linux/interrupt.h>
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@@ -36,10 +25,24 @@
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 	gic_kvm_info = info;
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 }
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+void gic_enable_of_quirks(const struct device_node *np,
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+			  const struct gic_quirk *quirks, void *data)
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+{
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+	for (; quirks->desc; quirks++) {
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+		if (!of_device_is_compatible(np, quirks->compatible))
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+			continue;
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+		if (quirks->init(data))
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+			pr_info("GIC: enabling workaround for %s\n",
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+				quirks->desc);
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+	}
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+}
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+
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 void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
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 		void *data)
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 {
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 	for (; quirks->desc; quirks++) {
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+		if (quirks->compatible)
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+			continue;
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 		if (quirks->iidr != (quirks->mask & iidr))
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 			continue;
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 		if (quirks->init(data))
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..
@@ -62,7 +65,7 @@
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 	 * for "irq", depending on "type".
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 	 */
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 	raw_spin_lock_irqsave(&irq_controller_lock, flags);
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-	val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
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+	val = oldval = readl_relaxed(base + confoff);
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 	if (type & IRQ_TYPE_LEVEL_MASK)
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 		val &= ~confmask;
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 	else if (type & IRQ_TYPE_EDGE_BOTH)
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@@ -82,14 +85,10 @@
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 	 * does not allow us to set the configuration or we are in a
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 	 * non-secure mode, and hence it may not be catastrophic.
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 	 */
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-	writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
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-	if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val) {
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-		if (WARN_ON(irq >= 32))
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-			ret = -EINVAL;
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-		else
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-			pr_warn("GIC: PPI%d is secure or misconfigured\n",
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-				irq - 16);
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-	}
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+	writel_relaxed(val, base + confoff);
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+	if (readl_relaxed(base + confoff) != val)
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+		ret = -EINVAL;
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+
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 	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
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 	if (sync_access)
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@@ -131,23 +130,25 @@
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 		sync_access();
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 }
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132
 
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-void gic_cpu_config(void __iomem *base, void (*sync_access)(void))
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+void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void))
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 {
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 	int i;
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136
 
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 	/*
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 	 * Deal with the banked PPI and SGI interrupts - disable all
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-	 * PPI interrupts, ensure all SGI interrupts are enabled.
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-	 * Make sure everything is deactivated.
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+	 * private interrupts. Make sure everything is deactivated.
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 	 */
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-	writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR);
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-	writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR);
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-	writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);
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+	for (i = 0; i < nr; i += 32) {
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+		writel_relaxed(GICD_INT_EN_CLR_X32,
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+			       base + GIC_DIST_ACTIVE_CLEAR + i / 8);
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+		writel_relaxed(GICD_INT_EN_CLR_X32,
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+			       base + GIC_DIST_ENABLE_CLEAR + i / 8);
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+	}
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 	/*
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 	 * Set priority on PPI and SGI interrupts
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 	 */
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-	for (i = 0; i < 32; i += 4)
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+	for (i = 0; i < nr; i += 4)
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 		writel_relaxed(GICD_INT_DEF_PRI_X4,
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 					base + GIC_DIST_PRI + i * 4 / 4);
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