~hc/RK356X_SDK_RELEASE.git

..	..	@@ -69,16 +69,16 @@
69	69	struct hns_roce_wqe_data_seg *dseg = NULL;
70	70	struct hns_roce_qp *qp = to_hr_qp(ibqp);
71	71	struct device *dev = &hr_dev->pdev->dev;
72		- struct hns_roce_sq_db sq_db;
73		- int ps_opcode = 0, i = 0;
	72	+ struct hns_roce_sq_db sq_db = {};
	73	+ int ps_opcode, i;
74	74	unsigned long flags = 0;
75	75	void *wqe = NULL;
76		- u32 doorbell[2];
77		- int nreq = 0;
78		- u32 ind = 0;
	76	+ __le32 doorbell[2];
79	77	int ret = 0;
80		- u8 *smac;
81	78	int loopback;
	79	+ u32 wqe_idx;
	80	+ int nreq;
	81	+ u8 *smac;
82	82
83	83	if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
84	84	ibqp->qp_type != IB_QPT_RC)) {
..	..	@@ -88,13 +88,15 @@
88	88	}
89	89
90	90	spin_lock_irqsave(&qp->sq.lock, flags);
91		- ind = qp->sq_next_wqe;
	91	+
92	92	for (nreq = 0; wr; ++nreq, wr = wr->next) {
93	93	if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
94	94	ret = -ENOMEM;
95	95	*bad_wr = wr;
96	96	goto out;
97	97	}
	98	+
	99	+ wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
98	100
99	101	if (unlikely(wr->num_sge > qp->sq.max_gs)) {
100	102	dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
..	..	@@ -104,9 +106,8 @@
104	106	goto out;
105	107	}
106	108
107		- wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
108		- qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
109		- wr->wr_id;
	109	+ wqe = hns_roce_get_send_wqe(qp, wqe_idx);
	110	+ qp->sq.wrid[wqe_idx] = wr->wr_id;
110	111
111	112	/* Corresponding to the RC and RD type wqe process separately */
112	113	if (ibqp->qp_type == IB_QPT_GSI) {
..	..	@@ -175,13 +176,11 @@
175	176	roce_set_field(ud_sq_wqe->u32_36,
176	177	UD_SEND_WQE_U32_36_FLOW_LABEL_M,
177	178	UD_SEND_WQE_U32_36_FLOW_LABEL_S,
178		- ah->av.sl_tclass_flowlabel &
179		- HNS_ROCE_FLOW_LABEL_MASK);
	179	+ ah->av.flowlabel);
180	180	roce_set_field(ud_sq_wqe->u32_36,
181	181	UD_SEND_WQE_U32_36_PRIORITY_M,
182	182	UD_SEND_WQE_U32_36_PRIORITY_S,
183		- le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
184		- HNS_ROCE_SL_SHIFT);
	183	+ ah->av.sl);
185	184	roce_set_field(ud_sq_wqe->u32_36,
186	185	UD_SEND_WQE_U32_36_SGID_INDEX_M,
187	186	UD_SEND_WQE_U32_36_SGID_INDEX_S,
..	..	@@ -195,8 +194,7 @@
195	194	roce_set_field(ud_sq_wqe->u32_40,
196	195	UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
197	196	UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
198		- ah->av.sl_tclass_flowlabel >>
199		- HNS_ROCE_TCLASS_SHIFT);
	197	+ ah->av.tclass);
200	198
201	199	memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
202	200
..	..	@@ -213,7 +211,6 @@
213	211	cpu_to_le32((wr->sg_list[1].addr) >> 32);
214	212	ud_sq_wqe->l_key1 =
215	213	cpu_to_le32(wr->sg_list[1].lkey);
216		- ind++;
217	214	} else if (ibqp->qp_type == IB_QPT_RC) {
218	215	u32 tmp_len = 0;
219	216
..	..	@@ -310,7 +307,6 @@
310	307	ctrl->flag \|= cpu_to_le32(wr->num_sge <<
311	308	HNS_ROCE_WQE_SGE_NUM_BIT);
312	309	}
313		- ind++;
314	310	}
315	311	}
316	312
..	..	@@ -321,8 +317,6 @@
321	317	/* Memory barrier */
322	318	wmb();
323	319
324		- sq_db.u32_4 = 0;
325		- sq_db.u32_8 = 0;
326	320	roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
327	321	SQ_DOORBELL_U32_4_SQ_HEAD_S,
328	322	(qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
..	..	@@ -334,11 +328,10 @@
334	328	SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
335	329	roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
336	330
337		- doorbell[0] = le32_to_cpu(sq_db.u32_4);
338		- doorbell[1] = le32_to_cpu(sq_db.u32_8);
	331	+ doorbell[0] = sq_db.u32_4;
	332	+ doorbell[1] = sq_db.u32_8;
339	333
340		- hns_roce_write64_k((__le32 *)doorbell, qp->sq.db_reg_l);
341		- qp->sq_next_wqe = ind;
	334	+ hns_roce_write64_k(doorbell, qp->sq.db_reg_l);
342	335	}
343	336
344	337	spin_unlock_irqrestore(&qp->sq.lock, flags);
..	..	@@ -350,22 +343,21 @@
350	343	const struct ib_recv_wr *wr,
351	344	const struct ib_recv_wr **bad_wr)
352	345	{
353		- int ret = 0;
354		- int nreq = 0;
355		- int ind = 0;
356		- int i = 0;
357		- u32 reg_val;
358		- unsigned long flags = 0;
359	346	struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
360	347	struct hns_roce_wqe_data_seg *scat = NULL;
361	348	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
362	349	struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
363	350	struct device *dev = &hr_dev->pdev->dev;
364		- struct hns_roce_rq_db rq_db;
365		- uint32_t doorbell[2] = {0};
	351	+ struct hns_roce_rq_db rq_db = {};
	352	+ __le32 doorbell[2] = {0};
	353	+ unsigned long flags = 0;
	354	+ unsigned int wqe_idx;
	355	+ int ret = 0;
	356	+ int nreq = 0;
	357	+ int i = 0;
	358	+ u32 reg_val;
366	359
367	360	spin_lock_irqsave(&hr_qp->rq.lock, flags);
368		- ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
369	361
370	362	for (nreq = 0; wr; ++nreq, wr = wr->next) {
371	363	if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
..	..	@@ -375,6 +367,8 @@
375	367	goto out;
376	368	}
377	369
	370	+ wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
	371	+
378	372	if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
379	373	dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
380	374	wr->num_sge, hr_qp->rq.max_gs);
..	..	@@ -383,7 +377,7 @@
383	377	goto out;
384	378	}
385	379
386		- ctrl = get_recv_wqe(hr_qp, ind);
	380	+ ctrl = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
387	381
388	382	roce_set_field(ctrl->rwqe_byte_12,
389	383	RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
..	..	@@ -395,9 +389,7 @@
395	389	for (i = 0; i < wr->num_sge; i++)
396	390	set_data_seg(scat + i, wr->sg_list + i);
397	391
398		- hr_qp->rq.wrid[ind] = wr->wr_id;
399		-
400		- ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
	392	+ hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
401	393	}
402	394
403	395	out:
..	..	@@ -423,9 +415,6 @@
423	415	ROCEE_QP1C_CFG3_0_REG +
424	416	QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
425	417	} else {
426		- rq_db.u32_4 = 0;
427		- rq_db.u32_8 = 0;
428		-
429	418	roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
430	419	RQ_DOORBELL_U32_4_RQ_HEAD_S,
431	420	hr_qp->rq.head);
..	..	@@ -436,11 +425,10 @@
436	425	roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
437	426	1);
438	427
439		- doorbell[0] = le32_to_cpu(rq_db.u32_4);
440		- doorbell[1] = le32_to_cpu(rq_db.u32_8);
	428	+ doorbell[0] = rq_db.u32_4;
	429	+ doorbell[1] = rq_db.u32_8;
441	430
442		- hns_roce_write64_k((__le32 *)doorbell,
443		- hr_qp->rq.db_reg_l);
	431	+ hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
444	432	}
445	433	}
446	434	spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
..	..	@@ -514,15 +502,12 @@
514	502	static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
515	503	u32 ext_sdb_alful)
516	504	{
	505	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	506	+ struct hns_roce_db_table *db = &priv->db_table;
517	507	struct device *dev = &hr_dev->pdev->dev;
518		- struct hns_roce_v1_priv *priv;
519		- struct hns_roce_db_table *db;
520	508	dma_addr_t sdb_dma_addr;
521	509	__le32 tmp;
522	510	u32 val;
523		-
524		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
525		- db = &priv->db_table;
526	511
527	512	/* Configure extend SDB threshold */
528	513	roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
..	..	@@ -549,22 +534,19 @@
549	534	roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
550	535
551	536	dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
552		- dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
	537	+ dev_dbg(dev, "ext SDB threshold: empty: 0x%x, ful: 0x%x\n",
553	538	ext_sdb_alept, ext_sdb_alful);
554	539	}
555	540
556	541	static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
557	542	u32 ext_odb_alful)
558	543	{
	544	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	545	+ struct hns_roce_db_table *db = &priv->db_table;
559	546	struct device *dev = &hr_dev->pdev->dev;
560		- struct hns_roce_v1_priv *priv;
561		- struct hns_roce_db_table *db;
562	547	dma_addr_t odb_dma_addr;
563	548	__le32 tmp;
564	549	u32 val;
565		-
566		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
567		- db = &priv->db_table;
568	550
569	551	/* Configure extend ODB threshold */
570	552	roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
..	..	@@ -594,15 +576,12 @@
594	576	static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
595	577	u32 odb_ext_mod)
596	578	{
	579	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	580	+ struct hns_roce_db_table *db = &priv->db_table;
597	581	struct device *dev = &hr_dev->pdev->dev;
598		- struct hns_roce_v1_priv *priv;
599		- struct hns_roce_db_table *db;
600	582	dma_addr_t sdb_dma_addr;
601	583	dma_addr_t odb_dma_addr;
602	584	int ret = 0;
603		-
604		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
605		- db = &priv->db_table;
606	585
607	586	db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
608	587	if (!db->ext_db)
..	..	@@ -703,35 +682,38 @@
703	682
704	683	static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
705	684	{
	685	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	686	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
706	687	struct hns_roce_caps *caps = &hr_dev->caps;
	688	+ struct ib_device *ibdev = &hr_dev->ib_dev;
707	689	struct device *dev = &hr_dev->pdev->dev;
708	690	struct ib_cq_init_attr cq_init_attr;
709		- struct hns_roce_free_mr *free_mr;
710	691	struct ib_qp_attr attr = { 0 };
711		- struct hns_roce_v1_priv *priv;
712	692	struct hns_roce_qp *hr_qp;
713	693	struct ib_cq *cq;
714	694	struct ib_pd *pd;
715	695	union ib_gid dgid;
716		- u64 subnet_prefix;
	696	+ __be64 subnet_prefix;
717	697	int attr_mask = 0;
718		- int i, j;
719	698	int ret;
	699	+ int i, j;
720	700	u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
721	701	u8 phy_port;
722	702	u8 port = 0;
723	703	u8 sl;
724	704
725		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
726		- free_mr = &priv->free_mr;
727		-
728	705	/* Reserved cq for loop qp */
729	706	cq_init_attr.cqe = HNS_ROCE_MIN_WQE_NUM * 2;
730	707	cq_init_attr.comp_vector = 0;
731		- cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL, NULL);
732		- if (IS_ERR(cq)) {
733		- dev_err(dev, "Create cq for reseved loop qp failed!");
	708	+
	709	+ cq = rdma_zalloc_drv_obj(ibdev, ib_cq);
	710	+ if (!cq)
734	711	return -ENOMEM;
	712	+
	713	+ ret = hns_roce_create_cq(cq, &cq_init_attr, NULL);
	714	+ if (ret) {
	715	+ dev_err(dev, "Create cq for reserved loop qp failed!");
	716	+ goto alloc_cq_failed;
735	717	}
736	718	free_mr->mr_free_cq = to_hr_cq(cq);
737	719	free_mr->mr_free_cq->ib_cq.device = &hr_dev->ib_dev;
..	..	@@ -741,12 +723,17 @@
741	723	free_mr->mr_free_cq->ib_cq.cq_context = NULL;
742	724	atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
743	725
744		- pd = hns_roce_alloc_pd(&hr_dev->ib_dev, NULL, NULL);
745		- if (IS_ERR(pd)) {
746		- dev_err(dev, "Create pd for reseved loop qp failed!");
	726	+ pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
	727	+ if (!pd) {
747	728	ret = -ENOMEM;
748		- goto alloc_pd_failed;
	729	+ goto alloc_mem_failed;
749	730	}
	731	+
	732	+ pd->device = ibdev;
	733	+ ret = hns_roce_alloc_pd(pd, NULL);
	734	+ if (ret)
	735	+ goto alloc_pd_failed;
	736	+
750	737	free_mr->mr_free_pd = to_hr_pd(pd);
751	738	free_mr->mr_free_pd->ibpd.device = &hr_dev->ib_dev;
752	739	free_mr->mr_free_pd->ibpd.uobject = NULL;
..	..	@@ -812,7 +799,7 @@
812	799	attr.dest_qp_num = hr_qp->qpn;
813	800	memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
814	801	hr_dev->dev_addr[port],
815		- MAC_ADDR_OCTET_NUM);
	802	+ ETH_ALEN);
816	803
817	804	memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
818	805	memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
..	..	@@ -849,65 +836,58 @@
849	836	create_lp_qp_failed:
850	837	for (i -= 1; i >= 0; i--) {
851	838	hr_qp = free_mr->mr_free_qp[i];
852		- if (hns_roce_v1_destroy_qp(&hr_qp->ibqp))
	839	+ if (hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL))
853	840	dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
854	841	}
855	842
856		- if (hns_roce_dealloc_pd(pd))
857		- dev_err(dev, "Destroy pd for create_lp_qp failed!\n");
	843	+ hns_roce_dealloc_pd(pd, NULL);
858	844
859	845	alloc_pd_failed:
860		- if (hns_roce_ib_destroy_cq(cq))
861		- dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
	846	+ kfree(pd);
862	847
	848	+alloc_mem_failed:
	849	+ hns_roce_destroy_cq(cq, NULL);
	850	+alloc_cq_failed:
	851	+ kfree(cq);
863	852	return ret;
864	853	}
865	854
866	855	static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
867	856	{
	857	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	858	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
868	859	struct device *dev = &hr_dev->pdev->dev;
869		- struct hns_roce_free_mr *free_mr;
870		- struct hns_roce_v1_priv *priv;
871	860	struct hns_roce_qp *hr_qp;
872	861	int ret;
873	862	int i;
874		-
875		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
876		- free_mr = &priv->free_mr;
877	863
878	864	for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
879	865	hr_qp = free_mr->mr_free_qp[i];
880	866	if (!hr_qp)
881	867	continue;
882	868
883		- ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp);
	869	+ ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL);
884	870	if (ret)
885	871	dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
886	872	i, ret);
887	873	}
888	874
889		- ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq);
890		- if (ret)
891		- dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
892		-
893		- ret = hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd);
894		- if (ret)
895		- dev_err(dev, "Destroy pd for mr_free failed(%d)!\n", ret);
	875	+ hns_roce_destroy_cq(&free_mr->mr_free_cq->ib_cq, NULL);
	876	+ kfree(&free_mr->mr_free_cq->ib_cq);
	877	+ hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd, NULL);
	878	+ kfree(&free_mr->mr_free_pd->ibpd);
896	879	}
897	880
898	881	static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
899	882	{
	883	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	884	+ struct hns_roce_db_table *db = &priv->db_table;
900	885	struct device *dev = &hr_dev->pdev->dev;
901		- struct hns_roce_v1_priv *priv;
902		- struct hns_roce_db_table *db;
903	886	u32 sdb_ext_mod;
904	887	u32 odb_ext_mod;
905	888	u32 sdb_evt_mod;
906	889	u32 odb_evt_mod;
907		- int ret = 0;
908		-
909		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
910		- db = &priv->db_table;
	890	+ int ret;
911	891
912	892	memset(db, 0, sizeof(*db));
913	893
..	..	@@ -954,16 +934,12 @@
954	934
955	935	static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
956	936	{
957		- struct device *dev = &hr_dev->pdev->dev;
	937	+ long end = HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS;
	938	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	939	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
958	940	struct hns_roce_recreate_lp_qp_work *lp_qp_work;
959		- struct hns_roce_free_mr *free_mr;
960		- struct hns_roce_v1_priv *priv;
	941	+ struct device *dev = &hr_dev->pdev->dev;
961	942	struct completion comp;
962		- unsigned long end =
963		- msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
964		-
965		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
966		- free_mr = &priv->free_mr;
967	943
968	944	lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
969	945	GFP_KERNEL);
..	..	@@ -980,10 +956,11 @@
980	956
981	957	queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
982	958
983		- while (time_before_eq(jiffies, end)) {
	959	+ while (end > 0) {
984	960	if (try_wait_for_completion(&comp))
985	961	return 0;
986	962	msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
	963	+ end -= HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE;
987	964	}
988	965
989	966	lp_qp_work->comp_flag = 0;
..	..	@@ -1021,29 +998,21 @@
1021	998
1022	999	static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1023	1000	{
1024		- struct hns_roce_mr_free_work *mr_work;
1025		- struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1026		- struct hns_roce_free_mr *free_mr;
1027		- struct hns_roce_cq *mr_free_cq;
1028		- struct hns_roce_v1_priv *priv;
1029		- struct hns_roce_dev *hr_dev;
1030		- struct hns_roce_mr *hr_mr;
1031		- struct hns_roce_qp *hr_qp;
1032		- struct device *dev;
1033	1001	unsigned long end =
1034	1002	msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1035		- int i;
1036		- int ret;
	1003	+ struct hns_roce_mr_free_work *mr_work =
	1004	+ container_of(work, struct hns_roce_mr_free_work, work);
	1005	+ struct hns_roce_dev *hr_dev = to_hr_dev(mr_work->ib_dev);
	1006	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1007	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
	1008	+ struct hns_roce_cq *mr_free_cq = free_mr->mr_free_cq;
	1009	+ struct hns_roce_mr *hr_mr = mr_work->mr;
	1010	+ struct device *dev = &hr_dev->pdev->dev;
	1011	+ struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
	1012	+ struct hns_roce_qp *hr_qp;
1037	1013	int ne = 0;
1038		-
1039		- mr_work = container_of(work, struct hns_roce_mr_free_work, work);
1040		- hr_mr = (struct hns_roce_mr *)mr_work->mr;
1041		- hr_dev = to_hr_dev(mr_work->ib_dev);
1042		- dev = &hr_dev->pdev->dev;
1043		-
1044		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1045		- free_mr = &priv->free_mr;
1046		- mr_free_cq = free_mr->mr_free_cq;
	1014	+ int ret;
	1015	+ int i;
1047	1016
1048	1017	for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1049	1018	hr_qp = free_mr->mr_free_qp[i];
..	..	@@ -1090,26 +1059,22 @@
1090	1059	}
1091	1060
1092	1061	static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1093		- struct hns_roce_mr *mr)
	1062	+ struct hns_roce_mr mr, struct ib_udata udata)
1094	1063	{
	1064	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1065	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
	1066	+ long end = HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS;
1095	1067	struct device *dev = &hr_dev->pdev->dev;
1096	1068	struct hns_roce_mr_free_work *mr_work;
1097		- struct hns_roce_free_mr *free_mr;
1098		- struct hns_roce_v1_priv *priv;
1099		- struct completion comp;
1100		- unsigned long end =
1101		- msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1102	1069	unsigned long start = jiffies;
1103		- int npages;
	1070	+ struct completion comp;
1104	1071	int ret = 0;
1105	1072
1106		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1107		- free_mr = &priv->free_mr;
1108		-
1109	1073	if (mr->enabled) {
1110		- if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1111		- & (hr_dev->caps.num_mtpts - 1)))
1112		- dev_warn(dev, "HW2SW_MPT failed!\n");
	1074	+ if (hns_roce_hw_destroy_mpt(hr_dev, NULL,
	1075	+ key_to_hw_index(mr->key) &
	1076	+ (hr_dev->caps.num_mtpts - 1)))
	1077	+ dev_warn(dev, "DESTROY_MPT failed!\n");
1113	1078	}
1114	1079
1115	1080	mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
..	..	@@ -1128,10 +1093,11 @@
1128	1093
1129	1094	queue_work(free_mr->free_mr_wq, &(mr_work->work));
1130	1095
1131		- while (time_before_eq(jiffies, end)) {
	1096	+ while (end > 0) {
1132	1097	if (try_wait_for_completion(&comp))
1133	1098	goto free_mr;
1134	1099	msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
	1100	+ end -= HNS_ROCE_V1_FREE_MR_WAIT_VALUE;
1135	1101	}
1136	1102
1137	1103	mr_work->comp_flag = 0;
..	..	@@ -1145,18 +1111,9 @@
1145	1111	dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1146	1112	mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1147	1113
1148		- if (mr->size != ~0ULL) {
1149		- npages = ib_umem_page_count(mr->umem);
1150		- dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1151		- mr->pbl_dma_addr);
1152		- }
1153		-
1154	1114	hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1155	1115	key_to_hw_index(mr->key), 0);
1156		-
1157		- if (mr->umem)
1158		- ib_umem_release(mr->umem);
1159		-
	1116	+ hns_roce_mtr_destroy(hr_dev, &mr->pbl_mtr);
1160	1117	kfree(mr);
1161	1118
1162	1119	return ret;
..	..	@@ -1164,12 +1121,9 @@
1164	1121
1165	1122	static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1166	1123	{
	1124	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1125	+ struct hns_roce_db_table *db = &priv->db_table;
1167	1126	struct device *dev = &hr_dev->pdev->dev;
1168		- struct hns_roce_v1_priv *priv;
1169		- struct hns_roce_db_table *db;
1170		-
1171		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1172		- db = &priv->db_table;
1173	1127
1174	1128	if (db->sdb_ext_mod) {
1175	1129	dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
..	..	@@ -1190,17 +1144,14 @@
1190	1144
1191	1145	static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1192	1146	{
1193		- int ret;
1194		- u32 val;
1195		- __le32 tmp;
1196		- int raq_shift = 0;
1197		- dma_addr_t addr;
1198		- struct hns_roce_v1_priv *priv;
1199		- struct hns_roce_raq_table *raq;
	1147	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1148	+ struct hns_roce_raq_table *raq = &priv->raq_table;
1200	1149	struct device *dev = &hr_dev->pdev->dev;
1201		-
1202		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1203		- raq = &priv->raq_table;
	1150	+ dma_addr_t addr;
	1151	+ int raq_shift;
	1152	+ __le32 tmp;
	1153	+ u32 val;
	1154	+ int ret;
1204	1155
1205	1156	raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1206	1157	if (!raq->e_raq_buf)
..	..	@@ -1280,12 +1231,9 @@
1280	1231
1281	1232	static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1282	1233	{
	1234	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1235	+ struct hns_roce_raq_table *raq = &priv->raq_table;
1283	1236	struct device *dev = &hr_dev->pdev->dev;
1284		- struct hns_roce_v1_priv *priv;
1285		- struct hns_roce_raq_table *raq;
1286		-
1287		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1288		- raq = &priv->raq_table;
1289	1237
1290	1238	dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1291	1239	raq->e_raq_buf->map);
..	..	@@ -1319,11 +1267,9 @@
1319	1267
1320	1268	static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1321	1269	{
	1270	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
1322	1271	struct device *dev = &hr_dev->pdev->dev;
1323		- struct hns_roce_v1_priv *priv;
1324	1272	int ret;
1325		-
1326		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1327	1273
1328	1274	priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1329	1275	HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
..	..	@@ -1362,10 +1308,8 @@
1362	1308
1363	1309	static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1364	1310	{
	1311	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
1365	1312	struct device *dev = &hr_dev->pdev->dev;
1366		- struct hns_roce_v1_priv *priv;
1367		-
1368		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1369	1313
1370	1314	dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1371	1315	priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
..	..	@@ -1379,12 +1323,9 @@
1379	1323
1380	1324	static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1381	1325	{
	1326	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1327	+ struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1382	1328	struct device *dev = &hr_dev->pdev->dev;
1383		- struct hns_roce_buf_list *tptr_buf;
1384		- struct hns_roce_v1_priv *priv;
1385		-
1386		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1387		- tptr_buf = &priv->tptr_table.tptr_buf;
1388	1329
1389	1330	/*
1390	1331	* This buffer will be used for CQ's tptr(tail pointer), also
..	..	@@ -1405,12 +1346,9 @@
1405	1346
1406	1347	static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1407	1348	{
	1349	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1350	+ struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1408	1351	struct device *dev = &hr_dev->pdev->dev;
1409		- struct hns_roce_buf_list *tptr_buf;
1410		- struct hns_roce_v1_priv *priv;
1411		-
1412		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1413		- tptr_buf = &priv->tptr_table.tptr_buf;
1414	1352
1415	1353	dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1416	1354	tptr_buf->buf, tptr_buf->map);
..	..	@@ -1418,13 +1356,10 @@
1418	1356
1419	1357	static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1420	1358	{
	1359	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1360	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
1421	1361	struct device *dev = &hr_dev->pdev->dev;
1422		- struct hns_roce_free_mr *free_mr;
1423		- struct hns_roce_v1_priv *priv;
1424		- int ret = 0;
1425		-
1426		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1427		- free_mr = &priv->free_mr;
	1362	+ int ret;
1428	1363
1429	1364	free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1430	1365	if (!free_mr->free_mr_wq) {
..	..	@@ -1444,11 +1379,8 @@
1444	1379
1445	1380	static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1446	1381	{
1447		- struct hns_roce_free_mr *free_mr;
1448		- struct hns_roce_v1_priv *priv;
1449		-
1450		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1451		- free_mr = &priv->free_mr;
	1382	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1383	+ struct hns_roce_free_mr *free_mr = &priv->free_mr;
1452	1384
1453	1385	flush_workqueue(free_mr->free_mr_wq);
1454	1386	destroy_workqueue(free_mr->free_mr_wq);
..	..	@@ -1505,42 +1437,10 @@
1505	1437	return ret;
1506	1438	}
1507	1439
1508		-static int hns_roce_des_qp_init(struct hns_roce_dev *hr_dev)
1509		-{
1510		- struct device *dev = &hr_dev->pdev->dev;
1511		- struct hns_roce_v1_priv *priv;
1512		- struct hns_roce_des_qp *des_qp;
1513		-
1514		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1515		- des_qp = &priv->des_qp;
1516		-
1517		- des_qp->requeue_flag = 1;
1518		- des_qp->qp_wq = create_singlethread_workqueue("hns_roce_destroy_qp");
1519		- if (!des_qp->qp_wq) {
1520		- dev_err(dev, "Create destroy qp workqueue failed!\n");
1521		- return -ENOMEM;
1522		- }
1523		-
1524		- return 0;
1525		-}
1526		-
1527		-static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1528		-{
1529		- struct hns_roce_v1_priv *priv;
1530		- struct hns_roce_des_qp *des_qp;
1531		-
1532		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1533		- des_qp = &priv->des_qp;
1534		-
1535		- des_qp->requeue_flag = 0;
1536		- flush_workqueue(des_qp->qp_wq);
1537		- destroy_workqueue(des_qp->qp_wq);
1538		-}
1539		-
1540	1440	static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1541	1441	{
1542		- int i = 0;
1543	1442	struct hns_roce_caps *caps = &hr_dev->caps;
	1443	+ int i;
1544	1444
1545	1445	hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1546	1446	hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
..	..	@@ -1570,18 +1470,19 @@
1570	1470	caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1571	1471	caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1572	1472	caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1573		- caps->qpc_entry_sz = HNS_ROCE_V1_QPC_ENTRY_SIZE;
	1473	+ caps->qpc_sz = HNS_ROCE_V1_QPC_SIZE;
1574	1474	caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1575	1475	caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1576	1476	caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1577	1477	caps->mtt_entry_sz = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1578		- caps->cq_entry_sz = HNS_ROCE_V1_CQE_ENTRY_SIZE;
	1478	+ caps->cqe_sz = HNS_ROCE_V1_CQE_SIZE;
1579	1479	caps->page_size_cap = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1580	1480	caps->reserved_lkey = 0;
1581	1481	caps->reserved_pds = 0;
1582	1482	caps->reserved_mrws = 1;
1583	1483	caps->reserved_uars = 0;
1584	1484	caps->reserved_cqs = 0;
	1485	+ caps->reserved_qps = 12; /* 2 SQP per port, six ports total 12 */
1585	1486	caps->chunk_sz = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1586	1487
1587	1488	for (i = 0; i < caps->num_ports; i++)
..	..	@@ -1655,12 +1556,6 @@
1655	1556	goto error_failed_tptr_init;
1656	1557	}
1657	1558
1658		- ret = hns_roce_des_qp_init(hr_dev);
1659		- if (ret) {
1660		- dev_err(dev, "des qp init failed!\n");
1661		- goto error_failed_des_qp_init;
1662		- }
1663		-
1664	1559	ret = hns_roce_free_mr_init(hr_dev);
1665	1560	if (ret) {
1666	1561	dev_err(dev, "free mr init failed!\n");
..	..	@@ -1672,9 +1567,6 @@
1672	1567	return 0;
1673	1568
1674	1569	error_failed_free_mr_init:
1675		- hns_roce_des_qp_free(hr_dev);
1676		-
1677		-error_failed_des_qp_init:
1678	1570	hns_roce_tptr_free(hr_dev);
1679	1571
1680	1572	error_failed_tptr_init:
..	..	@@ -1692,7 +1584,6 @@
1692	1584	{
1693	1585	hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1694	1586	hns_roce_free_mr_free(hr_dev);
1695		- hns_roce_des_qp_free(hr_dev);
1696	1587	hns_roce_tptr_free(hr_dev);
1697	1588	hns_roce_bt_free(hr_dev);
1698	1589	hns_roce_raq_free(hr_dev);
..	..	@@ -1744,8 +1635,6 @@
1744	1635
1745	1636	writel(val, hcr + 5);
1746	1637
1747		- mmiowb();
1748		-
1749	1638	return 0;
1750	1639	}
1751	1640
..	..	@@ -1753,7 +1642,7 @@
1753	1642	unsigned long timeout)
1754	1643	{
1755	1644	u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1756		- unsigned long end = 0;
	1645	+ unsigned long end;
1757	1646	u32 status = 0;
1758	1647
1759	1648	end = msecs_to_jiffies(timeout) + jiffies;
..	..	@@ -1779,10 +1668,13 @@
1779	1668	int gid_index, const union ib_gid *gid,
1780	1669	const struct ib_gid_attr *attr)
1781	1670	{
	1671	+ unsigned long flags;
1782	1672	u32 *p = NULL;
1783		- u8 gid_idx = 0;
	1673	+ u8 gid_idx;
1784	1674
1785	1675	gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
	1676	+
	1677	+ spin_lock_irqsave(&hr_dev->iboe.lock, flags);
1786	1678
1787	1679	p = (u32 *)&gid->raw[0];
1788	1680	roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
..	..	@@ -1799,6 +1691,8 @@
1799	1691	p = (u32 *)&gid->raw[0xc];
1800	1692	roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1801	1693	(HNS_ROCE_V1_GID_NUM * gid_idx));
	1694	+
	1695	+ spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
1802	1696
1803	1697	return 0;
1804	1698	}
..	..	@@ -1861,13 +1755,15 @@
1861	1755	val);
1862	1756	}
1863	1757
1864		-static int hns_roce_v1_write_mtpt(void mb_buf, struct hns_roce_mr mr,
	1758	+static int hns_roce_v1_write_mtpt(struct hns_roce_dev hr_dev, void mb_buf,
	1759	+ struct hns_roce_mr *mr,
1865	1760	unsigned long mtpt_idx)
1866	1761	{
	1762	+ u64 pages[HNS_ROCE_MAX_INNER_MTPT_NUM] = { 0 };
	1763	+ struct ib_device *ibdev = &hr_dev->ib_dev;
1867	1764	struct hns_roce_v1_mpt_entry *mpt_entry;
1868		- struct scatterlist *sg;
1869		- u64 *pages;
1870		- int entry;
	1765	+ dma_addr_t pbl_ba;
	1766	+ int count;
1871	1767	int i;
1872	1768
1873	1769	/* MPT filled into mailbox buf */
..	..	@@ -1917,22 +1813,15 @@
1917	1813	if (mr->type == MR_TYPE_DMA)
1918	1814	return 0;
1919	1815
1920		- pages = (u64 *) __get_free_page(GFP_KERNEL);
1921		- if (!pages)
1922		- return -ENOMEM;
1923		-
1924		- i = 0;
1925		- for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
1926		- pages[i] = ((u64)sg_dma_address(sg)) >> 12;
1927		-
1928		- /* Directly record to MTPT table firstly 7 entry */
1929		- if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1930		- break;
1931		- i++;
	1816	+ count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
	1817	+ ARRAY_SIZE(pages), &pbl_ba);
	1818	+ if (count < 1) {
	1819	+ ibdev_err(ibdev, "failed to find PBL mtr, count = %d.", count);
	1820	+ return -ENOBUFS;
1932	1821	}
1933	1822
1934	1823	/* Register user mr */
1935		- for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
	1824	+ for (i = 0; i < count; i++) {
1936	1825	switch (i) {
1937	1826	case 0:
1938	1827	mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
..	..	@@ -1998,21 +1887,16 @@
1998	1887	}
1999	1888	}
2000	1889
2001		- free_page((unsigned long) pages);
2002		-
2003		- mpt_entry->pbl_addr_l = cpu_to_le32((u32)(mr->pbl_dma_addr));
2004		-
	1890	+ mpt_entry->pbl_addr_l = cpu_to_le32(pbl_ba);
2005	1891	roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
2006		- MPT_BYTE_12_PBL_ADDR_H_S,
2007		- ((u32)(mr->pbl_dma_addr >> 32)));
	1892	+ MPT_BYTE_12_PBL_ADDR_H_S, upper_32_bits(pbl_ba));
2008	1893
2009	1894	return 0;
2010	1895	}
2011	1896
2012	1897	static void get_cqe(struct hns_roce_cq hr_cq, int n)
2013	1898	{
2014		- return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
2015		- n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
	1899	+ return hns_roce_buf_offset(hr_cq->mtr.kmem, n * HNS_ROCE_V1_CQE_SIZE);
2016	1900	}
2017	1901
2018	1902	static void get_sw_cqe(struct hns_roce_cq hr_cq, int n)
..	..	@@ -2021,7 +1905,7 @@
2021	1905
2022	1906	/* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2023	1907	return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
2024		- !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
	1908	+ !!(n & hr_cq->cq_depth)) ? hr_cqe : NULL;
2025	1909	}
2026	1910
2027	1911	static struct hns_roce_cqe next_cqe_sw(struct hns_roce_cq hr_cq)
..	..	@@ -2104,19 +1988,14 @@
2104	1988
2105	1989	static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2106	1990	struct hns_roce_cq hr_cq, void mb_buf,
2107		- u64 *mtts, dma_addr_t dma_handle, int nent,
2108		- u32 vector)
	1991	+ u64 *mtts, dma_addr_t dma_handle)
2109	1992	{
2110		- struct hns_roce_cq_context *cq_context = NULL;
2111		- struct hns_roce_buf_list *tptr_buf;
2112		- struct hns_roce_v1_priv *priv;
	1993	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
	1994	+ struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
	1995	+ struct hns_roce_cq_context *cq_context = mb_buf;
2113	1996	dma_addr_t tptr_dma_addr;
2114	1997	int offset;
2115	1998
2116		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2117		- tptr_buf = &priv->tptr_table.tptr_buf;
2118		-
2119		- cq_context = mb_buf;
2120	1999	memset(cq_context, 0, sizeof(*cq_context));
2121	2000
2122	2001	/* Get the tptr for this CQ. */
..	..	@@ -2140,9 +2019,9 @@
2140	2019	roce_set_field(cq_context->cqc_byte_12,
2141	2020	CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2142	2021	CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2143		- ilog2((unsigned int)nent));
	2022	+ ilog2(hr_cq->cq_depth));
2144	2023	roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2145		- CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
	2024	+ CQ_CONTEXT_CQC_BYTE_12_CEQN_S, hr_cq->vector);
2146	2025
2147	2026	cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2148	2027
..	..	@@ -2193,7 +2072,7 @@
2193	2072	{
2194	2073	struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2195	2074	u32 notification_flag;
2196		- __le32 doorbell[2];
	2075	+ __le32 doorbell[2] = {};
2197	2076
2198	2077	notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2199	2078	IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
..	..	@@ -2325,9 +2204,10 @@
2325	2204
2326	2205	if (is_send) {
2327	2206	/* SQ conrespond to CQE */
2328		- sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
	2207	+ sq_wqe = hns_roce_get_send_wqe(*cur_qp,
	2208	+ roce_get_field(cqe->cqe_byte_4,
2329	2209	CQE_BYTE_4_WQE_INDEX_M,
2330		- CQE_BYTE_4_WQE_INDEX_S)&
	2210	+ CQE_BYTE_4_WQE_INDEX_S) &
2331	2211	((*cur_qp)->sq.wqe_cnt-1));
2332	2212	switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2333	2213	case HNS_ROCE_WQE_OPCODE_SEND:
..	..	@@ -2456,29 +2336,22 @@
2456	2336	struct hns_roce_hem_table *table, int obj,
2457	2337	int step_idx)
2458	2338	{
	2339	+ struct hns_roce_v1_priv *priv = hr_dev->priv;
2459	2340	struct device *dev = &hr_dev->pdev->dev;
2460		- struct hns_roce_v1_priv *priv;
2461		- unsigned long end = 0, flags = 0;
	2341	+ long end = HW_SYNC_TIMEOUT_MSECS;
2462	2342	__le32 bt_cmd_val[2] = {0};
	2343	+ unsigned long flags = 0;
2463	2344	void __iomem *bt_cmd;
2464	2345	u64 bt_ba = 0;
2465	2346
2466		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2467		-
2468	2347	switch (table->type) {
2469	2348	case HEM_TYPE_QPC:
2470		- roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2471		- ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
2472	2349	bt_ba = priv->bt_table.qpc_buf.map >> 12;
2473	2350	break;
2474	2351	case HEM_TYPE_MTPT:
2475		- roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2476		- ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
2477	2352	bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2478	2353	break;
2479	2354	case HEM_TYPE_CQC:
2480		- roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2481		- ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
2482	2355	bt_ba = priv->bt_table.cqc_buf.map >> 12;
2483	2356	break;
2484	2357	case HEM_TYPE_SRQC:
..	..	@@ -2487,6 +2360,8 @@
2487	2360	default:
2488	2361	return 0;
2489	2362	}
	2363	+ roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
	2364	+ ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
2490	2365	roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2491	2366	ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2492	2367	roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
..	..	@@ -2496,10 +2371,9 @@
2496	2371
2497	2372	bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2498	2373
2499		- end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
2500	2374	while (1) {
2501	2375	if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2502		- if (!(time_before(jiffies, end))) {
	2376	+ if (!end) {
2503	2377	dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2504	2378	spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2505	2379	flags);
..	..	@@ -2508,10 +2382,11 @@
2508	2382	} else {
2509	2383	break;
2510	2384	}
2511		- msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
	2385	+ mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
	2386	+ end -= HW_SYNC_SLEEP_TIME_INTERVAL;
2512	2387	}
2513	2388
2514		- bt_cmd_val[0] = (__le32)bt_ba;
	2389	+ bt_cmd_val[0] = cpu_to_le32(bt_ba);
2515	2390	roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2516	2391	ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2517	2392	hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
..	..	@@ -2522,7 +2397,6 @@
2522	2397	}
2523	2398
2524	2399	static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2525		- struct hns_roce_mtt *mtt,
2526	2400	enum hns_roce_qp_state cur_state,
2527	2401	enum hns_roce_qp_state new_state,
2528	2402	struct hns_roce_qp_context *context,
..	..	@@ -2569,7 +2443,7 @@
2569	2443
2570	2444	struct hns_roce_cmd_mailbox *mailbox;
2571	2445	struct device *dev = &hr_dev->pdev->dev;
2572		- int ret = 0;
	2446	+ int ret;
2573	2447
2574	2448	if (cur_state >= HNS_ROCE_QP_NUM_STATE \|\|
2575	2449	new_state >= HNS_ROCE_QP_NUM_STATE \|\|
..	..	@@ -2603,6 +2477,28 @@
2603	2477	return ret;
2604	2478	}
2605	2479
	2480	+static int find_wqe_mtt(struct hns_roce_dev hr_dev, struct hns_roce_qp hr_qp,
	2481	+ u64 sq_ba, u64 rq_ba, dma_addr_t *bt_ba)
	2482	+{
	2483	+ struct ib_device *ibdev = &hr_dev->ib_dev;
	2484	+ int count;
	2485	+
	2486	+ count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, sq_ba, 1, bt_ba);
	2487	+ if (count < 1) {
	2488	+ ibdev_err(ibdev, "Failed to find SQ ba\n");
	2489	+ return -ENOBUFS;
	2490	+ }
	2491	+
	2492	+ count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, rq_ba,
	2493	+ 1, NULL);
	2494	+ if (!count) {
	2495	+ ibdev_err(ibdev, "Failed to find RQ ba\n");
	2496	+ return -ENOBUFS;
	2497	+ }
	2498	+
	2499	+ return 0;
	2500	+}
	2501	+
2606	2502	static int hns_roce_v1_m_sqp(struct ib_qp ibqp, const struct ib_qp_attr attr,
2607	2503	int attr_mask, enum ib_qp_state cur_state,
2608	2504	enum ib_qp_state new_state)
..	..	@@ -2610,25 +2506,20 @@
2610	2506	struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2611	2507	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2612	2508	struct hns_roce_sqp_context *context;
2613		- struct device *dev = &hr_dev->pdev->dev;
2614	2509	dma_addr_t dma_handle = 0;
2615	2510	u32 __iomem *addr;
2616		- int rq_pa_start;
	2511	+ u64 sq_ba = 0;
	2512	+ u64 rq_ba = 0;
2617	2513	__le32 tmp;
2618	2514	u32 reg_val;
2619		- u64 *mtts;
2620	2515
2621	2516	context = kzalloc(sizeof(*context), GFP_KERNEL);
2622	2517	if (!context)
2623	2518	return -ENOMEM;
2624	2519
2625	2520	/* Search QP buf's MTTs */
2626		- mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2627		- hr_qp->mtt.first_seg, &dma_handle);
2628		- if (!mtts) {
2629		- dev_err(dev, "qp buf pa find failed\n");
	2521	+ if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2630	2522	goto out;
2631		- }
2632	2523
2633	2524	if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2634	2525	roce_set_field(context->qp1c_bytes_4,
..	..	@@ -2642,11 +2533,11 @@
2642	2533	roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2643	2534	QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2644	2535
2645		- context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
	2536	+ context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2646	2537	roce_set_field(context->qp1c_bytes_12,
2647	2538	QP1C_BYTES_12_SQ_RQ_BT_H_M,
2648	2539	QP1C_BYTES_12_SQ_RQ_BT_H_S,
2649		- ((u32)(dma_handle >> 32)));
	2540	+ upper_32_bits(dma_handle));
2650	2541
2651	2542	roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2652	2543	QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
..	..	@@ -2654,7 +2545,7 @@
2654	2545	QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2655	2546	roce_set_bit(context->qp1c_bytes_16,
2656	2547	QP1C_BYTES_16_SIGNALING_TYPE_S,
2657		- le32_to_cpu(hr_qp->sq_signal_bits));
	2548	+ hr_qp->sq_signal_bits);
2658	2549	roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2659	2550	1);
2660	2551	roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
..	..	@@ -2667,14 +2558,12 @@
2667	2558	roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2668	2559	QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2669	2560
2670		- rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2671		- context->cur_rq_wqe_ba_l =
2672		- cpu_to_le32((u32)(mtts[rq_pa_start]));
	2561	+ context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
2673	2562
2674	2563	roce_set_field(context->qp1c_bytes_28,
2675	2564	QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2676	2565	QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2677		- (mtts[rq_pa_start]) >> 32);
	2566	+ upper_32_bits(rq_ba));
2678	2567	roce_set_field(context->qp1c_bytes_28,
2679	2568	QP1C_BYTES_28_RQ_CUR_IDX_M,
2680	2569	QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
..	..	@@ -2688,12 +2577,12 @@
2688	2577	QP1C_BYTES_32_TX_CQ_NUM_S,
2689	2578	to_hr_cq(ibqp->send_cq)->cqn);
2690	2579
2691		- context->cur_sq_wqe_ba_l = cpu_to_le32((u32)mtts[0]);
	2580	+ context->cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
2692	2581
2693	2582	roce_set_field(context->qp1c_bytes_40,
2694	2583	QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2695	2584	QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2696		- (mtts[0]) >> 32);
	2585	+ upper_32_bits(sq_ba));
2697	2586	roce_set_field(context->qp1c_bytes_40,
2698	2587	QP1C_BYTES_40_SQ_CUR_IDX_M,
2699	2588	QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
..	..	@@ -2737,7 +2626,6 @@
2737	2626	hr_qp->rq.tail = 0;
2738	2627	hr_qp->sq.head = 0;
2739	2628	hr_qp->sq.tail = 0;
2740		- hr_qp->sq_next_wqe = 0;
2741	2629	}
2742	2630
2743	2631	kfree(context);
..	..	@@ -2746,6 +2634,28 @@
2746	2634	out:
2747	2635	kfree(context);
2748	2636	return -EINVAL;
	2637	+}
	2638	+
	2639	+static bool check_qp_state(enum ib_qp_state cur_state,
	2640	+ enum ib_qp_state new_state)
	2641	+{
	2642	+ static const bool sm[][IB_QPS_ERR + 1] = {
	2643	+ [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
	2644	+ [IB_QPS_INIT] = true },
	2645	+ [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
	2646	+ [IB_QPS_INIT] = true,
	2647	+ [IB_QPS_RTR] = true,
	2648	+ [IB_QPS_ERR] = true },
	2649	+ [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
	2650	+ [IB_QPS_RTS] = true,
	2651	+ [IB_QPS_ERR] = true },
	2652	+ [IB_QPS_RTS] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true },
	2653	+ [IB_QPS_SQD] = {},
	2654	+ [IB_QPS_SQE] = {},
	2655	+ [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }
	2656	+ };
	2657	+
	2658	+ return sm[cur_state][new_state];
2749	2659	}
2750	2660
2751	2661	static int hns_roce_v1_m_qp(struct ib_qp ibqp, const struct ib_qp_attr attr,
..	..	@@ -2760,26 +2670,29 @@
2760	2670	dma_addr_t dma_handle_2 = 0;
2761	2671	dma_addr_t dma_handle = 0;
2762	2672	__le32 doorbell[2] = {0};
2763		- int rq_pa_start = 0;
2764	2673	u64 *mtts_2 = NULL;
2765	2674	int ret = -EINVAL;
2766		- u64 *mtts = NULL;
	2675	+ u64 sq_ba = 0;
	2676	+ u64 rq_ba = 0;
2767	2677	int port;
2768	2678	u8 port_num;
2769	2679	u8 *dmac;
2770	2680	u8 *smac;
	2681	+
	2682	+ if (!check_qp_state(cur_state, new_state)) {
	2683	+ ibdev_err(ibqp->device,
	2684	+ "not support QP(%u) status from %d to %d\n",
	2685	+ ibqp->qp_num, cur_state, new_state);
	2686	+ return -EINVAL;
	2687	+ }
2771	2688
2772	2689	context = kzalloc(sizeof(*context), GFP_KERNEL);
2773	2690	if (!context)
2774	2691	return -ENOMEM;
2775	2692
2776	2693	/* Search qp buf's mtts */
2777		- mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2778		- hr_qp->mtt.first_seg, &dma_handle);
2779		- if (mtts == NULL) {
2780		- dev_err(dev, "qp buf pa find failed\n");
	2694	+ if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2781	2695	goto out;
2782		- }
2783	2696
2784	2697	/* Search IRRL's mtts */
2785	2698	mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
..	..	@@ -2934,11 +2847,11 @@
2934	2847
2935	2848	dmac = (u8 *)attr->ah_attr.roce.dmac;
2936	2849
2937		- context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
	2850	+ context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2938	2851	roce_set_field(context->qpc_bytes_24,
2939	2852	QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2940	2853	QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2941		- ((u32)(dma_handle >> 32)));
	2854	+ upper_32_bits(dma_handle));
2942	2855	roce_set_bit(context->qpc_bytes_24,
2943	2856	QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2944	2857	1);
..	..	@@ -2960,7 +2873,7 @@
2960	2873	1);
2961	2874	roce_set_bit(context->qpc_bytes_32,
2962	2875	QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2963		- le32_to_cpu(hr_qp->sq_signal_bits));
	2876	+ hr_qp->sq_signal_bits);
2964	2877
2965	2878	port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2966	2879	hr_qp->port;
..	..	@@ -3037,14 +2950,12 @@
3037	2950	QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
3038	2951	QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
3039	2952
3040		- rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
3041		- context->cur_rq_wqe_ba_l =
3042		- cpu_to_le32((u32)(mtts[rq_pa_start]));
	2953	+ context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
3043	2954
3044	2955	roce_set_field(context->qpc_bytes_76,
3045	2956	QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
3046	2957	QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
3047		- mtts[rq_pa_start] >> 32);
	2958	+ upper_32_bits(rq_ba));
3048	2959	roce_set_field(context->qpc_bytes_76,
3049	2960	QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
3050	2961	QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
..	..	@@ -3106,8 +3017,7 @@
3106	3017	QP_CONTEXT_QPC_BYTES_156_SL_S,
3107	3018	rdma_ah_get_sl(&attr->ah_attr));
3108	3019	hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3109		- } else if (cur_state == IB_QPS_RTR &&
3110		- new_state == IB_QPS_RTS) {
	3020	+ } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3111	3021	/* If exist optional param, return error */
3112	3022	if ((attr_mask & IB_QP_ALT_PATH) \|\|
3113	3023	(attr_mask & IB_QP_ACCESS_FLAGS) \|\|
..	..	@@ -3119,12 +3029,12 @@
3119	3029	goto out;
3120	3030	}
3121	3031
3122		- context->rx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
	3032	+ context->rx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3123	3033
3124	3034	roce_set_field(context->qpc_bytes_120,
3125	3035	QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3126	3036	QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3127		- (mtts[0]) >> 32);
	3037	+ upper_32_bits(sq_ba));
3128	3038
3129	3039	roce_set_field(context->qpc_bytes_124,
3130	3040	QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
..	..	@@ -3267,28 +3177,18 @@
3267	3177	QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3268	3178	QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3269	3179
3270		- context->tx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
	3180	+ context->tx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3271	3181
3272	3182	roce_set_field(context->qpc_bytes_188,
3273	3183	QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3274	3184	QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3275		- (mtts[0]) >> 32);
	3185	+ upper_32_bits(sq_ba));
3276	3186	roce_set_bit(context->qpc_bytes_188,
3277	3187	QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3278	3188	roce_set_field(context->qpc_bytes_188,
3279	3189	QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3280	3190	QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3281	3191	0);
3282		- } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) \|\|
3283		- (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) \|\|
3284		- (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) \|\|
3285		- (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) \|\|
3286		- (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) \|\|
3287		- (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) \|\|
3288		- (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) \|\|
3289		- (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3290		- dev_err(dev, "not support this status migration\n");
3291		- goto out;
3292	3192	}
3293	3193
3294	3194	/* Every status migrate must change state */
..	..	@@ -3297,8 +3197,7 @@
3297	3197	QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3298	3198
3299	3199	/* SW pass context to HW */
3300		- ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3301		- to_hns_roce_state(cur_state),
	3200	+ ret = hns_roce_v1_qp_modify(hr_dev, to_hns_roce_state(cur_state),
3302	3201	to_hns_roce_state(new_state), context,
3303	3202	hr_qp);
3304	3203	if (ret) {
..	..	@@ -3351,7 +3250,6 @@
3351	3250	hr_qp->rq.tail = 0;
3352	3251	hr_qp->sq.head = 0;
3353	3252	hr_qp->sq.tail = 0;
3354		- hr_qp->sq_next_wqe = 0;
3355	3253	}
3356	3254	out:
3357	3255	kfree(context);
..	..	@@ -3494,7 +3392,7 @@
3494	3392	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3495	3393	struct device *dev = &hr_dev->pdev->dev;
3496	3394	struct hns_roce_qp_context *context;
3497		- int tmp_qp_state = 0;
	3395	+ int tmp_qp_state;
3498	3396	int ret = 0;
3499	3397	int state;
3500	3398
..	..	@@ -3605,7 +3503,7 @@
3605	3503	qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3606	3504	QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3607	3505	QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3608		- qp_attr->rnr_retry = (u8)context->rnr_retry;
	3506	+ qp_attr->rnr_retry = (u8)le32_to_cpu(context->rnr_retry);
3609	3507
3610	3508	done:
3611	3509	qp_attr->cur_qp_state = qp_attr->qp_state;
..	..	@@ -3639,372 +3537,47 @@
3639	3537	hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3640	3538	}
3641	3539
3642		-static void hns_roce_check_sdb_status(struct hns_roce_dev *hr_dev,
3643		- u32 old_send, u32 old_retry,
3644		- u32 tsp_st, u32 success_flags)
3645		-{
3646		- __le32 old_send_tmp, old_retry_tmp;
3647		- u32 sdb_retry_cnt;
3648		- u32 sdb_send_ptr;
3649		- u32 cur_cnt, old_cnt;
3650		- __le32 tmp, tmp1;
3651		- u32 send_ptr;
3652		-
3653		- sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3654		- sdb_retry_cnt = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3655		- tmp = cpu_to_le32(sdb_send_ptr);
3656		- tmp1 = cpu_to_le32(sdb_retry_cnt);
3657		- cur_cnt = roce_get_field(tmp, ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3658		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3659		- roce_get_field(tmp1, ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3660		- ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3661		-
3662		- old_send_tmp = (__le32 *)old_send;
3663		- old_retry_tmp = (__le32 *)old_retry;
3664		- if (!roce_get_bit(*tsp_st, ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
3665		- old_cnt = roce_get_field(*old_send_tmp,
3666		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3667		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3668		- roce_get_field(*old_retry_tmp,
3669		- ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3670		- ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3671		- if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3672		- *success_flags = 1;
3673		- } else {
3674		- old_cnt = roce_get_field(*old_send_tmp,
3675		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3676		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
3677		- if (cur_cnt - old_cnt > SDB_ST_CMP_VAL) {
3678		- *success_flags = 1;
3679		- } else {
3680		- send_ptr = roce_get_field(*old_send_tmp,
3681		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3682		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3683		- roce_get_field(tmp1,
3684		- ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3685		- ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3686		- roce_set_field(*old_send_tmp,
3687		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3688		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3689		- send_ptr);
3690		- }
3691		- }
3692		-}
3693		-
3694		-static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3695		- struct hns_roce_qp *hr_qp,
3696		- u32 sdb_issue_ptr,
3697		- u32 *sdb_inv_cnt,
3698		- u32 *wait_stage)
3699		-{
3700		- struct device *dev = &hr_dev->pdev->dev;
3701		- u32 sdb_send_ptr, old_send;
3702		- __le32 sdb_issue_ptr_tmp;
3703		- __le32 sdb_send_ptr_tmp;
3704		- u32 success_flags = 0;
3705		- unsigned long end;
3706		- u32 old_retry;
3707		- u32 inv_cnt;
3708		- u32 tsp_st;
3709		- __le32 tmp;
3710		-
3711		- if (*wait_stage > HNS_ROCE_V1_DB_STAGE2 \|\|
3712		- *wait_stage < HNS_ROCE_V1_DB_STAGE1) {
3713		- dev_err(dev, "QP(0x%lx) db status wait stage(%d) error!\n",
3714		- hr_qp->qpn, *wait_stage);
3715		- return -EINVAL;
3716		- }
3717		-
3718		- /* Calculate the total timeout for the entire verification process */
3719		- end = msecs_to_jiffies(HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS) + jiffies;
3720		-
3721		- if (*wait_stage == HNS_ROCE_V1_DB_STAGE1) {
3722		- /* Query db process status, until hw process completely */
3723		- sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3724		- while (roce_hw_index_cmp_lt(sdb_send_ptr, sdb_issue_ptr,
3725		- ROCEE_SDB_PTR_CMP_BITS)) {
3726		- if (!time_before(jiffies, end)) {
3727		- dev_dbg(dev, "QP(0x%lx) db process stage1 timeout. issue 0x%x send 0x%x.\n",
3728		- hr_qp->qpn, sdb_issue_ptr,
3729		- sdb_send_ptr);
3730		- return 0;
3731		- }
3732		-
3733		- msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3734		- sdb_send_ptr = roce_read(hr_dev,
3735		- ROCEE_SDB_SEND_PTR_REG);
3736		- }
3737		-
3738		- sdb_send_ptr_tmp = cpu_to_le32(sdb_send_ptr);
3739		- sdb_issue_ptr_tmp = cpu_to_le32(sdb_issue_ptr);
3740		- if (roce_get_field(sdb_issue_ptr_tmp,
3741		- ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
3742		- ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) ==
3743		- roce_get_field(sdb_send_ptr_tmp,
3744		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3745		- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)) {
3746		- old_send = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3747		- old_retry = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3748		-
3749		- do {
3750		- tsp_st = roce_read(hr_dev, ROCEE_TSP_BP_ST_REG);
3751		- tmp = cpu_to_le32(tsp_st);
3752		- if (roce_get_bit(tmp,
3753		- ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S) == 1) {
3754		- *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3755		- return 0;
3756		- }
3757		-
3758		- if (!time_before(jiffies, end)) {
3759		- dev_dbg(dev, "QP(0x%lx) db process stage1 timeout when send ptr equals issue ptr.\n"
3760		- "issue 0x%x send 0x%x.\n",
3761		- hr_qp->qpn,
3762		- le32_to_cpu(sdb_issue_ptr_tmp),
3763		- le32_to_cpu(sdb_send_ptr_tmp));
3764		- return 0;
3765		- }
3766		-
3767		- msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3768		-
3769		- hns_roce_check_sdb_status(hr_dev, &old_send,
3770		- &old_retry, &tsp_st,
3771		- &success_flags);
3772		- } while (!success_flags);
3773		- }
3774		-
3775		- *wait_stage = HNS_ROCE_V1_DB_STAGE2;
3776		-
3777		- /* Get list pointer */
3778		- *sdb_inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3779		- dev_dbg(dev, "QP(0x%lx) db process stage2. inv cnt = 0x%x.\n",
3780		- hr_qp->qpn, *sdb_inv_cnt);
3781		- }
3782		-
3783		- if (*wait_stage == HNS_ROCE_V1_DB_STAGE2) {
3784		- /* Query db's list status, until hw reversal */
3785		- inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3786		- while (roce_hw_index_cmp_lt(inv_cnt,
3787		- *sdb_inv_cnt + SDB_INV_CNT_OFFSET,
3788		- ROCEE_SDB_CNT_CMP_BITS)) {
3789		- if (!time_before(jiffies, end)) {
3790		- dev_dbg(dev, "QP(0x%lx) db process stage2 timeout. inv cnt 0x%x.\n",
3791		- hr_qp->qpn, inv_cnt);
3792		- return 0;
3793		- }
3794		-
3795		- msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3796		- inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3797		- }
3798		-
3799		- *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3800		- }
3801		-
3802		- return 0;
3803		-}
3804		-
3805		-static int check_qp_reset_state(struct hns_roce_dev *hr_dev,
3806		- struct hns_roce_qp *hr_qp,
3807		- struct hns_roce_qp_work *qp_work_entry,
3808		- int *is_timeout)
3809		-{
3810		- struct device *dev = &hr_dev->pdev->dev;
3811		- u32 sdb_issue_ptr;
3812		- int ret;
3813		-
3814		- if (hr_qp->state != IB_QPS_RESET) {
3815		- /* Set qp to ERR, waiting for hw complete processing all dbs */
3816		- ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3817		- IB_QPS_ERR);
3818		- if (ret) {
3819		- dev_err(dev, "Modify QP(0x%lx) to ERR failed!\n",
3820		- hr_qp->qpn);
3821		- return ret;
3822		- }
3823		-
3824		- /* Record issued doorbell */
3825		- sdb_issue_ptr = roce_read(hr_dev, ROCEE_SDB_ISSUE_PTR_REG);
3826		- qp_work_entry->sdb_issue_ptr = sdb_issue_ptr;
3827		- qp_work_entry->db_wait_stage = HNS_ROCE_V1_DB_STAGE1;
3828		-
3829		- /* Query db process status, until hw process completely */
3830		- ret = check_qp_db_process_status(hr_dev, hr_qp, sdb_issue_ptr,
3831		- &qp_work_entry->sdb_inv_cnt,
3832		- &qp_work_entry->db_wait_stage);
3833		- if (ret) {
3834		- dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3835		- hr_qp->qpn);
3836		- return ret;
3837		- }
3838		-
3839		- if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK) {
3840		- qp_work_entry->sche_cnt = 0;
3841		- *is_timeout = 1;
3842		- return 0;
3843		- }
3844		-
3845		- /* Modify qp to reset before destroying qp */
3846		- ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3847		- IB_QPS_RESET);
3848		- if (ret) {
3849		- dev_err(dev, "Modify QP(0x%lx) to RST failed!\n",
3850		- hr_qp->qpn);
3851		- return ret;
3852		- }
3853		- }
3854		-
3855		- return 0;
3856		-}
3857		-
3858		-static void hns_roce_v1_destroy_qp_work_fn(struct work_struct *work)
3859		-{
3860		- struct hns_roce_qp_work *qp_work_entry;
3861		- struct hns_roce_v1_priv *priv;
3862		- struct hns_roce_dev *hr_dev;
3863		- struct hns_roce_qp *hr_qp;
3864		- struct device *dev;
3865		- unsigned long qpn;
3866		- int ret;
3867		-
3868		- qp_work_entry = container_of(work, struct hns_roce_qp_work, work);
3869		- hr_dev = to_hr_dev(qp_work_entry->ib_dev);
3870		- dev = &hr_dev->pdev->dev;
3871		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
3872		- hr_qp = qp_work_entry->qp;
3873		- qpn = hr_qp->qpn;
3874		-
3875		- dev_dbg(dev, "Schedule destroy QP(0x%lx) work.\n", qpn);
3876		-
3877		- qp_work_entry->sche_cnt++;
3878		-
3879		- /* Query db process status, until hw process completely */
3880		- ret = check_qp_db_process_status(hr_dev, hr_qp,
3881		- qp_work_entry->sdb_issue_ptr,
3882		- &qp_work_entry->sdb_inv_cnt,
3883		- &qp_work_entry->db_wait_stage);
3884		- if (ret) {
3885		- dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3886		- qpn);
3887		- return;
3888		- }
3889		-
3890		- if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK &&
3891		- priv->des_qp.requeue_flag) {
3892		- queue_work(priv->des_qp.qp_wq, work);
3893		- return;
3894		- }
3895		-
3896		- /* Modify qp to reset before destroying qp */
3897		- ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3898		- IB_QPS_RESET);
3899		- if (ret) {
3900		- dev_err(dev, "Modify QP(0x%lx) to RST failed!\n", qpn);
3901		- return;
3902		- }
3903		-
3904		- hns_roce_qp_remove(hr_dev, hr_qp);
3905		- hns_roce_qp_free(hr_dev, hr_qp);
3906		-
3907		- if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3908		- /* RC QP, release QPN */
3909		- hns_roce_release_range_qp(hr_dev, qpn, 1);
3910		- kfree(hr_qp);
3911		- } else
3912		- kfree(hr_to_hr_sqp(hr_qp));
3913		-
3914		- kfree(qp_work_entry);
3915		-
3916		- dev_dbg(dev, "Accomplished destroy QP(0x%lx) work.\n", qpn);
3917		-}
3918		-
3919		-int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
	3540	+int hns_roce_v1_destroy_qp(struct ib_qp ibqp, struct ib_udata udata)
3920	3541	{
3921	3542	struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3922	3543	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3923		- struct device *dev = &hr_dev->pdev->dev;
3924		- struct hns_roce_qp_work qp_work_entry;
3925		- struct hns_roce_qp_work *qp_work;
3926		- struct hns_roce_v1_priv *priv;
3927	3544	struct hns_roce_cq send_cq, recv_cq;
3928		- int is_user = !!ibqp->pd->uobject;
3929		- int is_timeout = 0;
3930	3545	int ret;
3931	3546
3932		- ret = check_qp_reset_state(hr_dev, hr_qp, &qp_work_entry, &is_timeout);
3933		- if (ret) {
3934		- dev_err(dev, "QP reset state check failed(%d)!\n", ret);
	3547	+ ret = hns_roce_v1_modify_qp(ibqp, NULL, 0, hr_qp->state, IB_QPS_RESET);
	3548	+ if (ret)
3935	3549	return ret;
3936		- }
3937	3550
3938		- send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3939		- recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
	3551	+ send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
	3552	+ recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
3940	3553
3941	3554	hns_roce_lock_cqs(send_cq, recv_cq);
3942		- if (!is_user) {
3943		- __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3944		- to_hr_srq(hr_qp->ibqp.srq) : NULL);
3945		- if (send_cq != recv_cq)
	3555	+ if (!udata) {
	3556	+ if (recv_cq)
	3557	+ __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn,
	3558	+ (hr_qp->ibqp.srq ?
	3559	+ to_hr_srq(hr_qp->ibqp.srq) :
	3560	+ NULL));
	3561	+
	3562	+ if (send_cq && send_cq != recv_cq)
3946	3563	__hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3947	3564	}
	3565	+ hns_roce_qp_remove(hr_dev, hr_qp);
3948	3566	hns_roce_unlock_cqs(send_cq, recv_cq);
3949	3567
3950		- if (!is_timeout) {
3951		- hns_roce_qp_remove(hr_dev, hr_qp);
3952		- hns_roce_qp_free(hr_dev, hr_qp);
3953		-
3954		- /* RC QP, release QPN */
3955		- if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3956		- hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3957		- }
3958		-
3959		- hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3960		-
3961		- if (is_user)
3962		- ib_umem_release(hr_qp->umem);
3963		- else {
3964		- kfree(hr_qp->sq.wrid);
3965		- kfree(hr_qp->rq.wrid);
3966		-
3967		- hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3968		- }
3969		-
3970		- if (!is_timeout) {
3971		- if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3972		- kfree(hr_qp);
3973		- else
3974		- kfree(hr_to_hr_sqp(hr_qp));
3975		- } else {
3976		- qp_work = kzalloc(sizeof(*qp_work), GFP_KERNEL);
3977		- if (!qp_work)
3978		- return -ENOMEM;
3979		-
3980		- INIT_WORK(&qp_work->work, hns_roce_v1_destroy_qp_work_fn);
3981		- qp_work->ib_dev = &hr_dev->ib_dev;
3982		- qp_work->qp = hr_qp;
3983		- qp_work->db_wait_stage = qp_work_entry.db_wait_stage;
3984		- qp_work->sdb_issue_ptr = qp_work_entry.sdb_issue_ptr;
3985		- qp_work->sdb_inv_cnt = qp_work_entry.sdb_inv_cnt;
3986		- qp_work->sche_cnt = qp_work_entry.sche_cnt;
3987		-
3988		- priv = (struct hns_roce_v1_priv *)hr_dev->priv;
3989		- queue_work(priv->des_qp.qp_wq, &qp_work->work);
3990		- dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn);
3991		- }
	3568	+ hns_roce_qp_destroy(hr_dev, hr_qp, udata);
3992	3569
3993	3570	return 0;
3994	3571	}
3995	3572
3996		-static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
	3573	+static int hns_roce_v1_destroy_cq(struct ib_cq ibcq, struct ib_udata udata)
3997	3574	{
3998	3575	struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3999	3576	struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
4000	3577	struct device *dev = &hr_dev->pdev->dev;
4001	3578	u32 cqe_cnt_ori;
4002	3579	u32 cqe_cnt_cur;
4003		- u32 cq_buf_size;
4004	3580	int wait_time = 0;
4005		- int ret = 0;
4006		-
4007		- hns_roce_free_cq(hr_dev, hr_cq);
4008	3581
4009	3582	/*
4010	3583	* Before freeing cq buffer, we need to ensure that the outstanding CQE
..	..	@@ -4024,25 +3597,11 @@
4024	3597	if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
4025	3598	dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
4026	3599	hr_cq->cqn);
4027		- ret = -ETIMEDOUT;
4028	3600	break;
4029	3601	}
4030	3602	wait_time++;
4031	3603	}
4032		-
4033		- hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
4034		-
4035		- if (ibcq->uobject)
4036		- ib_umem_release(hr_cq->umem);
4037		- else {
4038		- /* Free the buff of stored cq */
4039		- cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
4040		- hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
4041		- }
4042		-
4043		- kfree(hr_cq);
4044		-
4045		- return ret;
	3604	+ return 0;
4046	3605	}
4047	3606
4048	3607	static void set_eq_cons_index_v1(struct hns_roce_eq *eq, int req_not)
..	..	@@ -4215,8 +3774,7 @@
4215	3774
4216	3775	static struct hns_roce_aeqe get_aeqe_v1(struct hns_roce_eq eq, u32 entry)
4217	3776	{
4218		- unsigned long off = (entry & (eq->entries - 1)) *
4219		- HNS_ROCE_AEQ_ENTRY_SIZE;
	3777	+ unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQE_SIZE;
4220	3778
4221	3779	return (struct hns_roce_aeqe )((u8 )
4222	3780	(eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
..	..	@@ -4246,7 +3804,8 @@
4246	3804	*/
4247	3805	dma_rmb();
4248	3806
4249		- dev_dbg(dev, "aeqe = %p, aeqe->asyn.event_type = 0x%lx\n", aeqe,
	3807	+ dev_dbg(dev, "aeqe = %pK, aeqe->asyn.event_type = 0x%lx\n",
	3808	+ aeqe,
4250	3809	roce_get_field(aeqe->asyn,
4251	3810	HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
4252	3811	HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
..	..	@@ -4309,10 +3868,8 @@
4309	3868	eq->cons_index++;
4310	3869	aeqes_found = 1;
4311	3870
4312		- if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1) {
4313		- dev_warn(dev, "cons_index overflow, set back to 0.\n");
	3871	+ if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1)
4314	3872	eq->cons_index = 0;
4315		- }
4316	3873	}
4317	3874
4318	3875	set_eq_cons_index_v1(eq, 0);
..	..	@@ -4322,8 +3879,7 @@
4322	3879
4323	3880	static struct hns_roce_ceqe get_ceqe_v1(struct hns_roce_eq eq, u32 entry)
4324	3881	{
4325		- unsigned long off = (entry & (eq->entries - 1)) *
4326		- HNS_ROCE_CEQ_ENTRY_SIZE;
	3882	+ unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQE_SIZE;
4327	3883
4328	3884	return (struct hns_roce_ceqe )((u8 )
4329	3885	(eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
..	..	@@ -4361,11 +3917,9 @@
4361	3917	++eq->cons_index;
4362	3918	ceqes_found = 1;
4363	3919
4364		- if (eq->cons_index > 2 * hr_dev->caps.ceqe_depth - 1) {
4365		- dev_warn(&eq->hr_dev->pdev->dev,
4366		- "cons_index overflow, set back to 0.\n");
	3920	+ if (eq->cons_index >
	3921	+ EQ_DEPTH_COEFF * hr_dev->caps.ceqe_depth - 1)
4367	3922	eq->cons_index = 0;
4368		- }
4369	3923	}
4370	3924
4371	3925	set_eq_cons_index_v1(eq, 0);
..	..	@@ -4377,7 +3931,7 @@
4377	3931	{
4378	3932	struct hns_roce_eq *eq = eq_ptr;
4379	3933	struct hns_roce_dev *hr_dev = eq->hr_dev;
4380		- int int_work = 0;
	3934	+ int int_work;
4381	3935
4382	3936	if (eq->type_flag == HNS_ROCE_CEQ)
4383	3937	/* CEQ irq routine, CEQ is pulse irq, not clear */
..	..	@@ -4575,9 +4129,9 @@
4575	4129	void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4576	4130	struct device *dev = &hr_dev->pdev->dev;
4577	4131	dma_addr_t tmp_dma_addr;
4578		- u32 eqconsindx_val = 0;
4579	4132	u32 eqcuridx_val = 0;
4580		- u32 eqshift_val = 0;
	4133	+ u32 eqconsindx_val;
	4134	+ u32 eqshift_val;
4581	4135	__le32 tmp2 = 0;
4582	4136	__le32 tmp1 = 0;
4583	4137	__le32 tmp = 0;
..	..	@@ -4609,7 +4163,6 @@
4609	4163	}
4610	4164
4611	4165	eq->buf_list[i].map = tmp_dma_addr;
4612		- memset(eq->buf_list[i].buf, 0, HNS_ROCE_BA_SIZE);
4613	4166	}
4614	4167	eq->cons_index = 0;
4615	4168	roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
..	..	@@ -4697,7 +4250,7 @@
4697	4250	CEQ_REG_OFFSET * i;
4698	4251	eq->entries = hr_dev->caps.ceqe_depth;
4699	4252	eq->log_entries = ilog2(eq->entries);
4700		- eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
	4253	+ eq->eqe_size = HNS_ROCE_CEQE_SIZE;
4701	4254	} else {
4702	4255	/* AEQ */
4703	4256	eq_table->eqc_base[i] = hr_dev->reg_base +
..	..	@@ -4707,7 +4260,7 @@
4707	4260	ROCEE_CAEP_AEQE_CONS_IDX_REG;
4708	4261	eq->entries = hr_dev->caps.aeqe_depth;
4709	4262	eq->log_entries = ilog2(eq->entries);
4710		- eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
	4263	+ eq->eqe_size = HNS_ROCE_AEQE_SIZE;
4711	4264	}
4712	4265	}
4713	4266
..	..	@@ -4792,6 +4345,16 @@
4792	4345	kfree(eq_table->eq);
4793	4346	}
4794	4347
	4348	+static const struct ib_device_ops hns_roce_v1_dev_ops = {
	4349	+ .destroy_qp = hns_roce_v1_destroy_qp,
	4350	+ .modify_cq = hns_roce_v1_modify_cq,
	4351	+ .poll_cq = hns_roce_v1_poll_cq,
	4352	+ .post_recv = hns_roce_v1_post_recv,
	4353	+ .post_send = hns_roce_v1_post_send,
	4354	+ .query_qp = hns_roce_v1_query_qp,
	4355	+ .req_notify_cq = hns_roce_v1_req_notify_cq,
	4356	+};
	4357	+
4795	4358	static const struct hns_roce_hw hns_roce_hw_v1 = {
4796	4359	.reset = hns_roce_v1_reset,
4797	4360	.hw_profile = hns_roce_v1_profile,
..	..	@@ -4817,6 +4380,7 @@
4817	4380	.destroy_cq = hns_roce_v1_destroy_cq,
4818	4381	.init_eq = hns_roce_v1_init_eq_table,
4819	4382	.cleanup_eq = hns_roce_v1_cleanup_eq_table,
	4383	+ .hns_roce_dev_ops = &hns_roce_v1_dev_ops,
4820	4384	};
4821	4385
4822	4386	static const struct of_device_id hns_roce_of_match[] = {
..	..	@@ -4831,19 +4395,13 @@
4831	4395	};
4832	4396	MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4833	4397
4834		-static int hns_roce_node_match(struct device dev, void fwnode)
4835		-{
4836		- return dev->fwnode == fwnode;
4837		-}
4838		-
4839	4398	static struct
4840	4399	platform_device hns_roce_find_pdev(struct fwnode_handle fwnode)
4841	4400	{
4842	4401	struct device *dev;
4843	4402
4844	4403	/* get the 'device' corresponding to the matching 'fwnode' */
4845		- dev = bus_find_device(&platform_bus_type, NULL,
4846		- fwnode, hns_roce_node_match);
	4404	+ dev = bus_find_device_by_fwnode(&platform_bus_type, fwnode);
4847	4405	/* get the platform device */
4848	4406	return dev ? to_platform_device(dev) : NULL;
4849	4407	}
..	..	@@ -4854,7 +4412,6 @@
4854	4412	struct platform_device *pdev = NULL;
4855	4413	struct net_device *netdev = NULL;
4856	4414	struct device_node *net_node;
4857		- struct resource *res;
4858	4415	int port_cnt = 0;
4859	4416	u8 phy_port;
4860	4417	int ret;
..	..	@@ -4893,8 +4450,7 @@
4893	4450	}
4894	4451
4895	4452	/* get the mapped register base address */
4896		- res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
4897		- hr_dev->reg_base = devm_ioremap_resource(dev, res);
	4453	+ hr_dev->reg_base = devm_platform_ioremap_resource(hr_dev->pdev, 0);
4898	4454	if (IS_ERR(hr_dev->reg_base))
4899	4455	return PTR_ERR(hr_dev->reg_base);
4900	4456
..	..	@@ -4969,10 +4525,8 @@
4969	4525	/* fetch the interrupt numbers */
4970	4526	for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4971	4527	hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4972		- if (hr_dev->irq[i] <= 0) {
4973		- dev_err(dev, "platform get of irq[=%d] failed!\n", i);
	4528	+ if (hr_dev->irq[i] <= 0)
4974	4529	return -EINVAL;
4975		- }
4976	4530	}
4977	4531
4978	4532	return 0;
..	..	@@ -4990,7 +4544,7 @@
4990	4544	struct hns_roce_dev *hr_dev;
4991	4545	struct device *dev = &pdev->dev;
4992	4546
4993		- hr_dev = (struct hns_roce_dev )ib_alloc_device(sizeof(hr_dev));
	4547	+ hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
4994	4548	if (!hr_dev)
4995	4549	return -ENOMEM;
4996	4550