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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/i2c/busses/i2c-xiic.c
....@@ -1,17 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * i2c-xiic.c
34  * Copyright (c) 2002-2007 Xilinx Inc.
45  * Copyright (c) 2009-2010 Intel Corporation
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
9
- *
10
- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
- * GNU General Public License for more details.
14
- *
156  *
167  * This code was implemented by Mocean Laboratories AB when porting linux
178  * to the automotive development board Russellville. The copyright holder
....@@ -55,32 +46,36 @@
5546 
5647 /**
5748  * struct xiic_i2c - Internal representation of the XIIC I2C bus
58
- * @base:	Memory base of the HW registers
59
- * @wait:	Wait queue for callers
60
- * @adap:	Kernel adapter representation
61
- * @tx_msg:	Messages from above to be sent
62
- * @lock:	Mutual exclusion
63
- * @tx_pos:	Current pos in TX message
64
- * @nmsgs:	Number of messages in tx_msg
65
- * @state:	See STATE_
66
- * @rx_msg:	Current RX message
67
- * @rx_pos:	Position within current RX message
49
+ * @dev: Pointer to device structure
50
+ * @base: Memory base of the HW registers
51
+ * @wait: Wait queue for callers
52
+ * @adap: Kernel adapter representation
53
+ * @tx_msg: Messages from above to be sent
54
+ * @lock: Mutual exclusion
55
+ * @tx_pos: Current pos in TX message
56
+ * @nmsgs: Number of messages in tx_msg
57
+ * @rx_msg: Current RX message
58
+ * @rx_pos: Position within current RX message
6859  * @endianness: big/little-endian byte order
60
+ * @clk: Pointer to AXI4-lite input clock
61
+ * @state: See STATE_
62
+ * @singlemaster: Indicates bus is single master
6963  */
7064 struct xiic_i2c {
71
-	struct device		*dev;
72
-	void __iomem		*base;
73
-	wait_queue_head_t	wait;
74
-	struct i2c_adapter	adap;
75
-	struct i2c_msg		*tx_msg;
76
-	struct mutex		lock;
77
-	unsigned int		tx_pos;
78
-	unsigned int		nmsgs;
79
-	enum xilinx_i2c_state	state;
80
-	struct i2c_msg		*rx_msg;
81
-	int			rx_pos;
82
-	enum xiic_endian	endianness;
65
+	struct device *dev;
66
+	void __iomem *base;
67
+	wait_queue_head_t wait;
68
+	struct i2c_adapter adap;
69
+	struct i2c_msg *tx_msg;
70
+	struct mutex lock;
71
+	unsigned int tx_pos;
72
+	unsigned int nmsgs;
73
+	struct i2c_msg *rx_msg;
74
+	int rx_pos;
75
+	enum xiic_endian endianness;
8376 	struct clk *clk;
77
+	enum xilinx_i2c_state state;
78
+	bool singlemaster;
8479 };
8580 
8681 
....@@ -163,6 +158,8 @@
163158 #define XIIC_RESET_MASK             0xAUL
164159 
165160 #define XIIC_PM_TIMEOUT		1000	/* ms */
161
+/* timeout waiting for the controller to respond */
162
+#define XIIC_I2C_TIMEOUT	(msecs_to_jiffies(1000))
166163 /*
167164  * The following constant is used for the device global interrupt enable
168165  * register, to enable all interrupts for the device, this is the only bit
....@@ -173,7 +170,7 @@
173170 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
174171 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
175172 
176
-static void xiic_start_xfer(struct xiic_i2c *i2c);
173
+static int xiic_start_xfer(struct xiic_i2c *i2c);
177174 static void __xiic_start_xfer(struct xiic_i2c *i2c);
178175 
179176 /*
....@@ -254,17 +251,29 @@
254251 	xiic_irq_en(i2c, mask);
255252 }
256253 
257
-static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
254
+static int xiic_clear_rx_fifo(struct xiic_i2c *i2c)
258255 {
259256 	u8 sr;
257
+	unsigned long timeout;
258
+
259
+	timeout = jiffies + XIIC_I2C_TIMEOUT;
260260 	for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
261261 		!(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
262
-		sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
262
+		sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) {
263263 		xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
264
+		if (time_after(jiffies, timeout)) {
265
+			dev_err(i2c->dev, "Failed to clear rx fifo\n");
266
+			return -ETIMEDOUT;
267
+		}
268
+	}
269
+
270
+	return 0;
264271 }
265272 
266
-static void xiic_reinit(struct xiic_i2c *i2c)
273
+static int xiic_reinit(struct xiic_i2c *i2c)
267274 {
275
+	int ret;
276
+
268277 	xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
269278 
270279 	/* Set receive Fifo depth to maximum (zero based). */
....@@ -277,12 +286,16 @@
277286 	xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
278287 
279288 	/* make sure RX fifo is empty */
280
-	xiic_clear_rx_fifo(i2c);
289
+	ret = xiic_clear_rx_fifo(i2c);
290
+	if (ret)
291
+		return ret;
281292 
282293 	/* Enable interrupts */
283294 	xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
284295 
285296 	xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
297
+
298
+	return 0;
286299 }
287300 
288301 static void xiic_deinit(struct xiic_i2c *i2c)
....@@ -515,6 +528,15 @@
515528 	if (i2c->tx_msg)
516529 		return -EBUSY;
517530 
531
+	/* In single master mode bus can only be busy, when in use by this
532
+	 * driver. If the register indicates bus being busy for some reason we
533
+	 * should ignore it, since bus will never be released and i2c will be
534
+	 * stuck forever.
535
+	 */
536
+	if (i2c->singlemaster) {
537
+		return 0;
538
+	}
539
+
518540 	/* for instance if previous transfer was terminated due to TX error
519541 	 * it might be that the bus is on it's way to become available
520542 	 * give it at most 3 ms to wake
....@@ -662,12 +684,18 @@
662684 
663685 }
664686 
665
-static void xiic_start_xfer(struct xiic_i2c *i2c)
687
+static int xiic_start_xfer(struct xiic_i2c *i2c)
666688 {
689
+	int ret;
667690 	mutex_lock(&i2c->lock);
668
-	xiic_reinit(i2c);
669
-	__xiic_start_xfer(i2c);
691
+
692
+	ret = xiic_reinit(i2c);
693
+	if (!ret)
694
+		__xiic_start_xfer(i2c);
695
+
670696 	mutex_unlock(&i2c->lock);
697
+
698
+	return ret;
671699 }
672700 
673701 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
....@@ -678,7 +706,7 @@
678706 	dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
679707 		xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
680708 
681
-	err = pm_runtime_get_sync(i2c->dev);
709
+	err = pm_runtime_resume_and_get(i2c->dev);
682710 	if (err < 0)
683711 		return err;
684712 
....@@ -689,7 +717,11 @@
689717 	i2c->tx_msg = msgs;
690718 	i2c->nmsgs = num;
691719 
692
-	xiic_start_xfer(i2c);
720
+	err = xiic_start_xfer(i2c);
721
+	if (err < 0) {
722
+		dev_err(adap->dev.parent, "Error xiic_start_xfer\n");
723
+		goto out;
724
+	}
693725 
694726 	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
695727 		(i2c->state == STATE_DONE), HZ)) {
....@@ -724,7 +756,6 @@
724756 
725757 static const struct i2c_adapter xiic_adapter = {
726758 	.owner = THIS_MODULE,
727
-	.name = DRIVER_NAME,
728759 	.class = I2C_CLASS_DEPRECATED,
729760 	.algo = &xiic_algorithm,
730761 	.quirks = &xiic_quirks,
....@@ -761,13 +792,16 @@
761792 	i2c_set_adapdata(&i2c->adap, i2c);
762793 	i2c->adap.dev.parent = &pdev->dev;
763794 	i2c->adap.dev.of_node = pdev->dev.of_node;
795
+	snprintf(i2c->adap.name, sizeof(i2c->adap.name),
796
+		 DRIVER_NAME " %s", pdev->name);
764797 
765798 	mutex_init(&i2c->lock);
766799 	init_waitqueue_head(&i2c->wait);
767800 
768801 	i2c->clk = devm_clk_get(&pdev->dev, NULL);
769802 	if (IS_ERR(i2c->clk)) {
770
-		dev_err(&pdev->dev, "input clock not found.\n");
803
+		if (PTR_ERR(i2c->clk) != -EPROBE_DEFER)
804
+			dev_err(&pdev->dev, "input clock not found.\n");
771805 		return PTR_ERR(i2c->clk);
772806 	}
773807 	ret = clk_prepare_enable(i2c->clk);
....@@ -776,10 +810,10 @@
776810 		return ret;
777811 	}
778812 	i2c->dev = &pdev->dev;
779
-	pm_runtime_enable(i2c->dev);
780813 	pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);
781814 	pm_runtime_use_autosuspend(i2c->dev);
782815 	pm_runtime_set_active(i2c->dev);
816
+	pm_runtime_enable(i2c->dev);
783817 	ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr,
784818 					xiic_process, IRQF_ONESHOT,
785819 					pdev->name, i2c);
....@@ -788,6 +822,9 @@
788822 		dev_err(&pdev->dev, "Cannot claim IRQ\n");
789823 		goto err_clk_dis;
790824 	}
825
+
826
+	i2c->singlemaster =
827
+		of_property_read_bool(pdev->dev.of_node, "single-master");
791828 
792829 	/*
793830 	 * Detect endianness
....@@ -801,7 +838,11 @@
801838 	if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
802839 		i2c->endianness = BIG;
803840 
804
-	xiic_reinit(i2c);
841
+	ret = xiic_reinit(i2c);
842
+	if (ret < 0) {
843
+		dev_err(&pdev->dev, "Cannot xiic_reinit\n");
844
+		goto err_clk_dis;
845
+	}
805846 
806847 	/* add i2c adapter to i2c tree */
807848 	ret = i2c_add_adapter(&i2c->adap);
....@@ -813,7 +854,7 @@
813854 	if (pdata) {
814855 		/* add in known devices to the bus */
815856 		for (i = 0; i < pdata->num_devices; i++)
816
-			i2c_new_device(&i2c->adap, pdata->devices + i);
857
+			i2c_new_client_device(&i2c->adap, pdata->devices + i);
817858 	}
818859 
819860 	return 0;
....@@ -833,14 +874,16 @@
833874 	/* remove adapter & data */
834875 	i2c_del_adapter(&i2c->adap);
835876 
836
-	ret = clk_prepare_enable(i2c->clk);
837
-	if (ret) {
838
-		dev_err(&pdev->dev, "Unable to enable clock.\n");
877
+	ret = pm_runtime_resume_and_get(i2c->dev);
878
+	if (ret < 0)
839879 		return ret;
840
-	}
880
+
841881 	xiic_deinit(i2c);
882
+	pm_runtime_put_sync(i2c->dev);
842883 	clk_disable_unprepare(i2c->clk);
843884 	pm_runtime_disable(&pdev->dev);
885
+	pm_runtime_set_suspended(&pdev->dev);
886
+	pm_runtime_dont_use_autosuspend(&pdev->dev);
844887 
845888 	return 0;
846889 }
....@@ -892,6 +935,7 @@
892935 
893936 module_platform_driver(xiic_i2c_driver);
894937 
938
+MODULE_ALIAS("platform:" DRIVER_NAME);
895939 MODULE_AUTHOR("info@mocean-labs.com");
896940 MODULE_DESCRIPTION("Xilinx I2C bus driver");
897941 MODULE_LICENSE("GPL v2");