forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/i2c/busses/i2c-designware-common.c
....@@ -8,17 +8,22 @@
88  * Copyright (C) 2007 MontaVista Software Inc.
99  * Copyright (C) 2009 Provigent Ltd.
1010  */
11
+#include <linux/acpi.h>
1112 #include <linux/clk.h>
1213 #include <linux/delay.h>
13
-#include <linux/export.h>
14
-#include <linux/errno.h>
14
+#include <linux/device.h>
1515 #include <linux/err.h>
16
+#include <linux/errno.h>
17
+#include <linux/export.h>
1618 #include <linux/i2c.h>
1719 #include <linux/interrupt.h>
1820 #include <linux/io.h>
21
+#include <linux/kernel.h>
1922 #include <linux/module.h>
2023 #include <linux/pm_runtime.h>
24
+#include <linux/regmap.h>
2125 #include <linux/swab.h>
26
+#include <linux/types.h>
2227 
2328 #include "i2c-designware-core.h"
2429 
....@@ -53,68 +58,275 @@
5358 		"incorrect slave-transmitter mode configuration",
5459 };
5560 
56
-u32 dw_readl(struct dw_i2c_dev *dev, int offset)
61
+static int dw_reg_read(void *context, unsigned int reg, unsigned int *val)
5762 {
58
-	u32 value;
63
+	struct dw_i2c_dev *dev = context;
5964 
60
-	if (dev->flags & ACCESS_16BIT)
61
-		value = readw_relaxed(dev->base + offset) |
62
-			(readw_relaxed(dev->base + offset + 2) << 16);
63
-	else
64
-		value = readl_relaxed(dev->base + offset);
65
+	*val = readl_relaxed(dev->base + reg);
6566 
66
-	if (dev->flags & ACCESS_SWAP)
67
-		return swab32(value);
68
-	else
69
-		return value;
67
+	return 0;
7068 }
7169 
72
-void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
70
+static int dw_reg_write(void *context, unsigned int reg, unsigned int val)
7371 {
74
-	if (dev->flags & ACCESS_SWAP)
75
-		b = swab32(b);
72
+	struct dw_i2c_dev *dev = context;
7673 
77
-	if (dev->flags & ACCESS_16BIT) {
78
-		writew_relaxed((u16)b, dev->base + offset);
79
-		writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
80
-	} else {
81
-		writel_relaxed(b, dev->base + offset);
82
-	}
74
+	writel_relaxed(val, dev->base + reg);
75
+
76
+	return 0;
77
+}
78
+
79
+static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val)
80
+{
81
+	struct dw_i2c_dev *dev = context;
82
+
83
+	*val = swab32(readl_relaxed(dev->base + reg));
84
+
85
+	return 0;
86
+}
87
+
88
+static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
89
+{
90
+	struct dw_i2c_dev *dev = context;
91
+
92
+	writel_relaxed(swab32(val), dev->base + reg);
93
+
94
+	return 0;
95
+}
96
+
97
+static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
98
+{
99
+	struct dw_i2c_dev *dev = context;
100
+
101
+	*val = readw_relaxed(dev->base + reg) |
102
+		(readw_relaxed(dev->base + reg + 2) << 16);
103
+
104
+	return 0;
105
+}
106
+
107
+static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
108
+{
109
+	struct dw_i2c_dev *dev = context;
110
+
111
+	writew_relaxed(val, dev->base + reg);
112
+	writew_relaxed(val >> 16, dev->base + reg + 2);
113
+
114
+	return 0;
83115 }
84116 
85117 /**
86
- * i2c_dw_set_reg_access() - Set register access flags
118
+ * i2c_dw_init_regmap() - Initialize registers map
87119  * @dev: device private data
88120  *
89
- * Autodetects needed register access mode and sets access flags accordingly.
90
- * This must be called before doing any other register access.
121
+ * Autodetects needed register access mode and creates the regmap with
122
+ * corresponding read/write callbacks. This must be called before doing any
123
+ * other register access.
91124  */
92
-int i2c_dw_set_reg_access(struct dw_i2c_dev *dev)
125
+int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
93126 {
127
+	struct regmap_config map_cfg = {
128
+		.reg_bits = 32,
129
+		.val_bits = 32,
130
+		.reg_stride = 4,
131
+		.disable_locking = true,
132
+		.reg_read = dw_reg_read,
133
+		.reg_write = dw_reg_write,
134
+		.max_register = DW_IC_COMP_TYPE,
135
+	};
94136 	u32 reg;
95137 	int ret;
138
+
139
+	/*
140
+	 * Skip detecting the registers map configuration if the regmap has
141
+	 * already been provided by a higher code.
142
+	 */
143
+	if (dev->map)
144
+		return 0;
96145 
97146 	ret = i2c_dw_acquire_lock(dev);
98147 	if (ret)
99148 		return ret;
100149 
101
-	reg = dw_readl(dev, DW_IC_COMP_TYPE);
150
+	reg = readl(dev->base + DW_IC_COMP_TYPE);
102151 	i2c_dw_release_lock(dev);
103152 
104153 	if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
105
-		/* Configure register endianess access */
106
-		dev->flags |= ACCESS_SWAP;
154
+		map_cfg.reg_read = dw_reg_read_swab;
155
+		map_cfg.reg_write = dw_reg_write_swab;
107156 	} else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
108
-		/* Configure register access mode 16bit */
109
-		dev->flags |= ACCESS_16BIT;
157
+		map_cfg.reg_read = dw_reg_read_word;
158
+		map_cfg.reg_write = dw_reg_write_word;
110159 	} else if (reg != DW_IC_COMP_TYPE_VALUE) {
111160 		dev_err(dev->dev,
112161 			"Unknown Synopsys component type: 0x%08x\n", reg);
113162 		return -ENODEV;
114163 	}
115164 
165
+	/*
166
+	 * Note we'll check the return value of the regmap IO accessors only
167
+	 * at the probe stage. The rest of the code won't do this because
168
+	 * basically we have MMIO-based regmap so non of the read/write methods
169
+	 * can fail.
170
+	 */
171
+	dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg);
172
+	if (IS_ERR(dev->map)) {
173
+		dev_err(dev->dev, "Failed to init the registers map\n");
174
+		return PTR_ERR(dev->map);
175
+	}
176
+
116177 	return 0;
117178 }
179
+
180
+static const u32 supported_speeds[] = {
181
+	I2C_MAX_HIGH_SPEED_MODE_FREQ,
182
+	I2C_MAX_FAST_MODE_PLUS_FREQ,
183
+	I2C_MAX_FAST_MODE_FREQ,
184
+	I2C_MAX_STANDARD_MODE_FREQ,
185
+};
186
+
187
+int i2c_dw_validate_speed(struct dw_i2c_dev *dev)
188
+{
189
+	struct i2c_timings *t = &dev->timings;
190
+	unsigned int i;
191
+
192
+	/*
193
+	 * Only standard mode at 100kHz, fast mode at 400kHz,
194
+	 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
195
+	 */
196
+	for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
197
+		if (t->bus_freq_hz == supported_speeds[i])
198
+			return 0;
199
+	}
200
+
201
+	dev_err(dev->dev,
202
+		"%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
203
+		t->bus_freq_hz);
204
+
205
+	return -EINVAL;
206
+}
207
+EXPORT_SYMBOL_GPL(i2c_dw_validate_speed);
208
+
209
+#ifdef CONFIG_ACPI
210
+
211
+#include <linux/dmi.h>
212
+
213
+/*
214
+ * The HCNT/LCNT information coming from ACPI should be the most accurate
215
+ * for given platform. However, some systems get it wrong. On such systems
216
+ * we get better results by calculating those based on the input clock.
217
+ */
218
+static const struct dmi_system_id i2c_dw_no_acpi_params[] = {
219
+	{
220
+		.ident = "Dell Inspiron 7348",
221
+		.matches = {
222
+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
223
+			DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"),
224
+		},
225
+	},
226
+	{}
227
+};
228
+
229
+static void i2c_dw_acpi_params(struct device *device, char method[],
230
+			       u16 *hcnt, u16 *lcnt, u32 *sda_hold)
231
+{
232
+	struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
233
+	acpi_handle handle = ACPI_HANDLE(device);
234
+	union acpi_object *obj;
235
+
236
+	if (dmi_check_system(i2c_dw_no_acpi_params))
237
+		return;
238
+
239
+	if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
240
+		return;
241
+
242
+	obj = (union acpi_object *)buf.pointer;
243
+	if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
244
+		const union acpi_object *objs = obj->package.elements;
245
+
246
+		*hcnt = (u16)objs[0].integer.value;
247
+		*lcnt = (u16)objs[1].integer.value;
248
+		*sda_hold = (u32)objs[2].integer.value;
249
+	}
250
+
251
+	kfree(buf.pointer);
252
+}
253
+
254
+int i2c_dw_acpi_configure(struct device *device)
255
+{
256
+	struct dw_i2c_dev *dev = dev_get_drvdata(device);
257
+	struct i2c_timings *t = &dev->timings;
258
+	u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
259
+
260
+	/*
261
+	 * Try to get SDA hold time and *CNT values from an ACPI method for
262
+	 * selected speed modes.
263
+	 */
264
+	i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
265
+	i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
266
+	i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
267
+	i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
268
+
269
+	switch (t->bus_freq_hz) {
270
+	case I2C_MAX_STANDARD_MODE_FREQ:
271
+		dev->sda_hold_time = ss_ht;
272
+		break;
273
+	case I2C_MAX_FAST_MODE_PLUS_FREQ:
274
+		dev->sda_hold_time = fp_ht;
275
+		break;
276
+	case I2C_MAX_HIGH_SPEED_MODE_FREQ:
277
+		dev->sda_hold_time = hs_ht;
278
+		break;
279
+	case I2C_MAX_FAST_MODE_FREQ:
280
+	default:
281
+		dev->sda_hold_time = fs_ht;
282
+		break;
283
+	}
284
+
285
+	return 0;
286
+}
287
+EXPORT_SYMBOL_GPL(i2c_dw_acpi_configure);
288
+
289
+static u32 i2c_dw_acpi_round_bus_speed(struct device *device)
290
+{
291
+	u32 acpi_speed;
292
+	int i;
293
+
294
+	acpi_speed = i2c_acpi_find_bus_speed(device);
295
+	/*
296
+	 * Some DSTDs use a non standard speed, round down to the lowest
297
+	 * standard speed.
298
+	 */
299
+	for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
300
+		if (acpi_speed >= supported_speeds[i])
301
+			return supported_speeds[i];
302
+	}
303
+
304
+	return 0;
305
+}
306
+
307
+#else	/* CONFIG_ACPI */
308
+
309
+static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; }
310
+
311
+#endif	/* CONFIG_ACPI */
312
+
313
+void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev)
314
+{
315
+	u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev);
316
+	struct i2c_timings *t = &dev->timings;
317
+
318
+	/*
319
+	 * Find bus speed from the "clock-frequency" device property, ACPI
320
+	 * or by using fast mode if neither is set.
321
+	 */
322
+	if (acpi_speed && t->bus_freq_hz)
323
+		t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
324
+	else if (acpi_speed || t->bus_freq_hz)
325
+		t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
326
+	else
327
+		t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
328
+}
329
+EXPORT_SYMBOL_GPL(i2c_dw_adjust_bus_speed);
118330 
119331 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
120332 {
....@@ -181,19 +393,25 @@
181393 		return ret;
182394 
183395 	/* Configure SDA Hold Time if required */
184
-	reg = dw_readl(dev, DW_IC_COMP_VERSION);
396
+	ret = regmap_read(dev->map, DW_IC_COMP_VERSION, &reg);
397
+	if (ret)
398
+		goto err_release_lock;
399
+
185400 	if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
186401 		if (!dev->sda_hold_time) {
187402 			/* Keep previous hold time setting if no one set it */
188
-			dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
403
+			ret = regmap_read(dev->map, DW_IC_SDA_HOLD,
404
+					  &dev->sda_hold_time);
405
+			if (ret)
406
+				goto err_release_lock;
189407 		}
190408 
191409 		/*
192410 		 * Workaround for avoiding TX arbitration lost in case I2C
193
-		 * slave pulls SDA down "too quickly" after falling egde of
411
+		 * slave pulls SDA down "too quickly" after falling edge of
194412 		 * SCL by enabling non-zero SDA RX hold. Specification says it
195413 		 * extends incoming SDA low to high transition while SCL is
196
-		 * high but it apprears to help also above issue.
414
+		 * high but it appears to help also above issue.
197415 		 */
198416 		if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
199417 			dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
....@@ -201,20 +419,24 @@
201419 		dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
202420 			dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,
203421 			dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);
422
+	} else if (dev->set_sda_hold_time) {
423
+		dev->set_sda_hold_time(dev);
204424 	} else if (dev->sda_hold_time) {
205425 		dev_warn(dev->dev,
206426 			"Hardware too old to adjust SDA hold time.\n");
207427 		dev->sda_hold_time = 0;
208428 	}
209429 
430
+err_release_lock:
210431 	i2c_dw_release_lock(dev);
211432 
212
-	return 0;
433
+	return ret;
213434 }
214435 
215436 void __i2c_dw_disable(struct dw_i2c_dev *dev)
216437 {
217438 	int timeout = 100;
439
+	u32 status;
218440 
219441 	do {
220442 		__i2c_dw_disable_nowait(dev);
....@@ -222,7 +444,8 @@
222444 		 * The enable status register may be unimplemented, but
223445 		 * in that case this test reads zero and exits the loop.
224446 		 */
225
-		if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == 0)
447
+		regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status);
448
+		if ((status & 1) == 0)
226449 			return;
227450 
228451 		/*
....@@ -249,13 +472,24 @@
249472 
250473 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
251474 {
252
-	if (IS_ERR(dev->clk))
253
-		return PTR_ERR(dev->clk);
475
+	int ret;
254476 
255
-	if (prepare)
256
-		return clk_prepare_enable(dev->clk);
477
+	if (prepare) {
478
+		/* Optional interface clock */
479
+		ret = clk_prepare_enable(dev->pclk);
480
+		if (ret)
481
+			return ret;
482
+
483
+		ret = clk_prepare_enable(dev->clk);
484
+		if (ret)
485
+			clk_disable_unprepare(dev->pclk);
486
+
487
+		return ret;
488
+	}
257489 
258490 	clk_disable_unprepare(dev->clk);
491
+	clk_disable_unprepare(dev->pclk);
492
+
259493 	return 0;
260494 }
261495 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
....@@ -267,7 +501,7 @@
267501 	if (!dev->acquire_lock)
268502 		return 0;
269503 
270
-	ret = dev->acquire_lock(dev);
504
+	ret = dev->acquire_lock();
271505 	if (!ret)
272506 		return 0;
273507 
....@@ -279,7 +513,7 @@
279513 void i2c_dw_release_lock(struct dw_i2c_dev *dev)
280514 {
281515 	if (dev->release_lock)
282
-		dev->release_lock(dev);
516
+		dev->release_lock();
283517 }
284518 
285519 /*
....@@ -287,22 +521,23 @@
287521  */
288522 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
289523 {
290
-	int timeout = TIMEOUT;
524
+	u32 status;
525
+	int ret;
291526 
292
-	while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
293
-		if (timeout <= 0) {
294
-			dev_warn(dev->dev, "timeout waiting for bus ready\n");
295
-			i2c_recover_bus(&dev->adapter);
527
+	ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
528
+				       !(status & DW_IC_STATUS_ACTIVITY),
529
+				       1100, 20000);
530
+	if (ret) {
531
+		dev_warn(dev->dev, "timeout waiting for bus ready\n");
296532 
297
-			if (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY)
298
-				return -ETIMEDOUT;
299
-			return 0;
300
-		}
301
-		timeout--;
302
-		usleep_range(1000, 1100);
533
+		i2c_recover_bus(&dev->adapter);
534
+
535
+		regmap_read(dev->map, DW_IC_STATUS, &status);
536
+		if (!(status & DW_IC_STATUS_ACTIVITY))
537
+			ret = 0;
303538 	}
304539 
305
-	return 0;
540
+	return ret;
306541 }
307542 
308543 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
....@@ -328,6 +563,34 @@
328563 		return -EIO;
329564 }
330565 
566
+int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
567
+{
568
+	u32 param, tx_fifo_depth, rx_fifo_depth;
569
+	int ret;
570
+
571
+	/*
572
+	 * Try to detect the FIFO depth if not set by interface driver,
573
+	 * the depth could be from 2 to 256 from HW spec.
574
+	 */
575
+	ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &param);
576
+	if (ret)
577
+		return ret;
578
+
579
+	tx_fifo_depth = ((param >> 16) & 0xff) + 1;
580
+	rx_fifo_depth = ((param >> 8)  & 0xff) + 1;
581
+	if (!dev->tx_fifo_depth) {
582
+		dev->tx_fifo_depth = tx_fifo_depth;
583
+		dev->rx_fifo_depth = rx_fifo_depth;
584
+	} else if (tx_fifo_depth >= 2) {
585
+		dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth,
586
+				tx_fifo_depth);
587
+		dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth,
588
+				rx_fifo_depth);
589
+	}
590
+
591
+	return 0;
592
+}
593
+
331594 u32 i2c_dw_func(struct i2c_adapter *adap)
332595 {
333596 	struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
....@@ -337,24 +600,20 @@
337600 
338601 void i2c_dw_disable(struct dw_i2c_dev *dev)
339602 {
603
+	u32 dummy;
604
+
340605 	/* Disable controller */
341606 	__i2c_dw_disable(dev);
342607 
343
-	/* Disable all interupts */
344
-	dw_writel(dev, 0, DW_IC_INTR_MASK);
345
-	dw_readl(dev, DW_IC_CLR_INTR);
608
+	/* Disable all interrupts */
609
+	regmap_write(dev->map, DW_IC_INTR_MASK, 0);
610
+	regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
346611 }
347612 
348613 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
349614 {
350
-	dw_writel(dev, 0, DW_IC_INTR_MASK);
615
+	regmap_write(dev->map, DW_IC_INTR_MASK, 0);
351616 }
352
-
353
-u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
354
-{
355
-	return dw_readl(dev, DW_IC_COMP_PARAM_1);
356
-}
357
-EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
358617 
359618 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
360619 MODULE_LICENSE("GPL");