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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/i2c/busses/i2c-cadence.c
....@@ -1,13 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * I2C bus driver for the Cadence I2C controller.
34  *
45  * Copyright (C) 2009 - 2014 Xilinx, Inc.
5
- *
6
- * This program is free software; you can redistribute it
7
- * and/or modify it under the terms of the GNU General Public
8
- * License as published by the Free Software Foundation;
9
- * either version 2 of the License, or (at your option) any
10
- * later version.
116  */
127 
138 #include <linux/clk.h>
....@@ -28,6 +23,7 @@
2823 #define CDNS_I2C_ISR_OFFSET		0x10 /* IRQ Status Register, RW */
2924 #define CDNS_I2C_XFER_SIZE_OFFSET	0x14 /* Transfer Size Register, RW */
3025 #define CDNS_I2C_TIME_OUT_OFFSET	0x1C /* Time Out Register, RW */
26
+#define CDNS_I2C_IMR_OFFSET		0x20 /* IRQ Mask Register, RO */
3127 #define CDNS_I2C_IER_OFFSET		0x24 /* IRQ Enable Register, WO */
3228 #define CDNS_I2C_IDR_OFFSET		0x28 /* IRQ Disable Register, WO */
3329 
....@@ -45,9 +41,17 @@
4541 #define CDNS_I2C_CR_DIVB_SHIFT		8
4642 #define CDNS_I2C_CR_DIVB_MASK		(0x3f << CDNS_I2C_CR_DIVB_SHIFT)
4743 
44
+#define CDNS_I2C_CR_MASTER_EN_MASK	(CDNS_I2C_CR_NEA | \
45
+					 CDNS_I2C_CR_ACK_EN | \
46
+					 CDNS_I2C_CR_MS)
47
+
48
+#define CDNS_I2C_CR_SLAVE_EN_MASK	~CDNS_I2C_CR_MASTER_EN_MASK
49
+
4850 /* Status Register Bit mask definitions */
4951 #define CDNS_I2C_SR_BA		BIT(8)
52
+#define CDNS_I2C_SR_TXDV	BIT(6)
5053 #define CDNS_I2C_SR_RXDV	BIT(5)
54
+#define CDNS_I2C_SR_RXRW	BIT(3)
5155 
5256 /*
5357  * I2C Address Register Bit mask definitions
....@@ -96,6 +100,14 @@
96100 					 CDNS_I2C_IXR_DATA | \
97101 					 CDNS_I2C_IXR_COMP)
98102 
103
+#define CDNS_I2C_IXR_SLAVE_INTR_MASK	(CDNS_I2C_IXR_RX_UNF | \
104
+					 CDNS_I2C_IXR_TX_OVF | \
105
+					 CDNS_I2C_IXR_RX_OVF | \
106
+					 CDNS_I2C_IXR_TO | \
107
+					 CDNS_I2C_IXR_NACK | \
108
+					 CDNS_I2C_IXR_DATA | \
109
+					 CDNS_I2C_IXR_COMP)
110
+
99111 #define CDNS_I2C_TIMEOUT		msecs_to_jiffies(1000)
100112 /* timeout for pm runtime autosuspend */
101113 #define CNDS_I2C_PM_TIMEOUT		1000	/* ms */
....@@ -109,9 +121,6 @@
109121 
110122 #define DRIVER_NAME		"cdns-i2c"
111123 
112
-#define CDNS_I2C_SPEED_MAX	400000
113
-#define CDNS_I2C_SPEED_DEFAULT	100000
114
-
115124 #define CDNS_I2C_DIVA_MAX	4
116125 #define CDNS_I2C_DIVB_MAX	64
117126 
....@@ -121,6 +130,32 @@
121130 
122131 #define cdns_i2c_readreg(offset)       readl_relaxed(id->membase + offset)
123132 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
133
+
134
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
135
+/**
136
+ * enum cdns_i2c_mode - I2C Controller current operating mode
137
+ *
138
+ * @CDNS_I2C_MODE_SLAVE:       I2C controller operating in slave mode
139
+ * @CDNS_I2C_MODE_MASTER:      I2C Controller operating in master mode
140
+ */
141
+enum cdns_i2c_mode {
142
+	CDNS_I2C_MODE_SLAVE,
143
+	CDNS_I2C_MODE_MASTER,
144
+};
145
+
146
+/**
147
+ * enum cdns_i2c_slave_mode - Slave state when I2C is operating in slave mode
148
+ *
149
+ * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle
150
+ * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master
151
+ * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master
152
+ */
153
+enum cdns_i2c_slave_state {
154
+	CDNS_I2C_SLAVE_STATE_IDLE,
155
+	CDNS_I2C_SLAVE_STATE_SEND,
156
+	CDNS_I2C_SLAVE_STATE_RECV,
157
+};
158
+#endif
124159 
125160 /**
126161  * struct cdns_i2c - I2C device private data structure
....@@ -143,6 +178,10 @@
143178  * @clk:		Pointer to struct clk
144179  * @clk_rate_change_nb:	Notifier block for clock rate changes
145180  * @quirks:		flag for broken hold bit usage in r1p10
181
+ * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register
182
+ * @slave:		Registered slave instance.
183
+ * @dev_mode:		I2C operating role(master/slave).
184
+ * @slave_state:	I2C Slave state(idle/read/write).
146185  */
147186 struct cdns_i2c {
148187 	struct device		*dev;
....@@ -163,6 +202,12 @@
163202 	struct clk *clk;
164203 	struct notifier_block clk_rate_change_nb;
165204 	u32 quirks;
205
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
206
+	u16 ctrl_reg_diva_divb;
207
+	struct i2c_client *slave;
208
+	enum cdns_i2c_mode dev_mode;
209
+	enum cdns_i2c_slave_state slave_state;
210
+#endif
166211 };
167212 
168213 struct cdns_platform_data {
....@@ -191,21 +236,159 @@
191236 		(id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
192237 }
193238 
239
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
240
+static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id)
241
+{
242
+	/* Disable all interrupts */
243
+	cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
244
+
245
+	/* Clear FIFO and transfer size */
246
+	cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
247
+
248
+	/* Update device mode and state */
249
+	id->dev_mode = mode;
250
+	id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
251
+
252
+	switch (mode) {
253
+	case CDNS_I2C_MODE_MASTER:
254
+		/* Enable i2c master */
255
+		cdns_i2c_writereg(id->ctrl_reg_diva_divb |
256
+				  CDNS_I2C_CR_MASTER_EN_MASK,
257
+				  CDNS_I2C_CR_OFFSET);
258
+		/*
259
+		 * This delay is needed to give the IP some time to switch to
260
+		 * the master mode. With lower values(like 110 us) i2cdetect
261
+		 * will not detect any slave and without this delay, the IP will
262
+		 * trigger a timeout interrupt.
263
+		 */
264
+		usleep_range(115, 125);
265
+		break;
266
+	case CDNS_I2C_MODE_SLAVE:
267
+		/* Enable i2c slave */
268
+		cdns_i2c_writereg(id->ctrl_reg_diva_divb &
269
+				  CDNS_I2C_CR_SLAVE_EN_MASK,
270
+				  CDNS_I2C_CR_OFFSET);
271
+
272
+		/* Setting slave address */
273
+		cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK,
274
+				  CDNS_I2C_ADDR_OFFSET);
275
+
276
+		/* Enable slave send/receive interrupts */
277
+		cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK,
278
+				  CDNS_I2C_IER_OFFSET);
279
+		break;
280
+	}
281
+}
282
+
283
+static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id)
284
+{
285
+	u8 bytes;
286
+	unsigned char data;
287
+
288
+	/* Prepare backend for data reception */
289
+	if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
290
+		id->slave_state = CDNS_I2C_SLAVE_STATE_RECV;
291
+		i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL);
292
+	}
293
+
294
+	/* Fetch number of bytes to receive */
295
+	bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
296
+
297
+	/* Read data and send to backend */
298
+	while (bytes--) {
299
+		data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
300
+		i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data);
301
+	}
302
+}
303
+
304
+static void cdns_i2c_slave_send_data(struct cdns_i2c *id)
305
+{
306
+	u8 data;
307
+
308
+	/* Prepare backend for data transmission */
309
+	if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
310
+		id->slave_state = CDNS_I2C_SLAVE_STATE_SEND;
311
+		i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data);
312
+	} else {
313
+		i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data);
314
+	}
315
+
316
+	/* Send data over bus */
317
+	cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET);
318
+}
319
+
194320 /**
195
- * cdns_i2c_isr - Interrupt handler for the I2C device
196
- * @irq:	irq number for the I2C device
197
- * @ptr:	void pointer to cdns_i2c structure
321
+ * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role
322
+ * @ptr:       Pointer to I2C device private data
198323  *
199
- * This function handles the data interrupt, transfer complete interrupt and
200
- * the error interrupts of the I2C device.
324
+ * This function handles the data interrupt and transfer complete interrupt of
325
+ * the I2C device in slave role.
201326  *
202327  * Return: IRQ_HANDLED always
203328  */
204
-static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
329
+static irqreturn_t cdns_i2c_slave_isr(void *ptr)
205330 {
206
-	unsigned int isr_status, avail_bytes, updatetx;
331
+	struct cdns_i2c *id = ptr;
332
+	unsigned int isr_status, i2c_status;
333
+
334
+	/* Fetch the interrupt status */
335
+	isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
336
+	cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
337
+
338
+	/* Ignore masked interrupts */
339
+	isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET);
340
+
341
+	/* Fetch transfer mode (send/receive) */
342
+	i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
343
+
344
+	/* Handle data send/receive */
345
+	if (i2c_status & CDNS_I2C_SR_RXRW) {
346
+		/* Send data to master */
347
+		if (isr_status & CDNS_I2C_IXR_DATA)
348
+			cdns_i2c_slave_send_data(id);
349
+
350
+		if (isr_status & CDNS_I2C_IXR_COMP) {
351
+			id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
352
+			i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
353
+		}
354
+	} else {
355
+		/* Receive data from master */
356
+		if (isr_status & CDNS_I2C_IXR_DATA)
357
+			cdns_i2c_slave_rcv_data(id);
358
+
359
+		if (isr_status & CDNS_I2C_IXR_COMP) {
360
+			cdns_i2c_slave_rcv_data(id);
361
+			id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
362
+			i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
363
+		}
364
+	}
365
+
366
+	/* Master indicated xfer stop or fifo underflow/overflow */
367
+	if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF |
368
+			  CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) {
369
+		id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
370
+		i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
371
+		cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
372
+	}
373
+
374
+	return IRQ_HANDLED;
375
+}
376
+#endif
377
+
378
+/**
379
+ * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role
380
+ * @ptr:       Pointer to I2C device private data
381
+ *
382
+ * This function handles the data interrupt, transfer complete interrupt and
383
+ * the error interrupts of the I2C device in master role.
384
+ *
385
+ * Return: IRQ_HANDLED always
386
+ */
387
+static irqreturn_t cdns_i2c_master_isr(void *ptr)
388
+{
389
+	unsigned int isr_status, avail_bytes;
207390 	unsigned int bytes_to_send;
208
-	bool hold_quirk;
391
+	bool updatetx;
209392 	struct cdns_i2c *id = ptr;
210393 	/* Signal completion only after everything is updated */
211394 	int done_flag = 0;
....@@ -213,6 +396,7 @@
213396 
214397 	isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
215398 	cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
399
+	id->err_status = 0;
216400 
217401 	/* Handling nack and arbitration lost interrupt */
218402 	if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
....@@ -224,11 +408,7 @@
224408 	 * Check if transfer size register needs to be updated again for a
225409 	 * large data receive operation.
226410 	 */
227
-	updatetx = 0;
228
-	if (id->recv_count > id->curr_recv_count)
229
-		updatetx = 1;
230
-
231
-	hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
411
+	updatetx = id->recv_count > id->curr_recv_count;
232412 
233413 	/* When receiving, handle data interrupt and completion interrupt */
234414 	if (id->p_recv_buf &&
....@@ -237,21 +417,29 @@
237417 		/* Read data if receive data valid is set */
238418 		while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
239419 		       CDNS_I2C_SR_RXDV) {
240
-			/*
241
-			 * Clear hold bit that was set for FIFO control if
242
-			 * RX data left is less than FIFO depth, unless
243
-			 * repeated start is selected.
244
-			 */
245
-			if ((id->recv_count < CDNS_I2C_FIFO_DEPTH) &&
246
-			    !id->bus_hold_flag)
247
-				cdns_i2c_clear_bus_hold(id);
420
+			if (id->recv_count > 0) {
421
+				*(id->p_recv_buf)++ =
422
+					cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
423
+				id->recv_count--;
424
+				id->curr_recv_count--;
248425 
249
-			*(id->p_recv_buf)++ =
250
-				cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
251
-			id->recv_count--;
252
-			id->curr_recv_count--;
426
+				/*
427
+				 * Clear hold bit that was set for FIFO control
428
+				 * if RX data left is less than or equal to
429
+				 * FIFO DEPTH unless repeated start is selected
430
+				 */
431
+				if (id->recv_count <= CDNS_I2C_FIFO_DEPTH &&
432
+				    !id->bus_hold_flag)
433
+					cdns_i2c_clear_bus_hold(id);
253434 
254
-			if (cdns_is_holdquirk(id, hold_quirk))
435
+			} else {
436
+				dev_err(id->adap.dev.parent,
437
+					"xfer_size reg rollover. xfer aborted!\n");
438
+				id->err_status |= CDNS_I2C_IXR_TO;
439
+				break;
440
+			}
441
+
442
+			if (cdns_is_holdquirk(id, updatetx))
255443 				break;
256444 		}
257445 
....@@ -262,7 +450,7 @@
262450 		 * maintain transfer size non-zero while performing a large
263451 		 * receive operation.
264452 		 */
265
-		if (cdns_is_holdquirk(id, hold_quirk)) {
453
+		if (cdns_is_holdquirk(id, updatetx)) {
266454 			/* wait while fifo is full */
267455 			while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
268456 			       (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
....@@ -282,22 +470,6 @@
282470 				cdns_i2c_writereg(id->recv_count -
283471 						  CDNS_I2C_FIFO_DEPTH,
284472 						  CDNS_I2C_XFER_SIZE_OFFSET);
285
-				id->curr_recv_count = id->recv_count;
286
-			}
287
-		} else if (id->recv_count && !hold_quirk &&
288
-						!id->curr_recv_count) {
289
-
290
-			/* Set the slave address in address register*/
291
-			cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
292
-						CDNS_I2C_ADDR_OFFSET);
293
-
294
-			if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
295
-				cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
296
-						CDNS_I2C_XFER_SIZE_OFFSET);
297
-				id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
298
-			} else {
299
-				cdns_i2c_writereg(id->recv_count,
300
-						CDNS_I2C_XFER_SIZE_OFFSET);
301473 				id->curr_recv_count = id->recv_count;
302474 			}
303475 		}
....@@ -347,7 +519,7 @@
347519 	}
348520 
349521 	/* Update the status for errors */
350
-	id->err_status = isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
522
+	id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
351523 	if (id->err_status)
352524 		status = IRQ_HANDLED;
353525 
....@@ -355,6 +527,27 @@
355527 		complete(&id->xfer_done);
356528 
357529 	return status;
530
+}
531
+
532
+/**
533
+ * cdns_i2c_isr - Interrupt handler for the I2C device
534
+ * @irq:	irq number for the I2C device
535
+ * @ptr:	void pointer to cdns_i2c structure
536
+ *
537
+ * This function passes the control to slave/master based on current role of
538
+ * i2c controller.
539
+ *
540
+ * Return: IRQ_HANDLED always
541
+ */
542
+static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
543
+{
544
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
545
+	struct cdns_i2c *id = ptr;
546
+
547
+	if (id->dev_mode == CDNS_I2C_MODE_SLAVE)
548
+		return cdns_i2c_slave_isr(ptr);
549
+#endif
550
+	return cdns_i2c_master_isr(ptr);
358551 }
359552 
360553 /**
....@@ -373,8 +566,13 @@
373566 	ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
374567 	ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
375568 
569
+	/*
570
+	 * Receive up to I2C_SMBUS_BLOCK_MAX data bytes, plus one message length
571
+	 * byte, plus one checksum byte if PEC is enabled. p_msg->len will be 2 if
572
+	 * PEC is enabled, otherwise 1.
573
+	 */
376574 	if (id->p_msg->flags & I2C_M_RECV_LEN)
377
-		id->recv_count = I2C_SMBUS_BLOCK_MAX + 1;
575
+		id->recv_count = I2C_SMBUS_BLOCK_MAX + id->p_msg->len;
378576 
379577 	id->curr_recv_count = id->recv_count;
380578 
....@@ -500,7 +698,7 @@
500698 	cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
501699 	/* Update the transfercount register to zero */
502700 	cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
503
-	/* Clear the interupt status register */
701
+	/* Clear the interrupt status register */
504702 	regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
505703 	cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
506704 	/* Clear the status register */
....@@ -511,7 +709,7 @@
511709 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
512710 		struct i2c_adapter *adap)
513711 {
514
-	unsigned long time_left;
712
+	unsigned long time_left, msg_timeout;
515713 	u32 reg;
516714 
517715 	id->p_msg = msg;
....@@ -536,8 +734,16 @@
536734 	else
537735 		cdns_i2c_msend(id);
538736 
737
+	/* Minimal time to execute this message */
738
+	msg_timeout = msecs_to_jiffies((1000 * msg->len * BITS_PER_BYTE) / id->i2c_clk);
739
+	/* Plus some wiggle room */
740
+	msg_timeout += msecs_to_jiffies(500);
741
+
742
+	if (msg_timeout < adap->timeout)
743
+		msg_timeout = adap->timeout;
744
+
539745 	/* Wait for the signal of completion */
540
-	time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout);
746
+	time_left = wait_for_completion_timeout(&id->xfer_done, msg_timeout);
541747 	if (time_left == 0) {
542748 		cdns_i2c_master_reset(adap);
543749 		dev_err(id->adap.dev.parent,
....@@ -551,6 +757,9 @@
551757 	/* If it is bus arbitration error, try again */
552758 	if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
553759 		return -EAGAIN;
760
+
761
+	if (msg->flags & I2C_M_RECV_LEN)
762
+		msg->len += min_t(unsigned int, msg->buf[0], I2C_SMBUS_BLOCK_MAX);
554763 
555764 	return 0;
556765 }
....@@ -572,10 +781,28 @@
572781 	u32 reg;
573782 	struct cdns_i2c *id = adap->algo_data;
574783 	bool hold_quirk;
784
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
785
+	bool change_role = false;
786
+#endif
575787 
576
-	ret = pm_runtime_get_sync(id->dev);
788
+	ret = pm_runtime_resume_and_get(id->dev);
577789 	if (ret < 0)
578790 		return ret;
791
+
792
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
793
+	/* Check i2c operating mode and switch if possible */
794
+	if (id->dev_mode == CDNS_I2C_MODE_SLAVE) {
795
+		if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE)
796
+			return -EAGAIN;
797
+
798
+		/* Set mode to master */
799
+		cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
800
+
801
+		/* Mark flag to change role once xfer is completed */
802
+		change_role = true;
803
+	}
804
+#endif
805
+
579806 	/* Check if the bus is free */
580807 	if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) {
581808 		ret = -EAGAIN;
....@@ -634,7 +861,15 @@
634861 	}
635862 
636863 	ret = num;
864
+
637865 out:
866
+
867
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
868
+	/* Switch i2c mode to slave */
869
+	if (change_role)
870
+		cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
871
+#endif
872
+
638873 	pm_runtime_mark_last_busy(id->dev);
639874 	pm_runtime_put_autosuspend(id->dev);
640875 	return ret;
....@@ -648,14 +883,67 @@
648883  */
649884 static u32 cdns_i2c_func(struct i2c_adapter *adap)
650885 {
651
-	return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
652
-		(I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
653
-		I2C_FUNC_SMBUS_BLOCK_DATA;
886
+	u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
887
+			(I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
888
+			I2C_FUNC_SMBUS_BLOCK_DATA;
889
+
890
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
891
+	func |= I2C_FUNC_SLAVE;
892
+#endif
893
+
894
+	return func;
654895 }
896
+
897
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
898
+static int cdns_reg_slave(struct i2c_client *slave)
899
+{
900
+	int ret;
901
+	struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
902
+									adap);
903
+
904
+	if (id->slave)
905
+		return -EBUSY;
906
+
907
+	if (slave->flags & I2C_CLIENT_TEN)
908
+		return -EAFNOSUPPORT;
909
+
910
+	ret = pm_runtime_resume_and_get(id->dev);
911
+	if (ret < 0)
912
+		return ret;
913
+
914
+	/* Store slave information */
915
+	id->slave = slave;
916
+
917
+	/* Enable I2C slave */
918
+	cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
919
+
920
+	return 0;
921
+}
922
+
923
+static int cdns_unreg_slave(struct i2c_client *slave)
924
+{
925
+	struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
926
+									adap);
927
+
928
+	pm_runtime_put(id->dev);
929
+
930
+	/* Remove slave information */
931
+	id->slave = NULL;
932
+
933
+	/* Enable I2C master */
934
+	cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
935
+
936
+	return 0;
937
+}
938
+#endif
655939 
656940 static const struct i2c_algorithm cdns_i2c_algo = {
657941 	.master_xfer	= cdns_i2c_master_xfer,
658942 	.functionality	= cdns_i2c_func,
943
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
944
+	.reg_slave	= cdns_reg_slave,
945
+	.unreg_slave	= cdns_unreg_slave,
946
+#endif
659947 };
660948 
661949 /**
....@@ -750,7 +1038,10 @@
7501038 	ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
7511039 			(div_b << CDNS_I2C_CR_DIVB_SHIFT));
7521040 	cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
753
-
1041
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
1042
+	id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK |
1043
+				 CDNS_I2C_CR_DIVB_MASK);
1044
+#endif
7541045 	return 0;
7551046 }
7561047 
....@@ -901,8 +1192,7 @@
9011192 		id->quirks = data->quirks;
9021193 	}
9031194 
904
-	r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
905
-	id->membase = devm_ioremap_resource(&pdev->dev, r_mem);
1195
+	id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem);
9061196 	if (IS_ERR(id->membase))
9071197 		return PTR_ERR(id->membase);
9081198 
....@@ -924,17 +1214,18 @@
9241214 
9251215 	id->clk = devm_clk_get(&pdev->dev, NULL);
9261216 	if (IS_ERR(id->clk)) {
927
-		dev_err(&pdev->dev, "input clock not found.\n");
1217
+		if (PTR_ERR(id->clk) != -EPROBE_DEFER)
1218
+			dev_err(&pdev->dev, "input clock not found.\n");
9281219 		return PTR_ERR(id->clk);
9291220 	}
9301221 	ret = clk_prepare_enable(id->clk);
9311222 	if (ret)
9321223 		dev_err(&pdev->dev, "Unable to enable clock.\n");
9331224 
934
-	pm_runtime_enable(id->dev);
9351225 	pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT);
9361226 	pm_runtime_use_autosuspend(id->dev);
9371227 	pm_runtime_set_active(id->dev);
1228
+	pm_runtime_enable(id->dev);
9381229 
9391230 	id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
9401231 	if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
....@@ -943,11 +1234,15 @@
9431234 
9441235 	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
9451236 			&id->i2c_clk);
946
-	if (ret || (id->i2c_clk > CDNS_I2C_SPEED_MAX))
947
-		id->i2c_clk = CDNS_I2C_SPEED_DEFAULT;
1237
+	if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ))
1238
+		id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ;
9481239 
949
-	cdns_i2c_writereg(CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS,
950
-			  CDNS_I2C_CR_OFFSET);
1240
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
1241
+	/* Set initial mode to master */
1242
+	id->dev_mode = CDNS_I2C_MODE_MASTER;
1243
+	id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
1244
+#endif
1245
+	cdns_i2c_writereg(CDNS_I2C_CR_MASTER_EN_MASK, CDNS_I2C_CR_OFFSET);
9511246 
9521247 	ret = cdns_i2c_setclk(id->input_clk, id);
9531248 	if (ret) {
....@@ -982,9 +1277,10 @@
9821277 	return 0;
9831278 
9841279 err_clk_dis:
1280
+	clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
9851281 	clk_disable_unprepare(id->clk);
986
-	pm_runtime_set_suspended(&pdev->dev);
9871282 	pm_runtime_disable(&pdev->dev);
1283
+	pm_runtime_set_suspended(&pdev->dev);
9881284 	return ret;
9891285 }
9901286 
....@@ -1000,10 +1296,13 @@
10001296 {
10011297 	struct cdns_i2c *id = platform_get_drvdata(pdev);
10021298 
1299
+	pm_runtime_disable(&pdev->dev);
1300
+	pm_runtime_set_suspended(&pdev->dev);
1301
+	pm_runtime_dont_use_autosuspend(&pdev->dev);
1302
+
10031303 	i2c_del_adapter(&id->adap);
10041304 	clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
10051305 	clk_disable_unprepare(id->clk);
1006
-	pm_runtime_disable(&pdev->dev);
10071306 
10081307 	return 0;
10091308 }