forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/i2c/busses/i2c-bcm-iproc.c
....@@ -17,17 +17,38 @@
1717 #include <linux/io.h>
1818 #include <linux/kernel.h>
1919 #include <linux/module.h>
20
+#include <linux/of_device.h>
2021 #include <linux/platform_device.h>
2122 #include <linux/slab.h>
2223 
24
+#define IDM_CTRL_DIRECT_OFFSET       0x00
2325 #define CFG_OFFSET                   0x00
2426 #define CFG_RESET_SHIFT              31
2527 #define CFG_EN_SHIFT                 30
28
+#define CFG_SLAVE_ADDR_0_SHIFT       28
2629 #define CFG_M_RETRY_CNT_SHIFT        16
2730 #define CFG_M_RETRY_CNT_MASK         0x0f
2831 
2932 #define TIM_CFG_OFFSET               0x04
3033 #define TIM_CFG_MODE_400_SHIFT       31
34
+#define TIM_RAND_SLAVE_STRETCH_SHIFT      24
35
+#define TIM_RAND_SLAVE_STRETCH_MASK       0x7f
36
+#define TIM_PERIODIC_SLAVE_STRETCH_SHIFT  16
37
+#define TIM_PERIODIC_SLAVE_STRETCH_MASK   0x7f
38
+
39
+#define S_CFG_SMBUS_ADDR_OFFSET           0x08
40
+#define S_CFG_EN_NIC_SMB_ADDR3_SHIFT      31
41
+#define S_CFG_NIC_SMB_ADDR3_SHIFT         24
42
+#define S_CFG_NIC_SMB_ADDR3_MASK          0x7f
43
+#define S_CFG_EN_NIC_SMB_ADDR2_SHIFT      23
44
+#define S_CFG_NIC_SMB_ADDR2_SHIFT         16
45
+#define S_CFG_NIC_SMB_ADDR2_MASK          0x7f
46
+#define S_CFG_EN_NIC_SMB_ADDR1_SHIFT      15
47
+#define S_CFG_NIC_SMB_ADDR1_SHIFT         8
48
+#define S_CFG_NIC_SMB_ADDR1_MASK          0x7f
49
+#define S_CFG_EN_NIC_SMB_ADDR0_SHIFT      7
50
+#define S_CFG_NIC_SMB_ADDR0_SHIFT         0
51
+#define S_CFG_NIC_SMB_ADDR0_MASK          0x7f
3152 
3253 #define M_FIFO_CTRL_OFFSET           0x0c
3354 #define M_FIFO_RX_FLUSH_SHIFT        31
....@@ -36,6 +57,14 @@
3657 #define M_FIFO_RX_CNT_MASK           0x7f
3758 #define M_FIFO_RX_THLD_SHIFT         8
3859 #define M_FIFO_RX_THLD_MASK          0x3f
60
+
61
+#define S_FIFO_CTRL_OFFSET           0x10
62
+#define S_FIFO_RX_FLUSH_SHIFT        31
63
+#define S_FIFO_TX_FLUSH_SHIFT        30
64
+#define S_FIFO_RX_CNT_SHIFT          16
65
+#define S_FIFO_RX_CNT_MASK           0x7f
66
+#define S_FIFO_RX_THLD_SHIFT         8
67
+#define S_FIFO_RX_THLD_MASK          0x3f
3968 
4069 #define M_CMD_OFFSET                 0x30
4170 #define M_CMD_START_BUSY_SHIFT       31
....@@ -46,25 +75,48 @@
4675 #define M_CMD_STATUS_NACK_ADDR       0x2
4776 #define M_CMD_STATUS_NACK_DATA       0x3
4877 #define M_CMD_STATUS_TIMEOUT         0x4
78
+#define M_CMD_STATUS_FIFO_UNDERRUN   0x5
79
+#define M_CMD_STATUS_RX_FIFO_FULL    0x6
4980 #define M_CMD_PROTOCOL_SHIFT         9
5081 #define M_CMD_PROTOCOL_MASK          0xf
82
+#define M_CMD_PROTOCOL_QUICK         0x0
5183 #define M_CMD_PROTOCOL_BLK_WR        0x7
5284 #define M_CMD_PROTOCOL_BLK_RD        0x8
85
+#define M_CMD_PROTOCOL_PROCESS       0xa
5386 #define M_CMD_PEC_SHIFT              8
5487 #define M_CMD_RD_CNT_SHIFT           0
5588 #define M_CMD_RD_CNT_MASK            0xff
89
+
90
+#define S_CMD_OFFSET                 0x34
91
+#define S_CMD_START_BUSY_SHIFT       31
92
+#define S_CMD_STATUS_SHIFT           23
93
+#define S_CMD_STATUS_MASK            0x07
94
+#define S_CMD_STATUS_SUCCESS         0x0
95
+#define S_CMD_STATUS_TIMEOUT         0x5
5696 
5797 #define IE_OFFSET                    0x38
5898 #define IE_M_RX_FIFO_FULL_SHIFT      31
5999 #define IE_M_RX_THLD_SHIFT           30
60100 #define IE_M_START_BUSY_SHIFT        28
61101 #define IE_M_TX_UNDERRUN_SHIFT       27
102
+#define IE_S_RX_FIFO_FULL_SHIFT      26
103
+#define IE_S_RX_THLD_SHIFT           25
104
+#define IE_S_RX_EVENT_SHIFT          24
105
+#define IE_S_START_BUSY_SHIFT        23
106
+#define IE_S_TX_UNDERRUN_SHIFT       22
107
+#define IE_S_RD_EVENT_SHIFT          21
62108 
63109 #define IS_OFFSET                    0x3c
64110 #define IS_M_RX_FIFO_FULL_SHIFT      31
65111 #define IS_M_RX_THLD_SHIFT           30
66112 #define IS_M_START_BUSY_SHIFT        28
67113 #define IS_M_TX_UNDERRUN_SHIFT       27
114
+#define IS_S_RX_FIFO_FULL_SHIFT      26
115
+#define IS_S_RX_THLD_SHIFT           25
116
+#define IS_S_RX_EVENT_SHIFT          24
117
+#define IS_S_START_BUSY_SHIFT        23
118
+#define IS_S_TX_UNDERRUN_SHIFT       22
119
+#define IS_S_RD_EVENT_SHIFT          21
68120 
69121 #define M_TX_OFFSET                  0x40
70122 #define M_TX_WR_STATUS_SHIFT         31
....@@ -78,19 +130,70 @@
78130 #define M_RX_DATA_SHIFT              0
79131 #define M_RX_DATA_MASK               0xff
80132 
133
+#define S_TX_OFFSET                  0x48
134
+#define S_TX_WR_STATUS_SHIFT         31
135
+#define S_TX_DATA_SHIFT              0
136
+#define S_TX_DATA_MASK               0xff
137
+
138
+#define S_RX_OFFSET                  0x4c
139
+#define S_RX_STATUS_SHIFT            30
140
+#define S_RX_STATUS_MASK             0x03
141
+#define S_RX_PEC_ERR_SHIFT           29
142
+#define S_RX_DATA_SHIFT              0
143
+#define S_RX_DATA_MASK               0xff
144
+
81145 #define I2C_TIMEOUT_MSEC             50000
82146 #define M_TX_RX_FIFO_SIZE            64
147
+#define M_RX_FIFO_MAX_THLD_VALUE     (M_TX_RX_FIFO_SIZE - 1)
148
+
149
+#define M_RX_MAX_READ_LEN            255
150
+#define M_RX_FIFO_THLD_VALUE         50
151
+
152
+#define IE_M_ALL_INTERRUPT_SHIFT     27
153
+#define IE_M_ALL_INTERRUPT_MASK      0x1e
154
+
155
+#define SLAVE_READ_WRITE_BIT_MASK    0x1
156
+#define SLAVE_READ_WRITE_BIT_SHIFT   0x1
157
+#define SLAVE_MAX_SIZE_TRANSACTION   64
158
+#define SLAVE_CLOCK_STRETCH_TIME     25
159
+
160
+#define IE_S_ALL_INTERRUPT_SHIFT     21
161
+#define IE_S_ALL_INTERRUPT_MASK      0x3f
162
+/*
163
+ * It takes ~18us to reading 10bytes of data, hence to keep tasklet
164
+ * running for less time, max slave read per tasklet is set to 10 bytes.
165
+ */
166
+#define MAX_SLAVE_RX_PER_INT         10
167
+
168
+enum i2c_slave_read_status {
169
+	I2C_SLAVE_RX_FIFO_EMPTY = 0,
170
+	I2C_SLAVE_RX_START,
171
+	I2C_SLAVE_RX_DATA,
172
+	I2C_SLAVE_RX_END,
173
+};
83174 
84175 enum bus_speed_index {
85176 	I2C_SPD_100K = 0,
86177 	I2C_SPD_400K,
87178 };
88179 
180
+enum bcm_iproc_i2c_type {
181
+	IPROC_I2C,
182
+	IPROC_I2C_NIC
183
+};
184
+
89185 struct bcm_iproc_i2c_dev {
90186 	struct device *device;
187
+	enum bcm_iproc_i2c_type type;
91188 	int irq;
92189 
93190 	void __iomem *base;
191
+	void __iomem *idm_base;
192
+
193
+	u32 ape_addr_mask;
194
+
195
+	/* lock for indirect access through IDM */
196
+	spinlock_t idm_lock;
94197 
95198 	struct i2c_adapter adapter;
96199 	unsigned int bus_speed;
....@@ -100,68 +203,452 @@
100203 
101204 	struct i2c_msg *msg;
102205 
206
+	struct i2c_client *slave;
207
+
103208 	/* bytes that have been transferred */
104209 	unsigned int tx_bytes;
210
+	/* bytes that have been read */
211
+	unsigned int rx_bytes;
212
+	unsigned int thld_bytes;
213
+
214
+	bool slave_rx_only;
215
+	bool rx_start_rcvd;
216
+	bool slave_read_complete;
217
+	u32 tx_underrun;
218
+	u32 slave_int_mask;
219
+	struct tasklet_struct slave_rx_tasklet;
105220 };
221
+
222
+/* tasklet to process slave rx data */
223
+static void slave_rx_tasklet_fn(unsigned long);
106224 
107225 /*
108226  * Can be expanded in the future if more interrupt status bits are utilized
109227  */
110
-#define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT))
228
+#define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
229
+		| BIT(IS_M_RX_THLD_SHIFT))
230
+
231
+#define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
232
+		| BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
233
+		| BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\
234
+		| BIT(IS_S_RX_THLD_SHIFT))
235
+
236
+static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
237
+static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
238
+static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
239
+					 bool enable);
240
+
241
+static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
242
+				   u32 offset)
243
+{
244
+	u32 val;
245
+
246
+	if (iproc_i2c->idm_base) {
247
+		spin_lock(&iproc_i2c->idm_lock);
248
+		writel(iproc_i2c->ape_addr_mask,
249
+		       iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
250
+		val = readl(iproc_i2c->base + offset);
251
+		spin_unlock(&iproc_i2c->idm_lock);
252
+	} else {
253
+		val = readl(iproc_i2c->base + offset);
254
+	}
255
+
256
+	return val;
257
+}
258
+
259
+static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
260
+				    u32 offset, u32 val)
261
+{
262
+	if (iproc_i2c->idm_base) {
263
+		spin_lock(&iproc_i2c->idm_lock);
264
+		writel(iproc_i2c->ape_addr_mask,
265
+		       iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
266
+		writel(val, iproc_i2c->base + offset);
267
+		spin_unlock(&iproc_i2c->idm_lock);
268
+	} else {
269
+		writel(val, iproc_i2c->base + offset);
270
+	}
271
+}
272
+
273
+static void bcm_iproc_i2c_slave_init(
274
+	struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
275
+{
276
+	u32 val;
277
+
278
+	iproc_i2c->tx_underrun = 0;
279
+	if (need_reset) {
280
+		/* put controller in reset */
281
+		val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
282
+		val |= BIT(CFG_RESET_SHIFT);
283
+		iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
284
+
285
+		/* wait 100 usec per spec */
286
+		udelay(100);
287
+
288
+		/* bring controller out of reset */
289
+		val &= ~(BIT(CFG_RESET_SHIFT));
290
+		iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
291
+	}
292
+
293
+	/* flush TX/RX FIFOs */
294
+	val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
295
+	iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
296
+
297
+	/* Maximum slave stretch time */
298
+	val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
299
+	val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
300
+	val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
301
+	iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
302
+
303
+	/* Configure the slave address */
304
+	val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
305
+	val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
306
+	val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
307
+	val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
308
+	iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
309
+
310
+	/* clear all pending slave interrupts */
311
+	iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
312
+
313
+	/* Enable interrupt register to indicate a valid byte in receive fifo */
314
+	val = BIT(IE_S_RX_EVENT_SHIFT);
315
+	/* Enable interrupt register to indicate a Master read transaction */
316
+	val |= BIT(IE_S_RD_EVENT_SHIFT);
317
+	/* Enable interrupt register for the Slave BUSY command */
318
+	val |= BIT(IE_S_START_BUSY_SHIFT);
319
+	iproc_i2c->slave_int_mask = val;
320
+	iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
321
+}
322
+
323
+static void bcm_iproc_i2c_check_slave_status(
324
+	struct bcm_iproc_i2c_dev *iproc_i2c)
325
+{
326
+	u32 val;
327
+
328
+	val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
329
+	/* status is valid only when START_BUSY is cleared after it was set */
330
+	if (val & BIT(S_CMD_START_BUSY_SHIFT))
331
+		return;
332
+
333
+	val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
334
+	if (val == S_CMD_STATUS_TIMEOUT) {
335
+		dev_err(iproc_i2c->device, "slave random stretch time timeout\n");
336
+
337
+		/* re-initialize i2c for recovery */
338
+		bcm_iproc_i2c_enable_disable(iproc_i2c, false);
339
+		bcm_iproc_i2c_slave_init(iproc_i2c, true);
340
+		bcm_iproc_i2c_enable_disable(iproc_i2c, true);
341
+	}
342
+}
343
+
344
+static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c)
345
+{
346
+	u8 rx_data, rx_status;
347
+	u32 rx_bytes = 0;
348
+	u32 val;
349
+
350
+	while (rx_bytes < MAX_SLAVE_RX_PER_INT) {
351
+		val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
352
+		rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
353
+		rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
354
+
355
+		if (rx_status == I2C_SLAVE_RX_START) {
356
+			/* Start of SMBUS Master write */
357
+			i2c_slave_event(iproc_i2c->slave,
358
+					I2C_SLAVE_WRITE_REQUESTED, &rx_data);
359
+			iproc_i2c->rx_start_rcvd = true;
360
+			iproc_i2c->slave_read_complete = false;
361
+		} else if (rx_status == I2C_SLAVE_RX_DATA &&
362
+			   iproc_i2c->rx_start_rcvd) {
363
+			/* Middle of SMBUS Master write */
364
+			i2c_slave_event(iproc_i2c->slave,
365
+					I2C_SLAVE_WRITE_RECEIVED, &rx_data);
366
+		} else if (rx_status == I2C_SLAVE_RX_END &&
367
+			   iproc_i2c->rx_start_rcvd) {
368
+			/* End of SMBUS Master write */
369
+			if (iproc_i2c->slave_rx_only)
370
+				i2c_slave_event(iproc_i2c->slave,
371
+						I2C_SLAVE_WRITE_RECEIVED,
372
+						&rx_data);
373
+
374
+			i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
375
+					&rx_data);
376
+		} else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
377
+			iproc_i2c->rx_start_rcvd = false;
378
+			iproc_i2c->slave_read_complete = true;
379
+			break;
380
+		}
381
+
382
+		rx_bytes++;
383
+	}
384
+}
385
+
386
+static void slave_rx_tasklet_fn(unsigned long data)
387
+{
388
+	struct bcm_iproc_i2c_dev *iproc_i2c = (struct bcm_iproc_i2c_dev *)data;
389
+	u32 int_clr;
390
+
391
+	bcm_iproc_i2c_slave_read(iproc_i2c);
392
+
393
+	/* clear pending IS_S_RX_EVENT_SHIFT interrupt */
394
+	int_clr = BIT(IS_S_RX_EVENT_SHIFT);
395
+
396
+	if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) {
397
+		/*
398
+		 * In case of single byte master-read request,
399
+		 * IS_S_TX_UNDERRUN_SHIFT event is generated before
400
+		 * IS_S_START_BUSY_SHIFT event. Hence start slave data send
401
+		 * from first IS_S_TX_UNDERRUN_SHIFT event.
402
+		 *
403
+		 * This means don't send any data from slave when
404
+		 * IS_S_RD_EVENT_SHIFT event is generated else it will increment
405
+		 * eeprom or other backend slave driver read pointer twice.
406
+		 */
407
+		iproc_i2c->tx_underrun = 0;
408
+		iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);
409
+
410
+		/* clear IS_S_RD_EVENT_SHIFT interrupt */
411
+		int_clr |= BIT(IS_S_RD_EVENT_SHIFT);
412
+	}
413
+
414
+	/* clear slave interrupt */
415
+	iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, int_clr);
416
+	/* enable slave interrupts */
417
+	iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, iproc_i2c->slave_int_mask);
418
+}
419
+
420
+static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
421
+				    u32 status)
422
+{
423
+	u32 val;
424
+	u8 value;
425
+
426
+	/*
427
+	 * Slave events in case of master-write, master-write-read and,
428
+	 * master-read
429
+	 *
430
+	 * Master-write     : only IS_S_RX_EVENT_SHIFT event
431
+	 * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
432
+	 *                    events
433
+	 * Master-read      : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
434
+	 *                    events or only IS_S_RD_EVENT_SHIFT
435
+	 */
436
+	if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
437
+	    status & BIT(IS_S_RD_EVENT_SHIFT)) {
438
+		/* disable slave interrupts */
439
+		val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
440
+		val &= ~iproc_i2c->slave_int_mask;
441
+		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
442
+
443
+		if (status & BIT(IS_S_RD_EVENT_SHIFT))
444
+			/* Master-write-read request */
445
+			iproc_i2c->slave_rx_only = false;
446
+		else
447
+			/* Master-write request only */
448
+			iproc_i2c->slave_rx_only = true;
449
+
450
+		/* schedule tasklet to read data later */
451
+		tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
452
+
453
+		/* clear only IS_S_RX_EVENT_SHIFT interrupt */
454
+		iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
455
+				 BIT(IS_S_RX_EVENT_SHIFT));
456
+	}
457
+
458
+	if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
459
+		iproc_i2c->tx_underrun++;
460
+		if (iproc_i2c->tx_underrun == 1)
461
+			/* Start of SMBUS for Master Read */
462
+			i2c_slave_event(iproc_i2c->slave,
463
+					I2C_SLAVE_READ_REQUESTED,
464
+					&value);
465
+		else
466
+			/* Master read other than start */
467
+			i2c_slave_event(iproc_i2c->slave,
468
+					I2C_SLAVE_READ_PROCESSED,
469
+					&value);
470
+
471
+		iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
472
+		/* start transfer */
473
+		val = BIT(S_CMD_START_BUSY_SHIFT);
474
+		iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
475
+
476
+		/* clear interrupt */
477
+		iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
478
+				 BIT(IS_S_TX_UNDERRUN_SHIFT));
479
+	}
480
+
481
+	/* Stop received from master in case of master read transaction */
482
+	if (status & BIT(IS_S_START_BUSY_SHIFT)) {
483
+		/*
484
+		 * Enable interrupt for TX FIFO becomes empty and
485
+		 * less than PKT_LENGTH bytes were output on the SMBUS
486
+		 */
487
+		iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
488
+		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
489
+				 iproc_i2c->slave_int_mask);
490
+
491
+		/* End of SMBUS for Master Read */
492
+		val = BIT(S_TX_WR_STATUS_SHIFT);
493
+		iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val);
494
+
495
+		val = BIT(S_CMD_START_BUSY_SHIFT);
496
+		iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
497
+
498
+		/* flush TX FIFOs */
499
+		val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET);
500
+		val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
501
+		iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
502
+
503
+		i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
504
+
505
+		/* clear interrupt */
506
+		iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
507
+				 BIT(IS_S_START_BUSY_SHIFT));
508
+	}
509
+
510
+	/* check slave transmit status only if slave is transmitting */
511
+	if (!iproc_i2c->slave_rx_only)
512
+		bcm_iproc_i2c_check_slave_status(iproc_i2c);
513
+
514
+	return true;
515
+}
516
+
517
+static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
518
+{
519
+	struct i2c_msg *msg = iproc_i2c->msg;
520
+	uint32_t val;
521
+
522
+	/* Read valid data from RX FIFO */
523
+	while (iproc_i2c->rx_bytes < msg->len) {
524
+		val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
525
+
526
+		/* rx fifo empty */
527
+		if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
528
+			break;
529
+
530
+		msg->buf[iproc_i2c->rx_bytes] =
531
+			(val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
532
+		iproc_i2c->rx_bytes++;
533
+	}
534
+}
535
+
536
+static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
537
+{
538
+	struct i2c_msg *msg = iproc_i2c->msg;
539
+	unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
540
+	unsigned int i;
541
+	u32 val;
542
+
543
+	/* can only fill up to the FIFO size */
544
+	tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
545
+	for (i = 0; i < tx_bytes; i++) {
546
+		/* start from where we left over */
547
+		unsigned int idx = iproc_i2c->tx_bytes + i;
548
+
549
+		val = msg->buf[idx];
550
+
551
+		/* mark the last byte */
552
+		if (idx == msg->len - 1) {
553
+			val |= BIT(M_TX_WR_STATUS_SHIFT);
554
+
555
+			if (iproc_i2c->irq) {
556
+				u32 tmp;
557
+
558
+				/*
559
+				 * Since this is the last byte, we should now
560
+				 * disable TX FIFO underrun interrupt
561
+				 */
562
+				tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
563
+				tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
564
+				iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
565
+						 tmp);
566
+			}
567
+		}
568
+
569
+		/* load data into TX FIFO */
570
+		iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
571
+	}
572
+
573
+	/* update number of transferred bytes */
574
+	iproc_i2c->tx_bytes += tx_bytes;
575
+}
576
+
577
+static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
578
+{
579
+	struct i2c_msg *msg = iproc_i2c->msg;
580
+	u32 bytes_left, val;
581
+
582
+	bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
583
+	bytes_left = msg->len - iproc_i2c->rx_bytes;
584
+	if (bytes_left == 0) {
585
+		if (iproc_i2c->irq) {
586
+			/* finished reading all data, disable rx thld event */
587
+			val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
588
+			val &= ~BIT(IS_M_RX_THLD_SHIFT);
589
+			iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
590
+		}
591
+	} else if (bytes_left < iproc_i2c->thld_bytes) {
592
+		/* set bytes left as threshold */
593
+		val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
594
+		val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
595
+		val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
596
+		iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
597
+		iproc_i2c->thld_bytes = bytes_left;
598
+	}
599
+	/*
600
+	 * bytes_left >= iproc_i2c->thld_bytes,
601
+	 * hence no need to change the THRESHOLD SET.
602
+	 * It will remain as iproc_i2c->thld_bytes itself
603
+	 */
604
+}
605
+
606
+static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
607
+					  u32 status)
608
+{
609
+	/* TX FIFO is empty and we have more data to send */
610
+	if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
611
+		bcm_iproc_i2c_send(iproc_i2c);
612
+
613
+	/* RX FIFO threshold is reached and data needs to be read out */
614
+	if (status & BIT(IS_M_RX_THLD_SHIFT))
615
+		bcm_iproc_i2c_read(iproc_i2c);
616
+
617
+	/* transfer is done */
618
+	if (status & BIT(IS_M_START_BUSY_SHIFT)) {
619
+		iproc_i2c->xfer_is_done = 1;
620
+		if (iproc_i2c->irq)
621
+			complete(&iproc_i2c->done);
622
+	}
623
+}
111624 
112625 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
113626 {
114627 	struct bcm_iproc_i2c_dev *iproc_i2c = data;
115
-	u32 status = readl(iproc_i2c->base + IS_OFFSET);
628
+	u32 slave_status;
629
+	u32 status;
630
+	bool ret;
631
+
632
+	status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
633
+	/* process only slave interrupt which are enabled */
634
+	slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &
635
+		       ISR_MASK_SLAVE;
636
+
637
+	if (slave_status) {
638
+		ret = bcm_iproc_i2c_slave_isr(iproc_i2c, slave_status);
639
+		if (ret)
640
+			return IRQ_HANDLED;
641
+		else
642
+			return IRQ_NONE;
643
+	}
116644 
117645 	status &= ISR_MASK;
118
-
119646 	if (!status)
120647 		return IRQ_NONE;
121648 
122
-	/* TX FIFO is empty and we have more data to send */
123
-	if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) {
124
-		struct i2c_msg *msg = iproc_i2c->msg;
125
-		unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
126
-		unsigned int i;
127
-		u32 val;
128
-
129
-		/* can only fill up to the FIFO size */
130
-		tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
131
-		for (i = 0; i < tx_bytes; i++) {
132
-			/* start from where we left over */
133
-			unsigned int idx = iproc_i2c->tx_bytes + i;
134
-
135
-			val = msg->buf[idx];
136
-
137
-			/* mark the last byte */
138
-			if (idx == msg->len - 1) {
139
-				u32 tmp;
140
-
141
-				val |= BIT(M_TX_WR_STATUS_SHIFT);
142
-
143
-				/*
144
-				 * Since this is the last byte, we should
145
-				 * now disable TX FIFO underrun interrupt
146
-				 */
147
-				tmp = readl(iproc_i2c->base + IE_OFFSET);
148
-				tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
149
-				writel(tmp, iproc_i2c->base + IE_OFFSET);
150
-			}
151
-
152
-			/* load data into TX FIFO */
153
-			writel(val, iproc_i2c->base + M_TX_OFFSET);
154
-		}
155
-		/* update number of transferred bytes */
156
-		iproc_i2c->tx_bytes += tx_bytes;
157
-	}
158
-
159
-	if (status & BIT(IS_M_START_BUSY_SHIFT)) {
160
-		iproc_i2c->xfer_is_done = 1;
161
-		complete(&iproc_i2c->done);
162
-	}
163
-
164
-	writel(status, iproc_i2c->base + IS_OFFSET);
649
+	/* process all master based events */
650
+	bcm_iproc_i2c_process_m_event(iproc_i2c, status);
651
+	iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
165652 
166653 	return IRQ_HANDLED;
167654 }
....@@ -171,26 +658,29 @@
171658 	u32 val;
172659 
173660 	/* put controller in reset */
174
-	val = readl(iproc_i2c->base + CFG_OFFSET);
175
-	val |= 1 << CFG_RESET_SHIFT;
176
-	val &= ~(1 << CFG_EN_SHIFT);
177
-	writel(val, iproc_i2c->base + CFG_OFFSET);
661
+	val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
662
+	val |= BIT(CFG_RESET_SHIFT);
663
+	val &= ~(BIT(CFG_EN_SHIFT));
664
+	iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
178665 
179666 	/* wait 100 usec per spec */
180667 	udelay(100);
181668 
182669 	/* bring controller out of reset */
183
-	val &= ~(1 << CFG_RESET_SHIFT);
184
-	writel(val, iproc_i2c->base + CFG_OFFSET);
670
+	val &= ~(BIT(CFG_RESET_SHIFT));
671
+	iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
185672 
186673 	/* flush TX/RX FIFOs and set RX FIFO threshold to zero */
187
-	val = (1 << M_FIFO_RX_FLUSH_SHIFT) | (1 << M_FIFO_TX_FLUSH_SHIFT);
188
-	writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
674
+	val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
675
+	iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
189676 	/* disable all interrupts */
190
-	writel(0, iproc_i2c->base + IE_OFFSET);
677
+	val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
678
+	val &= ~(IE_M_ALL_INTERRUPT_MASK <<
679
+			IE_M_ALL_INTERRUPT_SHIFT);
680
+	iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
191681 
192682 	/* clear all pending interrupts */
193
-	writel(0xffffffff, iproc_i2c->base + IS_OFFSET);
683
+	iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
194684 
195685 	return 0;
196686 }
....@@ -200,12 +690,12 @@
200690 {
201691 	u32 val;
202692 
203
-	val = readl(iproc_i2c->base + CFG_OFFSET);
693
+	val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
204694 	if (enable)
205695 		val |= BIT(CFG_EN_SHIFT);
206696 	else
207697 		val &= ~BIT(CFG_EN_SHIFT);
208
-	writel(val, iproc_i2c->base + CFG_OFFSET);
698
+	iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
209699 }
210700 
211701 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
....@@ -213,7 +703,7 @@
213703 {
214704 	u32 val;
215705 
216
-	val = readl(iproc_i2c->base + M_CMD_OFFSET);
706
+	val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
217707 	val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
218708 
219709 	switch (val) {
....@@ -236,6 +726,14 @@
236726 		dev_dbg(iproc_i2c->device, "bus timeout\n");
237727 		return -ETIMEDOUT;
238728 
729
+	case M_CMD_STATUS_FIFO_UNDERRUN:
730
+		dev_dbg(iproc_i2c->device, "FIFO under-run\n");
731
+		return -ENXIO;
732
+
733
+	case M_CMD_STATUS_RX_FIFO_FULL:
734
+		dev_dbg(iproc_i2c->device, "RX FIFO full\n");
735
+		return -ETIMEDOUT;
736
+
239737 	default:
240738 		dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
241739 
....@@ -248,18 +746,83 @@
248746 	}
249747 }
250748 
251
-static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
252
-					 struct i2c_msg *msg)
749
+static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
750
+				   struct i2c_msg *msg,
751
+				   u32 cmd)
253752 {
254
-	int ret, i;
255
-	u8 addr;
256
-	u32 val;
257
-	unsigned int tx_bytes;
258753 	unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
754
+	u32 val, status;
755
+	int ret;
756
+
757
+	iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
758
+
759
+	if (iproc_i2c->irq) {
760
+		time_left = wait_for_completion_timeout(&iproc_i2c->done,
761
+							time_left);
762
+		/* disable all interrupts */
763
+		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
764
+		/* read it back to flush the write */
765
+		iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
766
+		/* make sure the interrupt handler isn't running */
767
+		synchronize_irq(iproc_i2c->irq);
768
+
769
+	} else { /* polling mode */
770
+		unsigned long timeout = jiffies + time_left;
771
+
772
+		do {
773
+			status = iproc_i2c_rd_reg(iproc_i2c,
774
+						  IS_OFFSET) & ISR_MASK;
775
+			bcm_iproc_i2c_process_m_event(iproc_i2c, status);
776
+			iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
777
+
778
+			if (time_after(jiffies, timeout)) {
779
+				time_left = 0;
780
+				break;
781
+			}
782
+
783
+			cpu_relax();
784
+			cond_resched();
785
+		} while (!iproc_i2c->xfer_is_done);
786
+	}
787
+
788
+	if (!time_left && !iproc_i2c->xfer_is_done) {
789
+		dev_err(iproc_i2c->device, "transaction timed out\n");
790
+
791
+		/* flush both TX/RX FIFOs */
792
+		val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
793
+		iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
794
+		return -ETIMEDOUT;
795
+	}
796
+
797
+	ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
798
+	if (ret) {
799
+		/* flush both TX/RX FIFOs */
800
+		val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
801
+		iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
802
+		return ret;
803
+	}
804
+
805
+	return 0;
806
+}
807
+
808
+/*
809
+ * If 'process_call' is true, then this is a multi-msg transfer that requires
810
+ * a repeated start between the messages.
811
+ * More specifically, it must be a write (reg) followed by a read (data).
812
+ * The i2c quirks are set to enforce this rule.
813
+ */
814
+static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c,
815
+					struct i2c_msg *msgs, bool process_call)
816
+{
817
+	int i;
818
+	u8 addr;
819
+	u32 val, tmp, val_intr_en;
820
+	unsigned int tx_bytes;
821
+	struct i2c_msg *msg = &msgs[0];
259822 
260823 	/* check if bus is busy */
261
-	if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) &
262
-	       BIT(M_CMD_START_BUSY_SHIFT))) {
824
+	if (!!(iproc_i2c_rd_reg(iproc_i2c,
825
+				M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
263826 		dev_warn(iproc_i2c->device, "bus is busy\n");
264827 		return -EBUSY;
265828 	}
....@@ -268,7 +831,7 @@
268831 
269832 	/* format and load slave address into the TX FIFO */
270833 	addr = i2c_8bit_addr_from_msg(msg);
271
-	writel(addr, iproc_i2c->base + M_TX_OFFSET);
834
+	iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
272835 
273836 	/*
274837 	 * For a write transaction, load data into the TX FIFO. Only allow
....@@ -281,16 +844,33 @@
281844 			val = msg->buf[i];
282845 
283846 			/* mark the last byte */
284
-			if (i == msg->len - 1)
285
-				val |= 1 << M_TX_WR_STATUS_SHIFT;
847
+			if (!process_call && (i == msg->len - 1))
848
+				val |= BIT(M_TX_WR_STATUS_SHIFT);
286849 
287
-			writel(val, iproc_i2c->base + M_TX_OFFSET);
850
+			iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
288851 		}
289852 		iproc_i2c->tx_bytes = tx_bytes;
290853 	}
291854 
855
+	/* Process the read message if this is process call */
856
+	if (process_call) {
857
+		msg++;
858
+		iproc_i2c->msg = msg;  /* point to second msg */
859
+
860
+		/*
861
+		 * The last byte to be sent out should be a slave
862
+		 * address with read operation
863
+		 */
864
+		addr = i2c_8bit_addr_from_msg(msg);
865
+		/* mark it the last byte out */
866
+		val = addr | BIT(M_TX_WR_STATUS_SHIFT);
867
+		iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
868
+	}
869
+
292870 	/* mark as incomplete before starting the transaction */
293
-	reinit_completion(&iproc_i2c->done);
871
+	if (iproc_i2c->irq)
872
+		reinit_completion(&iproc_i2c->done);
873
+
294874 	iproc_i2c->xfer_is_done = 0;
295875 
296876 	/*
....@@ -298,88 +878,79 @@
298878 	 * transaction is done, i.e., the internal start_busy bit, transitions
299879 	 * from 1 to 0.
300880 	 */
301
-	val = BIT(IE_M_START_BUSY_SHIFT);
881
+	val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
302882 
303883 	/*
304884 	 * If TX data size is larger than the TX FIFO, need to enable TX
305885 	 * underrun interrupt, which will be triggerred when the TX FIFO is
306886 	 * empty. When that happens we can then pump more data into the FIFO
307887 	 */
308
-	if (!(msg->flags & I2C_M_RD) &&
888
+	if (!process_call && !(msg->flags & I2C_M_RD) &&
309889 	    msg->len > iproc_i2c->tx_bytes)
310
-		val |= BIT(IE_M_TX_UNDERRUN_SHIFT);
311
-
312
-	writel(val, iproc_i2c->base + IE_OFFSET);
890
+		val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
313891 
314892 	/*
315893 	 * Now we can activate the transfer. For a read operation, specify the
316894 	 * number of bytes to read
317895 	 */
318896 	val = BIT(M_CMD_START_BUSY_SHIFT);
319
-	if (msg->flags & I2C_M_RD) {
320
-		val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) |
897
+
898
+	if (msg->len == 0) {
899
+		/* SMBUS QUICK Command (Read/Write) */
900
+		val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
901
+	} else if (msg->flags & I2C_M_RD) {
902
+		u32 protocol;
903
+
904
+		iproc_i2c->rx_bytes = 0;
905
+		if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
906
+			iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
907
+		else
908
+			iproc_i2c->thld_bytes = msg->len;
909
+
910
+		/* set threshold value */
911
+		tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
912
+		tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
913
+		tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
914
+		iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
915
+
916
+		/* enable the RX threshold interrupt */
917
+		val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
918
+
919
+		protocol = process_call ?
920
+				M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD;
921
+
922
+		val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
321923 		       (msg->len << M_CMD_RD_CNT_SHIFT);
322924 	} else {
323925 		val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
324926 	}
325
-	writel(val, iproc_i2c->base + M_CMD_OFFSET);
326927 
327
-	time_left = wait_for_completion_timeout(&iproc_i2c->done, time_left);
928
+	if (iproc_i2c->irq)
929
+		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
328930 
329
-	/* disable all interrupts */
330
-	writel(0, iproc_i2c->base + IE_OFFSET);
331
-	/* read it back to flush the write */
332
-	readl(iproc_i2c->base + IE_OFFSET);
333
-
334
-	/* make sure the interrupt handler isn't running */
335
-	synchronize_irq(iproc_i2c->irq);
336
-
337
-	if (!time_left && !iproc_i2c->xfer_is_done) {
338
-		dev_err(iproc_i2c->device, "transaction timed out\n");
339
-
340
-		/* flush FIFOs */
341
-		val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
342
-		      (1 << M_FIFO_TX_FLUSH_SHIFT);
343
-		writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
344
-		return -ETIMEDOUT;
345
-	}
346
-
347
-	ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
348
-	if (ret) {
349
-		/* flush both TX/RX FIFOs */
350
-		val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
351
-		      (1 << M_FIFO_TX_FLUSH_SHIFT);
352
-		writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
353
-		return ret;
354
-	}
355
-
356
-	/*
357
-	 * For a read operation, we now need to load the data from FIFO
358
-	 * into the memory buffer
359
-	 */
360
-	if (msg->flags & I2C_M_RD) {
361
-		for (i = 0; i < msg->len; i++) {
362
-			msg->buf[i] = (readl(iproc_i2c->base + M_RX_OFFSET) >>
363
-				      M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
364
-		}
365
-	}
366
-
367
-	return 0;
931
+	return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
368932 }
369933 
370934 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
371935 			      struct i2c_msg msgs[], int num)
372936 {
373937 	struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
374
-	int ret, i;
938
+	bool process_call = false;
939
+	int ret;
375940 
376
-	/* go through all messages */
377
-	for (i = 0; i < num; i++) {
378
-		ret = bcm_iproc_i2c_xfer_single_msg(iproc_i2c, &msgs[i]);
379
-		if (ret) {
380
-			dev_dbg(iproc_i2c->device, "xfer failed\n");
381
-			return ret;
941
+	if (num == 2) {
942
+		/* Repeated start, use process call */
943
+		process_call = true;
944
+		if (msgs[1].flags & I2C_M_NOSTART) {
945
+			dev_err(iproc_i2c->device, "Invalid repeated start\n");
946
+			return -EOPNOTSUPP;
382947 		}
948
+	}
949
+
950
+	ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call);
951
+	if (ret) {
952
+		dev_dbg(iproc_i2c->device, "xfer failed\n");
953
+		return ret;
383954 	}
384955 
385956 	return num;
....@@ -387,17 +958,27 @@
387958 
388959 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
389960 {
390
-	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
961
+	u32 val;
962
+
963
+	val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
964
+
965
+	if (adap->algo->reg_slave)
966
+		val |= I2C_FUNC_SLAVE;
967
+
968
+	return val;
391969 }
392970 
393
-static const struct i2c_algorithm bcm_iproc_algo = {
971
+static struct i2c_algorithm bcm_iproc_algo = {
394972 	.master_xfer = bcm_iproc_i2c_xfer,
395973 	.functionality = bcm_iproc_i2c_functionality,
974
+	.reg_slave = bcm_iproc_i2c_reg_slave,
975
+	.unreg_slave = bcm_iproc_i2c_unreg_slave,
396976 };
397977 
398978 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
399
-	/* need to reserve one byte in the FIFO for the slave address */
400
-	.max_read_len = M_TX_RX_FIFO_SIZE - 1,
979
+	.flags = I2C_AQ_COMB_WRITE_THEN_READ,
980
+	.max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE,
981
+	.max_read_len = M_RX_MAX_READ_LEN,
401982 };
402983 
403984 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
....@@ -409,26 +990,26 @@
409990 	if (ret < 0) {
410991 		dev_info(iproc_i2c->device,
411992 			"unable to interpret clock-frequency DT property\n");
412
-		bus_speed = 100000;
993
+		bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
413994 	}
414995 
415
-	if (bus_speed < 100000) {
996
+	if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) {
416997 		dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
417998 			bus_speed);
418999 		dev_err(iproc_i2c->device,
4191000 			"valid speeds are 100khz and 400khz\n");
4201001 		return -EINVAL;
421
-	} else if (bus_speed < 400000) {
422
-		bus_speed = 100000;
1002
+	} else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) {
1003
+		bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
4231004 	} else {
424
-		bus_speed = 400000;
1005
+		bus_speed = I2C_MAX_FAST_MODE_FREQ;
4251006 	}
4261007 
4271008 	iproc_i2c->bus_speed = bus_speed;
428
-	val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
429
-	val &= ~(1 << TIM_CFG_MODE_400_SHIFT);
430
-	val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
431
-	writel(val, iproc_i2c->base + TIM_CFG_OFFSET);
1009
+	val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1010
+	val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1011
+	val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1012
+	iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
4321013 
4331014 	dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
4341015 
....@@ -449,12 +1030,37 @@
4491030 
4501031 	platform_set_drvdata(pdev, iproc_i2c);
4511032 	iproc_i2c->device = &pdev->dev;
1033
+	iproc_i2c->type =
1034
+		(enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
4521035 	init_completion(&iproc_i2c->done);
4531036 
4541037 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4551038 	iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
4561039 	if (IS_ERR(iproc_i2c->base))
4571040 		return PTR_ERR(iproc_i2c->base);
1041
+
1042
+	if (iproc_i2c->type == IPROC_I2C_NIC) {
1043
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1044
+		iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
1045
+							    res);
1046
+		if (IS_ERR(iproc_i2c->idm_base))
1047
+			return PTR_ERR(iproc_i2c->idm_base);
1048
+
1049
+		ret = of_property_read_u32(iproc_i2c->device->of_node,
1050
+					   "brcm,ape-hsls-addr-mask",
1051
+					   &iproc_i2c->ape_addr_mask);
1052
+		if (ret < 0) {
1053
+			dev_err(iproc_i2c->device,
1054
+				"'brcm,ape-hsls-addr-mask' missing\n");
1055
+			return -EINVAL;
1056
+		}
1057
+
1058
+		spin_lock_init(&iproc_i2c->idm_lock);
1059
+
1060
+		/* no slave support */
1061
+		bcm_iproc_algo.reg_slave = NULL;
1062
+		bcm_iproc_algo.unreg_slave = NULL;
1063
+	}
4581064 
4591065 	ret = bcm_iproc_i2c_init(iproc_i2c);
4601066 	if (ret)
....@@ -465,24 +1071,29 @@
4651071 		return ret;
4661072 
4671073 	irq = platform_get_irq(pdev, 0);
468
-	if (irq <= 0) {
469
-		dev_err(iproc_i2c->device, "no irq resource\n");
470
-		return irq;
471
-	}
472
-	iproc_i2c->irq = irq;
1074
+	if (irq > 0) {
1075
+		ret = devm_request_irq(iproc_i2c->device, irq,
1076
+				       bcm_iproc_i2c_isr, 0, pdev->name,
1077
+				       iproc_i2c);
1078
+		if (ret < 0) {
1079
+			dev_err(iproc_i2c->device,
1080
+				"unable to request irq %i\n", irq);
1081
+			return ret;
1082
+		}
4731083 
474
-	ret = devm_request_irq(iproc_i2c->device, irq, bcm_iproc_i2c_isr, 0,
475
-			       pdev->name, iproc_i2c);
476
-	if (ret < 0) {
477
-		dev_err(iproc_i2c->device, "unable to request irq %i\n", irq);
478
-		return ret;
1084
+		iproc_i2c->irq = irq;
1085
+	} else {
1086
+		dev_warn(iproc_i2c->device,
1087
+			 "no irq resource, falling back to poll mode\n");
4791088 	}
4801089 
4811090 	bcm_iproc_i2c_enable_disable(iproc_i2c, true);
4821091 
4831092 	adap = &iproc_i2c->adapter;
4841093 	i2c_set_adapdata(adap, iproc_i2c);
485
-	strlcpy(adap->name, "Broadcom iProc I2C adapter", sizeof(adap->name));
1094
+	snprintf(adap->name, sizeof(adap->name),
1095
+		"Broadcom iProc (%s)",
1096
+		of_node_full_name(iproc_i2c->device->of_node));
4861097 	adap->algo = &bcm_iproc_algo;
4871098 	adap->quirks = &bcm_iproc_i2c_quirks;
4881099 	adap->dev.parent = &pdev->dev;
....@@ -495,10 +1106,15 @@
4951106 {
4961107 	struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
4971108 
498
-	/* make sure there's no pending interrupt when we remove the adapter */
499
-	writel(0, iproc_i2c->base + IE_OFFSET);
500
-	readl(iproc_i2c->base + IE_OFFSET);
501
-	synchronize_irq(iproc_i2c->irq);
1109
+	if (iproc_i2c->irq) {
1110
+		/*
1111
+		 * Make sure there's no pending interrupt when we remove the
1112
+		 * adapter
1113
+		 */
1114
+		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1115
+		iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1116
+		synchronize_irq(iproc_i2c->irq);
1117
+	}
5021118 
5031119 	i2c_del_adapter(&iproc_i2c->adapter);
5041120 	bcm_iproc_i2c_enable_disable(iproc_i2c, false);
....@@ -512,10 +1128,15 @@
5121128 {
5131129 	struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
5141130 
515
-	/* make sure there's no pending interrupt when we go into suspend */
516
-	writel(0, iproc_i2c->base + IE_OFFSET);
517
-	readl(iproc_i2c->base + IE_OFFSET);
518
-	synchronize_irq(iproc_i2c->irq);
1131
+	if (iproc_i2c->irq) {
1132
+		/*
1133
+		 * Make sure there's no pending interrupt when we go into
1134
+		 * suspend
1135
+		 */
1136
+		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1137
+		iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1138
+		synchronize_irq(iproc_i2c->irq);
1139
+	}
5191140 
5201141 	/* now disable the controller */
5211142 	bcm_iproc_i2c_enable_disable(iproc_i2c, false);
....@@ -538,10 +1159,10 @@
5381159 		return ret;
5391160 
5401161 	/* configure to the desired bus speed */
541
-	val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
542
-	val &= ~(1 << TIM_CFG_MODE_400_SHIFT);
543
-	val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
544
-	writel(val, iproc_i2c->base + TIM_CFG_OFFSET);
1162
+	val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1163
+	val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1164
+	val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1165
+	iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
5451166 
5461167 	bcm_iproc_i2c_enable_disable(iproc_i2c, true);
5471168 
....@@ -558,8 +1179,71 @@
5581179 #define BCM_IPROC_I2C_PM_OPS NULL
5591180 #endif /* CONFIG_PM_SLEEP */
5601181 
1182
+
1183
+static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
1184
+{
1185
+	struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1186
+
1187
+	if (iproc_i2c->slave)
1188
+		return -EBUSY;
1189
+
1190
+	if (slave->flags & I2C_CLIENT_TEN)
1191
+		return -EAFNOSUPPORT;
1192
+
1193
+	iproc_i2c->slave = slave;
1194
+
1195
+	tasklet_init(&iproc_i2c->slave_rx_tasklet, slave_rx_tasklet_fn,
1196
+		     (unsigned long)iproc_i2c);
1197
+
1198
+	bcm_iproc_i2c_slave_init(iproc_i2c, false);
1199
+	return 0;
1200
+}
1201
+
1202
+static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1203
+{
1204
+	u32 tmp;
1205
+	struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1206
+
1207
+	if (!iproc_i2c->slave)
1208
+		return -EINVAL;
1209
+
1210
+	disable_irq(iproc_i2c->irq);
1211
+
1212
+	/* disable all slave interrupts */
1213
+	tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1214
+	tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1215
+			IE_S_ALL_INTERRUPT_SHIFT);
1216
+	iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
1217
+
1218
+	tasklet_kill(&iproc_i2c->slave_rx_tasklet);
1219
+
1220
+	/* Erase the slave address programmed */
1221
+	tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1222
+	tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1223
+	iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
1224
+
1225
+	/* flush TX/RX FIFOs */
1226
+	tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
1227
+	iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, tmp);
1228
+
1229
+	/* clear all pending slave interrupts */
1230
+	iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
1231
+
1232
+	iproc_i2c->slave = NULL;
1233
+
1234
+	enable_irq(iproc_i2c->irq);
1235
+
1236
+	return 0;
1237
+}
1238
+
5611239 static const struct of_device_id bcm_iproc_i2c_of_match[] = {
562
-	{ .compatible = "brcm,iproc-i2c" },
1240
+	{
1241
+		.compatible = "brcm,iproc-i2c",
1242
+		.data = (int *)IPROC_I2C,
1243
+	}, {
1244
+		.compatible = "brcm,iproc-nic-i2c",
1245
+		.data = (int *)IPROC_I2C_NIC,
1246
+	},
5631247 	{ /* sentinel */ }
5641248 };
5651249 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);