forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/gpu/drm/vc4/vc4_regs.h
....@@ -1,27 +1,23 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  *  Copyright © 2014-2015 Broadcom
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
74  */
85 
96 #ifndef VC4_REGS_H
107 #define VC4_REGS_H
118 
9
+#include <linux/bitfield.h>
1210 #include <linux/bitops.h>
1311 
1412 #define VC4_MASK(high, low) ((u32)GENMASK(high, low))
1513 /* Using the GNU statement expression extension */
1614 #define VC4_SET_FIELD(value, field)					\
1715 	({								\
18
-		uint32_t fieldval = (value) << field##_SHIFT;		\
19
-		WARN_ON((fieldval & ~field##_MASK) != 0);		\
20
-		fieldval & field##_MASK;				\
16
+		WARN_ON(!FIELD_FIT(field##_MASK, value));		\
17
+		FIELD_PREP(field##_MASK, value);			\
2118 	 })
2219 
23
-#define VC4_GET_FIELD(word, field) (((word) & field##_MASK) >>		\
24
-				    field##_SHIFT)
20
+#define VC4_GET_FIELD(word, field) FIELD_GET(field##_MASK, word)
2521 
2622 #define V3D_IDENT0   0x00000
2723 # define V3D_EXPECTED_IDENT0 \
....@@ -133,6 +129,8 @@
133129 #define V3D_ERRSTAT  0x00f20
134130 
135131 #define PV_CONTROL				0x00
132
+# define PV5_CONTROL_FIFO_LEVEL_HIGH_MASK	VC4_MASK(26, 25)
133
+# define PV5_CONTROL_FIFO_LEVEL_HIGH_SHIFT	25
136134 # define PV_CONTROL_FORMAT_MASK			VC4_MASK(23, 21)
137135 # define PV_CONTROL_FORMAT_SHIFT		21
138136 # define PV_CONTROL_FORMAT_24			0
....@@ -212,11 +210,16 @@
212210 
213211 #define PV_HACT_ACT				0x30
214212 
213
+#define PV_MUX_CFG				0x34
214
+# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_MASK	VC4_MASK(5, 2)
215
+# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT	2
216
+# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP	8
217
+
218
+#define SCALER_CHANNELS_COUNT			3
219
+
215220 #define SCALER_DISPCTRL                         0x00000000
216221 /* Global register for clock gating the HVS */
217222 # define SCALER_DISPCTRL_ENABLE			BIT(31)
218
-# define SCALER_DISPCTRL_DSP2EISLUR		BIT(15)
219
-# define SCALER_DISPCTRL_DSP1EISLUR		BIT(14)
220223 # define SCALER_DISPCTRL_DSP3_MUX_MASK		VC4_MASK(19, 18)
221224 # define SCALER_DISPCTRL_DSP3_MUX_SHIFT		18
222225 
....@@ -224,45 +227,25 @@
224227  * SCALER_DISPSTAT_IRQDISP0.  Note that short frame contributions are
225228  * always enabled.
226229  */
227
-# define SCALER_DISPCTRL_DSP0EISLUR		BIT(13)
228
-# define SCALER_DISPCTRL_DSP2EIEOLN		BIT(12)
229
-# define SCALER_DISPCTRL_DSP2EIEOF		BIT(11)
230
-# define SCALER_DISPCTRL_DSP1EIEOLN		BIT(10)
231
-# define SCALER_DISPCTRL_DSP1EIEOF		BIT(9)
230
+# define SCALER_DISPCTRL_DSPEISLUR(x)		BIT(13 + (x))
232231 /* Enables Display 0 end-of-line-N contribution to
233232  * SCALER_DISPSTAT_IRQDISP0
234233  */
235
-# define SCALER_DISPCTRL_DSP0EIEOLN		BIT(8)
234
+# define SCALER_DISPCTRL_DSPEIEOLN(x)		BIT(8 + ((x) * 2))
236235 /* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */
237
-# define SCALER_DISPCTRL_DSP0EIEOF		BIT(7)
236
+# define SCALER_DISPCTRL_DSPEIEOF(x)		BIT(7 + ((x) * 2))
238237 
239238 # define SCALER_DISPCTRL_SLVRDEIRQ		BIT(6)
240239 # define SCALER_DISPCTRL_SLVWREIRQ		BIT(5)
241240 # define SCALER_DISPCTRL_DMAEIRQ		BIT(4)
242
-# define SCALER_DISPCTRL_DISP2EIRQ		BIT(3)
243
-# define SCALER_DISPCTRL_DISP1EIRQ		BIT(2)
244241 /* Enables interrupt generation on the enabled EOF/EOLN/EISLUR
245242  * bits and short frames..
246243  */
247
-# define SCALER_DISPCTRL_DISP0EIRQ		BIT(1)
244
+# define SCALER_DISPCTRL_DISPEIRQ(x)		BIT(1 + (x))
248245 /* Enables interrupt generation on scaler profiler interrupt. */
249246 # define SCALER_DISPCTRL_SCLEIRQ		BIT(0)
250247 
251248 #define SCALER_DISPSTAT                         0x00000004
252
-# define SCALER_DISPSTAT_COBLOW2		BIT(29)
253
-# define SCALER_DISPSTAT_EOLN2			BIT(28)
254
-# define SCALER_DISPSTAT_ESFRAME2		BIT(27)
255
-# define SCALER_DISPSTAT_ESLINE2		BIT(26)
256
-# define SCALER_DISPSTAT_EUFLOW2		BIT(25)
257
-# define SCALER_DISPSTAT_EOF2			BIT(24)
258
-
259
-# define SCALER_DISPSTAT_COBLOW1		BIT(21)
260
-# define SCALER_DISPSTAT_EOLN1			BIT(20)
261
-# define SCALER_DISPSTAT_ESFRAME1		BIT(19)
262
-# define SCALER_DISPSTAT_ESLINE1		BIT(18)
263
-# define SCALER_DISPSTAT_EUFLOW1		BIT(17)
264
-# define SCALER_DISPSTAT_EOF1			BIT(16)
265
-
266249 # define SCALER_DISPSTAT_RESP_MASK		VC4_MASK(15, 14)
267250 # define SCALER_DISPSTAT_RESP_SHIFT		14
268251 # define SCALER_DISPSTAT_RESP_OKAY		0
....@@ -270,23 +253,26 @@
270253 # define SCALER_DISPSTAT_RESP_SLVERR		2
271254 # define SCALER_DISPSTAT_RESP_DECERR		3
272255 
273
-# define SCALER_DISPSTAT_COBLOW0		BIT(13)
256
+# define SCALER_DISPSTAT_COBLOW(x)		BIT(13 + ((x) * 8))
274257 /* Set when the DISPEOLN line is done compositing. */
275
-# define SCALER_DISPSTAT_EOLN0			BIT(12)
258
+# define SCALER_DISPSTAT_EOLN(x)		BIT(12 + ((x) * 8))
276259 /* Set when VSTART is seen but there are still pixels in the current
277260  * output line.
278261  */
279
-# define SCALER_DISPSTAT_ESFRAME0		BIT(11)
262
+# define SCALER_DISPSTAT_ESFRAME(x)		BIT(11 + ((x) * 8))
280263 /* Set when HSTART is seen but there are still pixels in the current
281264  * output line.
282265  */
283
-# define SCALER_DISPSTAT_ESLINE0		BIT(10)
266
+# define SCALER_DISPSTAT_ESLINE(x)		BIT(10 + ((x) * 8))
284267 /* Set when the the downstream tries to read from the display FIFO
285268  * while it's empty.
286269  */
287
-# define SCALER_DISPSTAT_EUFLOW0		BIT(9)
270
+# define SCALER_DISPSTAT_EUFLOW(x)		BIT(9 + ((x) * 8))
288271 /* Set when the display mode changes from RUN to EOF */
289
-# define SCALER_DISPSTAT_EOF0			BIT(8)
272
+# define SCALER_DISPSTAT_EOF(x)			BIT(8 + ((x) * 8))
273
+
274
+# define SCALER_DISPSTAT_IRQMASK(x)		VC4_MASK(13 + ((x) * 8), \
275
+							 8 + ((x) * 8))
290276 
291277 /* Set on AXI invalid DMA ID error. */
292278 # define SCALER_DISPSTAT_DMA_ERROR		BIT(7)
....@@ -298,20 +284,28 @@
298284  * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY.
299285  */
300286 # define SCALER_DISPSTAT_IRQDMA			BIT(4)
301
-# define SCALER_DISPSTAT_IRQDISP2		BIT(3)
302
-# define SCALER_DISPSTAT_IRQDISP1		BIT(2)
303287 /* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their
304288  * corresponding interrupt bit is enabled in DISPCTRL.
305289  */
306
-# define SCALER_DISPSTAT_IRQDISP0		BIT(1)
290
+# define SCALER_DISPSTAT_IRQDISP(x)		BIT(1 + (x))
307291 /* On read, the profiler interrupt.  On write, clear *all* interrupt bits. */
308292 # define SCALER_DISPSTAT_IRQSCL			BIT(0)
309293 
310294 #define SCALER_DISPID                           0x00000008
311295 #define SCALER_DISPECTRL                        0x0000000c
296
+# define SCALER_DISPECTRL_DSP2_MUX_SHIFT	31
297
+# define SCALER_DISPECTRL_DSP2_MUX_MASK		VC4_MASK(31, 31)
298
+
312299 #define SCALER_DISPPROF                         0x00000010
300
+
313301 #define SCALER_DISPDITHER                       0x00000014
302
+# define SCALER_DISPDITHER_DSP5_MUX_SHIFT	30
303
+# define SCALER_DISPDITHER_DSP5_MUX_MASK	VC4_MASK(31, 30)
304
+
314305 #define SCALER_DISPEOLN                         0x00000018
306
+# define SCALER_DISPEOLN_DSP4_MUX_SHIFT		30
307
+# define SCALER_DISPEOLN_DSP4_MUX_MASK		VC4_MASK(31, 30)
308
+
315309 #define SCALER_DISPLIST0                        0x00000020
316310 #define SCALER_DISPLIST1                        0x00000024
317311 #define SCALER_DISPLIST2                        0x00000028
....@@ -349,6 +343,20 @@
349343 # define SCALER_DISPCTRLX_WIDTH_SHIFT		12
350344 # define SCALER_DISPCTRLX_HEIGHT_MASK		VC4_MASK(11, 0)
351345 # define SCALER_DISPCTRLX_HEIGHT_SHIFT		0
346
+
347
+# define SCALER5_DISPCTRLX_WIDTH_MASK		VC4_MASK(28, 16)
348
+# define SCALER5_DISPCTRLX_WIDTH_SHIFT		16
349
+/* Generates a single frame when VSTART is seen and stops at the last
350
+ * pixel read from the FIFO.
351
+ */
352
+# define SCALER5_DISPCTRLX_ONESHOT		BIT(15)
353
+/* Processes a single context in the dlist and then task switch,
354
+ * instead of an entire line.
355
+ */
356
+# define SCALER5_DISPCTRLX_ONECTX_MASK		VC4_MASK(14, 13)
357
+# define SCALER5_DISPCTRLX_ONECTX_SHIFT		13
358
+# define SCALER5_DISPCTRLX_HEIGHT_MASK		VC4_MASK(12, 0)
359
+# define SCALER5_DISPCTRLX_HEIGHT_SHIFT		0
352360 
353361 #define SCALER_DISPBKGND0                       0x00000044
354362 # define SCALER_DISPBKGND_AUTOHS		BIT(31)
....@@ -483,32 +491,18 @@
483491 #define SCALER_DLIST_START                      0x00002000
484492 #define SCALER_DLIST_SIZE                       0x00004000
485493 
486
-#define VC4_HDMI_CORE_REV			0x000
494
+#define SCALER5_DLIST_START			0x00004000
487495 
488
-#define VC4_HDMI_SW_RESET_CONTROL		0x004
489496 # define VC4_HDMI_SW_RESET_FORMAT_DETECT	BIT(1)
490497 # define VC4_HDMI_SW_RESET_HDMI			BIT(0)
491498 
492
-#define VC4_HDMI_HOTPLUG_INT			0x008
493
-
494
-#define VC4_HDMI_HOTPLUG			0x00c
495499 # define VC4_HDMI_HOTPLUG_CONNECTED		BIT(0)
496500 
497
-/* 3 bits per field, where each field maps from that corresponding MAI
498
- * bus channel to the given HDMI channel.
499
- */
500
-#define VC4_HDMI_MAI_CHANNEL_MAP		0x090
501
-
502
-#define VC4_HDMI_MAI_CONFIG			0x094
503501 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE		BIT(27)
504502 # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE		BIT(26)
505503 # define VC4_HDMI_MAI_CHANNEL_MASK_MASK			VC4_MASK(15, 0)
506504 # define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT		0
507505 
508
-/* Last received format word on the MAI bus. */
509
-#define VC4_HDMI_MAI_FORMAT			0x098
510
-
511
-#define VC4_HDMI_AUDIO_PACKET_CONFIG		0x09c
512506 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT		BIT(29)
513507 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS	BIT(24)
514508 # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT		BIT(19)
....@@ -522,12 +516,8 @@
522516 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK			VC4_MASK(7, 0)
523517 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT			0
524518 
525
-#define VC4_HDMI_RAM_PACKET_CONFIG		0x0a0
526519 # define VC4_HDMI_RAM_PACKET_ENABLE		BIT(16)
527520 
528
-#define VC4_HDMI_RAM_PACKET_STATUS		0x0a4
529
-
530
-#define VC4_HDMI_CRP_CFG			0x0a8
531521 /* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead
532522  * of pixel clock.
533523  */
....@@ -541,23 +531,12 @@
541531 # define VC4_HDMI_CRP_CFG_N_MASK		VC4_MASK(19, 0)
542532 # define VC4_HDMI_CRP_CFG_N_SHIFT		0
543533 
544
-/* 20-bit fields containing CTS values to be transmitted if !EXTERNAL_CTS_EN */
545
-#define VC4_HDMI_CTS_0				0x0ac
546
-#define VC4_HDMI_CTS_1				0x0b0
547
-/* 20-bit fields containing number of clocks to send CTS0/1 before
548
- * switching to the other one.
549
- */
550
-#define VC4_HDMI_CTS_PERIOD_0			0x0b4
551
-#define VC4_HDMI_CTS_PERIOD_1			0x0b8
552
-
553
-#define VC4_HDMI_HORZA				0x0c4
554534 # define VC4_HDMI_HORZA_VPOS			BIT(14)
555535 # define VC4_HDMI_HORZA_HPOS			BIT(13)
556536 /* Horizontal active pixels (hdisplay). */
557537 # define VC4_HDMI_HORZA_HAP_MASK		VC4_MASK(12, 0)
558538 # define VC4_HDMI_HORZA_HAP_SHIFT		0
559539 
560
-#define VC4_HDMI_HORZB				0x0c8
561540 /* Horizontal pack porch (htotal - hsync_end). */
562541 # define VC4_HDMI_HORZB_HBP_MASK		VC4_MASK(29, 20)
563542 # define VC4_HDMI_HORZB_HBP_SHIFT		20
....@@ -568,7 +547,6 @@
568547 # define VC4_HDMI_HORZB_HFP_MASK		VC4_MASK(9, 0)
569548 # define VC4_HDMI_HORZB_HFP_SHIFT		0
570549 
571
-#define VC4_HDMI_FIFO_CTL			0x05c
572550 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE	BIT(14)
573551 # define VC4_HDMI_FIFO_CTL_USE_EMPTY		BIT(13)
574552 # define VC4_HDMI_FIFO_CTL_ON_VB		BIT(7)
....@@ -581,15 +559,12 @@
581559 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N	BIT(0)
582560 # define VC4_HDMI_FIFO_VALID_WRITE_MASK		0xefff
583561 
584
-#define VC4_HDMI_SCHEDULER_CONTROL		0x0c0
585562 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
586563 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
587564 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT	BIT(3)
588565 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE	BIT(1)
589566 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI	BIT(0)
590567 
591
-#define VC4_HDMI_VERTA0				0x0cc
592
-#define VC4_HDMI_VERTA1				0x0d4
593568 /* Vertical sync pulse (vsync_end - vsync_start). */
594569 # define VC4_HDMI_VERTA_VSP_MASK		VC4_MASK(24, 20)
595570 # define VC4_HDMI_VERTA_VSP_SHIFT		20
....@@ -600,8 +575,6 @@
600575 # define VC4_HDMI_VERTA_VAL_MASK		VC4_MASK(12, 0)
601576 # define VC4_HDMI_VERTA_VAL_SHIFT		0
602577 
603
-#define VC4_HDMI_VERTB0				0x0d0
604
-#define VC4_HDMI_VERTB1				0x0d8
605578 /* Vertical sync pulse offset (for interlaced) */
606579 # define VC4_HDMI_VERTB_VSPO_MASK		VC4_MASK(21, 9)
607580 # define VC4_HDMI_VERTB_VSPO_SHIFT		9
....@@ -609,7 +582,6 @@
609582 # define VC4_HDMI_VERTB_VBP_MASK		VC4_MASK(8, 0)
610583 # define VC4_HDMI_VERTB_VBP_SHIFT		0
611584 
612
-#define VC4_HDMI_CEC_CNTRL_1			0x0e8
613585 /* Set when the transmission has ended. */
614586 # define VC4_HDMI_CEC_TX_EOM			BIT(31)
615587 /* If set, transmission was acked on the 1st or 2nd attempt (only one
....@@ -650,7 +622,6 @@
650622 /* Set these fields to how many bit clock cycles get to that many
651623  * microseconds.
652624  */
653
-#define VC4_HDMI_CEC_CNTRL_2			0x0ec
654625 # define VC4_HDMI_CEC_CNT_TO_1500_US_MASK	VC4_MASK(30, 24)
655626 # define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT	24
656627 # define VC4_HDMI_CEC_CNT_TO_1300_US_MASK	VC4_MASK(23, 17)
....@@ -662,7 +633,6 @@
662633 # define VC4_HDMI_CEC_CNT_TO_400_US_MASK	VC4_MASK(4, 0)
663634 # define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT	0
664635 
665
-#define VC4_HDMI_CEC_CNTRL_3			0x0f0
666636 # define VC4_HDMI_CEC_CNT_TO_2750_US_MASK	VC4_MASK(31, 24)
667637 # define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT	24
668638 # define VC4_HDMI_CEC_CNT_TO_2400_US_MASK	VC4_MASK(23, 16)
....@@ -672,7 +642,6 @@
672642 # define VC4_HDMI_CEC_CNT_TO_1700_US_MASK	VC4_MASK(7, 0)
673643 # define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT	0
674644 
675
-#define VC4_HDMI_CEC_CNTRL_4			0x0f4
676645 # define VC4_HDMI_CEC_CNT_TO_4300_US_MASK	VC4_MASK(31, 24)
677646 # define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT	24
678647 # define VC4_HDMI_CEC_CNT_TO_3900_US_MASK	VC4_MASK(23, 16)
....@@ -682,7 +651,6 @@
682651 # define VC4_HDMI_CEC_CNT_TO_3500_US_MASK	VC4_MASK(7, 0)
683652 # define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT	0
684653 
685
-#define VC4_HDMI_CEC_CNTRL_5			0x0f8
686654 # define VC4_HDMI_CEC_TX_SW_RESET		BIT(27)
687655 # define VC4_HDMI_CEC_RX_SW_RESET		BIT(26)
688656 # define VC4_HDMI_CEC_PAD_SW_RESET		BIT(25)
....@@ -695,39 +663,11 @@
695663 # define VC4_HDMI_CEC_CNT_TO_4500_US_MASK	VC4_MASK(7, 0)
696664 # define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT	0
697665 
698
-/* Transmit data, first byte is low byte of the 32-bit reg.  MSB of
699
- * each byte transmitted first.
700
- */
701
-#define VC4_HDMI_CEC_TX_DATA_1			0x0fc
702
-#define VC4_HDMI_CEC_TX_DATA_2			0x100
703
-#define VC4_HDMI_CEC_TX_DATA_3			0x104
704
-#define VC4_HDMI_CEC_TX_DATA_4			0x108
705
-#define VC4_HDMI_CEC_RX_DATA_1			0x10c
706
-#define VC4_HDMI_CEC_RX_DATA_2			0x110
707
-#define VC4_HDMI_CEC_RX_DATA_3			0x114
708
-#define VC4_HDMI_CEC_RX_DATA_4			0x118
709
-
710
-#define VC4_HDMI_TX_PHY_RESET_CTL		0x2c0
711
-
712
-#define VC4_HDMI_TX_PHY_CTL0			0x2c4
713666 # define VC4_HDMI_TX_PHY_RNG_PWRDN		BIT(25)
714667 
715
-/* Interrupt status bits */
716
-#define VC4_HDMI_CPU_STATUS			0x340
717
-#define VC4_HDMI_CPU_SET			0x344
718
-#define VC4_HDMI_CPU_CLEAR			0x348
719668 # define VC4_HDMI_CPU_CEC			BIT(6)
720669 # define VC4_HDMI_CPU_HOTPLUG			BIT(0)
721670 
722
-#define VC4_HDMI_CPU_MASK_STATUS		0x34c
723
-#define VC4_HDMI_CPU_MASK_SET			0x350
724
-#define VC4_HDMI_CPU_MASK_CLEAR			0x354
725
-
726
-#define VC4_HDMI_GCP(x)				(0x400 + ((x) * 0x4))
727
-#define VC4_HDMI_RAM_PACKET(x)			(0x400 + ((x) * 0x24))
728
-#define VC4_HDMI_PACKET_STRIDE			0x24
729
-
730
-#define VC4_HD_M_CTL				0x00c
731671 /* Debug: Current receive value on the CEC pad. */
732672 # define VC4_HD_CECRXD				BIT(9)
733673 /* Debug: Override CEC output to 0. */
....@@ -737,7 +677,6 @@
737677 # define VC4_HD_M_SW_RST			BIT(2)
738678 # define VC4_HD_M_ENABLE			BIT(0)
739679 
740
-#define VC4_HD_MAI_CTL				0x014
741680 /* Set when audio stream is received at a slower rate than the
742681  * sampling period, so MAI fifo goes empty.  Write 1 to clear.
743682  */
....@@ -762,7 +701,6 @@
762701 /* Single-shot reset bit.  Read value is undefined. */
763702 # define VC4_HD_MAI_CTL_RESET			BIT(0)
764703 
765
-#define VC4_HD_MAI_THR				0x018
766704 # define VC4_HD_MAI_THR_PANICHIGH_MASK		VC4_MASK(29, 24)
767705 # define VC4_HD_MAI_THR_PANICHIGH_SHIFT		24
768706 # define VC4_HD_MAI_THR_PANICLOW_MASK		VC4_MASK(21, 16)
....@@ -772,31 +710,23 @@
772710 # define VC4_HD_MAI_THR_DREQLOW_MASK		VC4_MASK(5, 0)
773711 # define VC4_HD_MAI_THR_DREQLOW_SHIFT		0
774712 
775
-/* Format header to be placed on the MAI data. Unused. */
776
-#define VC4_HD_MAI_FMT				0x01c
777
-
778
-/* Register for DMAing in audio data to be transported over the MAI
779
- * bus to the Falcon core.
780
- */
781
-#define VC4_HD_MAI_DATA				0x020
782
-
783713 /* Divider from HDMI HSM clock to MAI serial clock.  Sampling period
784714  * converges to N / (M + 1) cycles.
785715  */
786
-#define VC4_HD_MAI_SMP				0x02c
787716 # define VC4_HD_MAI_SMP_N_MASK			VC4_MASK(31, 8)
788717 # define VC4_HD_MAI_SMP_N_SHIFT			8
789718 # define VC4_HD_MAI_SMP_M_MASK			VC4_MASK(7, 0)
790719 # define VC4_HD_MAI_SMP_M_SHIFT			0
791720 
792
-#define VC4_HD_VID_CTL				0x038
793721 # define VC4_HD_VID_CTL_ENABLE			BIT(31)
794722 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE	BIT(30)
795723 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET	BIT(29)
796724 # define VC4_HD_VID_CTL_VSYNC_LOW		BIT(28)
797725 # define VC4_HD_VID_CTL_HSYNC_LOW		BIT(27)
726
+# define VC4_HD_VID_CTL_CLRSYNC			BIT(24)
727
+# define VC4_HD_VID_CTL_CLRRGB			BIT(23)
728
+# define VC4_HD_VID_CTL_BLANKPIX		BIT(18)
798729 
799
-#define VC4_HD_CSC_CTL				0x040
800730 # define VC4_HD_CSC_CTL_ORDER_MASK		VC4_MASK(7, 5)
801731 # define VC4_HD_CSC_CTL_ORDER_SHIFT		5
802732 # define VC4_HD_CSC_CTL_ORDER_RGB		0
....@@ -814,14 +744,7 @@
814744 # define VC4_HD_CSC_CTL_RGB2YCC			BIT(1)
815745 # define VC4_HD_CSC_CTL_ENABLE			BIT(0)
816746 
817
-#define VC4_HD_CSC_12_11			0x044
818
-#define VC4_HD_CSC_14_13			0x048
819
-#define VC4_HD_CSC_22_21			0x04c
820
-#define VC4_HD_CSC_24_23			0x050
821
-#define VC4_HD_CSC_32_31			0x054
822
-#define VC4_HD_CSC_34_33			0x058
823
-
824
-#define VC4_HD_FRAME_COUNT			0x068
747
+# define VC4_DVP_HT_CLOCK_STOP_PIXEL		BIT(1)
825748 
826749 /* HVS display list information. */
827750 #define HVS_BOOTLOADER_DLIST_END                32
....@@ -848,6 +771,8 @@
848771 	HVS_PIXEL_FORMAT_PALETTE = 13,
849772 	HVS_PIXEL_FORMAT_YUV444_RGB = 14,
850773 	HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
774
+	HVS_PIXEL_FORMAT_RGBA1010102 = 16,
775
+	HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,
851776 };
852777 
853778 /* Note: the LSB is the rightmost character shown.  Only valid for
....@@ -902,6 +827,10 @@
902827 #define SCALER_CTL0_RGBA_EXPAND_MSB		2
903828 #define SCALER_CTL0_RGBA_EXPAND_ROUND		3
904829 
830
+#define SCALER5_CTL0_ALPHA_EXPAND		BIT(12)
831
+
832
+#define SCALER5_CTL0_RGB_EXPAND			BIT(11)
833
+
905834 #define SCALER_CTL0_SCL1_MASK			VC4_MASK(10, 8)
906835 #define SCALER_CTL0_SCL1_SHIFT			8
907836 
....@@ -919,9 +848,12 @@
919848 
920849 /* Set to indicate no scaling. */
921850 #define SCALER_CTL0_UNITY			BIT(4)
851
+#define SCALER5_CTL0_UNITY			BIT(15)
922852 
923853 #define SCALER_CTL0_PIXEL_FORMAT_MASK		VC4_MASK(3, 0)
924854 #define SCALER_CTL0_PIXEL_FORMAT_SHIFT		0
855
+
856
+#define SCALER5_CTL0_PIXEL_FORMAT_MASK		VC4_MASK(4, 0)
925857 
926858 #define SCALER_POS0_FIXED_ALPHA_MASK		VC4_MASK(31, 24)
927859 #define SCALER_POS0_FIXED_ALPHA_SHIFT		24
....@@ -932,11 +864,47 @@
932864 #define SCALER_POS0_START_X_MASK		VC4_MASK(11, 0)
933865 #define SCALER_POS0_START_X_SHIFT		0
934866 
867
+#define SCALER5_POS0_START_Y_MASK		VC4_MASK(27, 16)
868
+#define SCALER5_POS0_START_Y_SHIFT		16
869
+
870
+#define SCALER5_POS0_START_X_MASK		VC4_MASK(13, 0)
871
+#define SCALER5_POS0_START_X_SHIFT		0
872
+
873
+#define SCALER5_POS0_VFLIP			BIT(31)
874
+#define SCALER5_POS0_HFLIP			BIT(15)
875
+
876
+#define SCALER5_CTL2_ALPHA_MODE_MASK		VC4_MASK(31, 30)
877
+#define SCALER5_CTL2_ALPHA_MODE_SHIFT		30
878
+#define SCALER5_CTL2_ALPHA_MODE_PIPELINE		0
879
+#define SCALER5_CTL2_ALPHA_MODE_FIXED		1
880
+#define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO	2
881
+#define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07	3
882
+
883
+#define SCALER5_CTL2_ALPHA_PREMULT		BIT(29)
884
+
885
+#define SCALER5_CTL2_ALPHA_MIX			BIT(28)
886
+
887
+#define SCALER5_CTL2_ALPHA_LOC			BIT(25)
888
+
889
+#define SCALER5_CTL2_MAP_SEL_MASK		VC4_MASK(18, 17)
890
+#define SCALER5_CTL2_MAP_SEL_SHIFT		17
891
+
892
+#define SCALER5_CTL2_GAMMA			BIT(16)
893
+
894
+#define SCALER5_CTL2_ALPHA_MASK			VC4_MASK(15, 4)
895
+#define SCALER5_CTL2_ALPHA_SHIFT		4
896
+
935897 #define SCALER_POS1_SCL_HEIGHT_MASK		VC4_MASK(27, 16)
936898 #define SCALER_POS1_SCL_HEIGHT_SHIFT		16
937899 
938900 #define SCALER_POS1_SCL_WIDTH_MASK		VC4_MASK(11, 0)
939901 #define SCALER_POS1_SCL_WIDTH_SHIFT		0
902
+
903
+#define SCALER5_POS1_SCL_HEIGHT_MASK		VC4_MASK(28, 16)
904
+#define SCALER5_POS1_SCL_HEIGHT_SHIFT		16
905
+
906
+#define SCALER5_POS1_SCL_WIDTH_MASK		VC4_MASK(12, 0)
907
+#define SCALER5_POS1_SCL_WIDTH_SHIFT		0
940908 
941909 #define SCALER_POS2_ALPHA_MODE_MASK		VC4_MASK(31, 30)
942910 #define SCALER_POS2_ALPHA_MODE_SHIFT		30
....@@ -952,6 +920,12 @@
952920 
953921 #define SCALER_POS2_WIDTH_MASK			VC4_MASK(11, 0)
954922 #define SCALER_POS2_WIDTH_SHIFT			0
923
+
924
+#define SCALER5_POS2_HEIGHT_MASK		VC4_MASK(28, 16)
925
+#define SCALER5_POS2_HEIGHT_SHIFT		16
926
+
927
+#define SCALER5_POS2_WIDTH_MASK			VC4_MASK(12, 0)
928
+#define SCALER5_POS2_WIDTH_SHIFT		0
955929 
956930 /* Color Space Conversion words.  Some values are S2.8 signed
957931  * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
....@@ -1037,14 +1011,18 @@
10371011 #define SCALER_TILE_HEIGHT_MASK			VC4_MASK(15, 0)
10381012 #define SCALER_TILE_HEIGHT_SHIFT		0
10391013 
1014
+/* Common PITCH0 fields */
1015
+#define SCALER_PITCH0_SINK_PIX_MASK		VC4_MASK(31, 26)
1016
+#define SCALER_PITCH0_SINK_PIX_SHIFT		26
1017
+
10401018 /* PITCH0 fields for T-tiled. */
10411019 #define SCALER_PITCH0_TILE_WIDTH_L_MASK		VC4_MASK(22, 16)
10421020 #define SCALER_PITCH0_TILE_WIDTH_L_SHIFT	16
10431021 #define SCALER_PITCH0_TILE_LINE_DIR		BIT(15)
10441022 #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR	BIT(14)
10451023 /* Y offset within a tile. */
1046
-#define SCALER_PITCH0_TILE_Y_OFFSET_MASK	VC4_MASK(13, 7)
1047
-#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT	7
1024
+#define SCALER_PITCH0_TILE_Y_OFFSET_MASK	VC4_MASK(13, 8)
1025
+#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT	8
10481026 #define SCALER_PITCH0_TILE_WIDTH_R_MASK		VC4_MASK(6, 0)
10491027 #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT	0
10501028